CN110211943A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN110211943A
CN110211943A CN201810832374.8A CN201810832374A CN110211943A CN 110211943 A CN110211943 A CN 110211943A CN 201810832374 A CN201810832374 A CN 201810832374A CN 110211943 A CN110211943 A CN 110211943A
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CN
China
Prior art keywords
layer
hole
insulating layer
wiring
face
Prior art date
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Pending
Application number
CN201810832374.8A
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English (en)
Inventor
田嶋尚之
栗田洋一郎
下川一生
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Kioxia Corp
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Toshiba Memory Corp
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Publication date
Application filed by Toshiba Memory Corp filed Critical Toshiba Memory Corp
Publication of CN110211943A publication Critical patent/CN110211943A/zh
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Abstract

本发明的实施方式提供电极层的位置精度较高的半导体装置及其制造方法。本发明的实施方式的半导体装置具备：再配线层；多个凸块，设置在所述再配线层的第1面上；多个芯片，积层在所述再配线层的第2面上；及树脂构件，设置在所述第2面上，覆盖所述多个芯片。所述再配线层具有：绝缘层；配线，设置在所述绝缘层内；第1通孔，设置在所述绝缘层内，与所述配线连接；电极层，设置在所述绝缘层内，由与所述第1通孔的材料不同的金属材料形成，在所述第1面露出，且与所述第1通孔及所述凸块连接；及第2通孔，设置在所述绝缘层内，与所述配线及所述多个芯片连接。所述电极层与所述第2面的距离短于所述第1面与所述第2面的距离。

Description

半导体装置及其制造方法
【相关申请案】
本申请案享有以日本专利申请案2018-34557号(申请日：2018年2月28日)为基础申请案的优先权。本申请案通过参照该基础申请案而包含基础申请案的全部内容。
技术领域
实施方式涉及半导体装置及其制造方法。
背景技术
自先前以来制造如下半导体装置，即，在印刷基板上积层多片存储器芯片，并利用树脂铸模。在印刷基板的下表面接合有凸块，经由该凸块将半导体装置安装于电子设备等。另一方面，近年来，由于要求半导体装置低矮化，因此提出有使用再配线层代替印刷基板的技术。再配线层通过半导体制程形成在支撑基板上，在再配线层上积层芯片之后将支撑基板除去。在再配线层的下表面上设置有电极层，且在该电极层接合有凸块。然而，除去支撑基板之后的再配线层容易产生翘曲，难以精度佳地形成电极层。
发明内容
实施方式提供电极层的位置精度较高的半导体装置及其制造方法。
实施方式的半导体装置具备：再配线层；多个凸块，设置在所述再配线层的第1面上；多个芯片，积层在所述再配线层的第2面上；及树脂构件，设置在所述第2面上，覆盖所述多个芯片。所述再配线层具有：绝缘层；配线，设置在所述绝缘层内；第1通孔，设置在所述绝缘层内，与所述配线连接；电极层，设置在所述绝缘层内，由与所述第1通孔的材料不同的金属材料形成，在所述第1面露出，且与所述第1通孔及所述凸块连接；及第2通孔，设置在所述绝缘层内，与所述配线及所述多个芯片连接。所述电极层与所述第2面的距离短于所述第1面与所述第2面的距离。
实施方式的半导体装置的制造方法具备如下步骤，即：在支撑基板上形成绝缘层、设置在所述绝缘层内且在所述绝缘层的下表面露出的多个第1通孔、设置在所述绝缘层内且与所述多个第1通孔连接的多个配线、及与所述配线连接且在所述绝缘层的上表面露出的多个第2通孔；在所述绝缘层上积层多个芯片，并且将所述多个芯片连接于所述第2通孔；在所述绝缘层上形成覆盖所述多个芯片的树脂构件；将所述支撑基板除去；通过对所述第1通孔的露出面进行蚀刻而在所述绝缘层的下表面形成凹部；在所述凹部内形成包含与所述第1通孔的材料不同的金属材料的电极层；及在所述电极层接合凸块。
附图说明
图1是表示实施方式的半导体装置的剖视图。
图2是表示实施方式的半导体装置的再配线层的一部分的局部放大剖视图。
图3(a)～(d)是表示实施方式的半导体装置的制造方法的剖视图。
图4(a)～(c)是表示实施方式的半导体装置的制造方法的剖视图。
图5(a)～(c)是表示实施方式的半导体装置的制造方法的剖视图。
图6(a)～(c)是表示实施方式的半导体装置的制造方法的剖视图。
图7(a)及(b)是表示实施方式的半导体装置的制造方法的剖视图。
图8是表示实施方式的半导体装置的制造方法的局部放大剖视图。
具体实施方式
以下对实施方式进行说明。
图1是表示本实施方式的半导体装置的剖视图。
图2是表示本实施方式的半导体装置的再配线层的一部分的局部放大剖视图。
如图1所示，本实施方式的半导体装置1中设置有再配线层10。在再配线层10中，设置有包含作为母材的例如有机材料的绝缘层11。此外，在再配线层10中，在绝缘层11内设置有多个配线12、多个通孔13、多个通孔14及多个电极层15。
配线12包含例如金属材料，埋入于绝缘层11内。通孔13包含例如铜(Cu)等金属材料，配置在绝缘层11内，且与配线12连接。以下，在本说明书中，将从配线12向通孔13的方向称为“下”，将其相反方向称为“上”。即，通孔13配置在较配线12更下方。通孔14包含金属材料，例如贵金属，例如镍(Ni)层、钯(Pd)层及金(Au)层的积层体，在绝缘层11内配置在较配线12更上方，且与配线12连接。通孔14在再配线层10的上表面10a露出。
电极层15在绝缘层11内配置在通孔13的下表面上，且与通孔13连接。电极层15在再配线层10的下表面10b露出。电极层15包含与通孔13的材料不同的金属材料，例如包含贵金属。电极层15的厚度为例如数μm(微米)。
此外，在半导体装置1中，在再配线层10上设置有多个半导体芯片20，且这些半导体芯片20沿上下方向积层。半导体芯片20为例如三维NAND型存储器芯片。再配线层10的通孔14与最下段的半导体芯片20通过微凸块21接合。此外，相邻的半导体芯片20彼此通过微凸块22接合。另外，本说明书中“接合”是指机械连结并且电性连接的状态。在再配线层10的上表面10a上设置有树脂构件24。树脂构件24包含树脂材料，积层的半导体芯片20覆盖微凸块21及22。
在半导体装置1中，在再配线层10的下表面10b上设置有凸块26。凸块26包含例如焊料，其直径大于微凸块21及22的直径，例如数百μm。凸块26接合于电极层15的下表面15a(参照图2)。
此外，在再配线层10的下表面10b上搭载有控制用芯片27。控制用芯片27经由微凸块28接合于再配线层10的电极层15。即，多个电极层15中的一部分接合于凸块26，另一部分接合于微凸块28。此外，在再配线层10与控制用芯片27之间，设置有覆盖微凸块28的树脂构件29。
在半导体装置1中，各半导体芯片20的电极(未图示)经由微凸块22及21、通孔14、配线12、通孔13、电极层15及凸块26连接于外部。而且，控制用芯片27作为例如控制多个半导体芯片20与外部之间的信号的交换的介面发挥功能，并且作为控制这些半导体芯片20的动作的控制器发挥功能。
如图2所示，在配线12设置有包含例如铜的本体部12a，且在本体部12a的下表面上设置有铜层12b及钛层12c。另一方面，包含电极层15及通孔13的积层体的形状为倒四棱锥台形状。即，越接近于电极层15则宽度变得越窄。在电极层15中，从通孔13侧依序积层有镍层15b及金属间化合物层15c。镍层15b与通孔13相接，金属间化合物层15c与凸块26相接。金属间化合物层15c包含以例如铜、锡(Sn)及镍(Ni)为主成分的金属间化合物，也可包含钯(Pd)及金(Au)等贵金属。
电极层15与再配线层10的上表面10a的距离L1短于再配线层10的厚度，即再配线层10的下表面10b与上表面10a的距离L2。即，L1<L2。此外，电极层15的下表面15a，即凸块26侧的表面相对于再配线层10的下表面10b凹陷。另外，电极层15的下表面15a也可与再配线层10的下表面10b构成同一平面。换言之，电极层15的下表面15a与再配线层10的上表面10a的距离L3为上述距离L2以下。即，L3≦L2。
其次，对本实施方式的半导体装置的制造方法进行说明。
图3(a)～(d)、图4(a)～(c)、图5(a)～(c)、图6(a)～(c)、图7(a)及(b)是表示本实施方式的半导体装置的制造方法的剖视图。
图8是表示本实施方式的半导体装置的制造方法的局部放大剖视图。
首先，如图3(a)所示，准备支撑基板100。支撑基板100为例如硅晶片或玻璃基板。其次，在支撑基板100的上表面上形成剥离层101。剥离层101包含例如能够溶解于特定化学液的有机材料、通过光照射产生分解反应的有机材料、或施加固定以上的应力则产生剥离的有机材料或者无机材料。其次，在剥离层101上形成钛(Ti)层102，并在该钛层102上形成铜层103。钛层102与支撑基板100的密接性较高。由钛层102及铜层103构成晶种层104。
其次，如图3(b)所示，在晶种层104上形成包含例如有机材料的绝缘层11a。其次，通过例如微影法或激光照射而在绝缘层11a形成贯通孔11b。晶种层104在贯通孔11b的底面露出。
其次，如图3(c)所示，经由晶种层104进行电解镀覆，在贯通孔11b内埋入金属材料例如铜而形成通孔13。此时，铜层103由于导电性较高，因此在大范围形成后述的抗蚀剂图案105的情况下，容易使电解镀覆的厚度均匀化。
其次，如图3(d)所示，在绝缘层11a上形成钛层12c及铜层12b。其次，在铜层12b上形成抗蚀剂图案105。在抗蚀剂图案105通过微影法形成开口部105a。铜层12b在开口部105a的底面露出。其次，将钛层12c及铜层12b作为晶种层进行电解镀覆而将铜埋入于开口部105a内，形成本体部12a。其次，将抗蚀剂图案105除去。接下来，进行蚀刻，将铜层12b及钛层12c中的未被本体部12a覆盖的部分除去。由此，铜层12b及钛层12c俯视下被图案化为与本体部12a相同的形状。由本体部12a及经图案化的铜层12b及钛层12c形成配线12。配线12与通孔13连接。
其次，如图4(a)所示，在绝缘层11a及配线12上形成包含例如有机材料的绝缘层11c。由绝缘层11a及绝缘层11c形成绝缘层11。其次，通过例如微影法或激光照射而在绝缘层11c形成贯通孔11d。配线12在贯通孔11d的底面露出。
其次，如图4(b)所示，通过无电解镀覆法而在配线12的露出面上形成包含贵金属的金属材料，例如依序形成镍层、钯层及金层。由此，在贯通孔11d内形成通孔14。通孔14与配线12连接，并且在绝缘层11a的上表面露出。
其次，如图4(c)所示，在通孔14上经由微凸块21接合半导体芯片20。其次，在该半导体芯片20上，隔着微凸块22积层多个半导体芯片20。由此，在绝缘层11上积层有多个半导体芯片20。多个半导体芯片20的电极(未图示)经由微凸块22及21而与通孔14连接。另外，也可将包含预先经由微凸块22相互接合的多个半导体芯片20的积层体经由微凸块21接合于通孔14。
其次，如图5(a)所示，在绝缘层11上以覆盖包含多个半导体芯片20的积层体的方式成形密封树脂材料，且以例如200℃以下的温度使该树脂材料热硬化，由此形成树脂构件24。
其次，如图5(b)所示，通过使用例如化学液进行溶解，或者通过光照射将剥离层分解而除去剥离层101。或，以超过剥离层101的密接力的力将支撑基板100自剥离层101剥离。由此，将支撑基板100除去而露出晶种层104。
其次，如图5(c)所示，如果在晶种层104上残留有剥离层101的残渣(未图示)则将其除去。其次，通过例如湿式蚀刻法将晶种层104除去。由此，绝缘层11及通孔13露出。
其次，如图6(a)所示，通过例如湿式蚀刻法对通孔13的露出面进行蚀刻。由此，将通孔13的一部分除去而在绝缘层11的下表面形成凹部106。通孔13的残留部在凹部106的底面露出。凹部106的深度为例如数μm。另外，在设通孔13的材料为铜的情况下，通过控制铜蚀刻液的处理条件，能够以1次湿式蚀刻处理除去铜层103的整个表面与通孔13的一部分。
其次，如图6(b)及图8所示，通过例如无电解镀覆法而在通孔13的露出面形成与通孔13的材料不同的金属材料，例如包含贵金属的金属材料，例如依序形成镍层15b、钯层15d及金层15e。由此，在凹部106内形成电极层15。此时，以电极层15的厚度不超过通孔13的除去厚度，即凹部106的深度的方式控制电极材料的成长条件，例如温度或处理时间。由绝缘层11、配线12、通孔13、通孔14及电极层15形成再配线层10。电极层15的下表面15a相对于再配线层10的下表面10b凹陷或为同一平面。
其次，如图6(c)所示，在一部分电极层15经由微凸块28接合控制用芯片27。其次，在再配线层10与控制用芯片27之间，以覆盖微凸块28的方式形成树脂构件29。
其次，如图7(a)所示，在未接合微凸块28的电极层15接合包含例如焊料的凸块26。此时，如图8及图2所示，在接合有凸块26的电极层15中，金层15e及钯层15d扩散于凸块26内而消失。另一方面，在镍层15b与凸块26之间，形成以铜、锡及镍为主成分的金属间化合物层15c。
其次，如图7(b)所示，进行切割而将再配线层10及树脂构件24切断。由此，制造多个半导体装置1。
其次，对本实施方式的效果进行说明。
本实施方式中，在图3(a)～图5(a)所示的步骤中，在支撑基板100上形成绝缘层11、包含半导体芯片20的积层体、及包含树脂构件24等的构造体之后，在图5(b)所示的步骤中将支撑基板100除去。此外，在图5(c)～图7(a)所示的步骤中，形成电极层15及凸块26。由此，可经由再配线层10将半导体芯片20连接于凸块26。其结果，与使用印刷基板的情况相比，可实现半导体装置1的低矮化。
此外，当在图5(b)所示的步骤中将支撑基板100除去时存在如下情况，即，因主要在半导体芯片20产生的应力、及使树脂构件24热硬化时的应力而导致在绝缘层11、包含半导体芯片20的积层体、包含树脂构件24等的构造体产生翘曲。如果产生翘曲，则通孔13的位置自设计位置偏移。然而，本实施方式中，在图6(a)所示的步骤中，通过对通孔13进行蚀刻而形成凹部106，在图6(b)所示的步骤中，在凹部106内通过无电解镀覆法而形成电极层15。如此，在本实施方式中，即便在通孔13的位置偏移的情况下，也可自行对准地形成电极层15，因此电极层15的位置精度较高。此外，由于电极层15形成在凹部106内，因此不会随着电极层15的形成而电极层15彼此接近，可抑制电极层15间的短路。
相对于此，假若欲通过例如微影法及RIE(Reactive Ion Etching：反应性离子蚀刻)法等与通孔13独立地形成电极层15，则在因构造体的翘曲而通孔13的位置偏移的情况下，难以进行电极层15与通孔13的位置对准。此外，假若不形成凹部106而形成电极层15，则随着电极层15的成长，电极层15也在水平方向扩展，因此电极层15彼此接近而存在短路的可能性。为了切实地防止电极层15彼此的短路，在设计阶段必须预先使电极层15间的距离充分长，从而妨碍半导体装置1的小型化。
根据以上说明的实施方式，可实现电极层的位置精度较高的半导体装置及其制造方法。
以上，对本发明的几个实施方式进行了说明，但这些实施方式是作为示例提出，并未意图限定发明的范围。这些新颖的实施方式能够以其他各种形态实施，可在不脱离发明要旨的范围进行各种省略、替换、变更。这些实施方式或其变化包含在发明的范围或要旨中，并且包含在权利要求书中所记载的发明及其等价物的范围。
[符号的说明]
1：半导体装置
10：再配线层
10a：上表面
10b：下表面
11：绝缘层
11a：绝缘层
11b：贯通孔
11c：绝缘层
11d：贯通孔
12：配线
12a：本体部
12b：铜层
12c：钛层
13：通孔
14：通孔
15：电极层
15a：下表面
15b：镍层
15c：金属间化合物层
15d：钯层
15e：金层
20：半导体芯片
21、22：微凸块
24：树脂构件
26：凸块
27：控制用芯片
28：微凸块
29：树脂构件
100：支撑基板
101：剥离层
102：钛层
103：铜层
104：晶种层
105：抗蚀剂图案
105a：开口部
106：凹部
L1、L2、L3：距离

Claims (6)

1.一种半导体装置，其具备：
再配线层；
多个凸块，设置在所述再配线层的第1面上；
多个芯片，积层在所述再配线层的第2面上；及
树脂构件，设置在所述第2面上，覆盖所述多个芯片；且
所述再配线层具有：
绝缘层；
配线，设置在所述绝缘层内；
第1通孔，设置在所述绝缘层内，与所述配线连接；
电极层，设置在所述绝缘层内，由与所述第1通孔的材料不同的金属材料形成，在所述第1面露出，且与所述第1通孔及所述凸块连接；及
第2通孔，设置在所述绝缘层内，与所述配线及所述多个芯片连接；且
所述电极层与所述第2面的距离短于所述第1面与所述第2面的距离。
2.根据权利要求1所述的半导体装置，其中所述电极层的所述凸块侧的表面与所述第1面构成同一平面，或相对于所述第1面凹陷。
3.根据权利要求1或2所述的半导体装置，其中所述电极层包含贵金属。
4.根据权利要求1或2所述的半导体装置，其进而具备设置在所述第1面上且与所述配线连接的控制用芯片。
5.一种半导体装置的制造方法，其具备如下步骤，即：
在支撑基板上，形成绝缘层、设置在所述绝缘层内且在所述绝缘层的下表面露出的多个第1通孔、设置在所述绝缘层内且与所述多个第1通孔连接的多个配线、及与所述配线连接且在所述绝缘层的上表面露出的多个第2通孔；
在所述绝缘层上积层多个芯片，并且将所述多个芯片连接于所述第2通孔；
在所述绝缘层上形成覆盖所述多个芯片的树脂构件；
将所述支撑基板除去；
通过对所述第1通孔的露出面进行蚀刻而在所述绝缘层的下表面形成凹部；
在所述凹部内形成包含与所述第1通孔的材料不同的金属材料的电极层；及
在所述电极层接合凸块。
6.根据权利要求5所述的半导体装置的制造方法，其中形成所述电极层的步骤具有如下步骤，即，在所述第1通孔的露出面无电解镀覆所述金属材料。
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