CN102299115A - 具有包含势垒金属的凸块组合件的晶片级封装(wlp)装置 - Google Patents

具有包含势垒金属的凸块组合件的晶片级封装(wlp)装置 Download PDF

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CN102299115A
CN102299115A CN2011101768236A CN201110176823A CN102299115A CN 102299115 A CN102299115 A CN 102299115A CN 2011101768236 A CN2011101768236 A CN 2011101768236A CN 201110176823 A CN201110176823 A CN 201110176823A CN 102299115 A CN102299115 A CN 102299115A
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Prior art keywords
barrier layer
oxidation
cap
cam unit
copper post
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CN2011101768236A
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周条
阿尔卡迪·V·萨莫伊洛夫
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Maxim Integrated Products Inc
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Maxim Integrated Products Inc
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Publication of CN102299115A publication Critical patent/CN102299115A/zh
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Abstract

本发明涉及WLP半导体装置，其包含凸块组合件，所述凸块组合件具有用于抑制所述凸块组合件内的电迁移的势垒层。在一实施方案中，所述凸块组合件包含形成于所述WLP装置的集成电路芯片上的铜柱。在所述铜柱的外表面上提供由例如镍(Ni)等金属形成的势垒层以抑制所述凸块组合件中的电迁移。在所述势垒层上方提供由例如锡(Sn)等金属形成的防氧化帽。在所述防氧化帽上方形成焊料凸块。所述防氧化帽抑制在所述凸块组合件的制作期间所述势垒层的氧化。

Description

具有包含势垒金属的凸块组合件的晶片级封装(WLP)装置
技术领域
本发明涉及半导体装置的制造。
背景技术
半导体装置的制造中所使用的传统制作工艺采用微光刻将集成电路图案化到由例如硅或类似材料等半导体形成的圆形晶片上。通常，将经图案化的晶片分割成个别集成电路芯片或裸片以将所述集成电路彼此分离。使用各种封装技术来组装或封装所述个别集成电路芯片以形成可安装到印刷电路板的半导体装置。
多年来，封装技术已演变而开发出更小、更廉价、更可靠且更环保的封装。举例来说，已开发出芯片尺寸封装技术，其采用具有不大于集成电路芯片的面积的1.2倍的表面积的直接表面可安装封装。晶片级封装是一种借以在单个化之前在晶片级上封装集成电路芯片的新兴芯片尺寸封装技术，其囊括了多种技术。晶片级封装将晶片制作工艺扩展为包含装置互连及装置保护过程。因此，晶片级封装通过允许在晶片级上集成晶片制作、封装、测试及老化过程而流线化制造工艺。
发明内容
描述晶片级封装(WLP)装置，其包含凸块组合件，所述凸块组合件包括经配置以抑制凸块组合件内的电迁移的势垒层。在一实施方案中，所述凸块组合件包含形成于所述WLP装置的集成电路芯片上的铜柱。给所述铜柱的外表面施加由例如镍(Ni)等金属形成的势垒层以抑制所述凸块组合件中的电迁移。在所述势垒层上方施加由例如锡(Sn)等金属形成的防氧化帽。所述防氧化帽抑制在所述凸块组合件的制作期间所述势垒层的氧化且充当可在环氧树脂研磨期间被研磨使得所述势垒层的厚度不受影响的牺牲层。
提供此发明内容以按简化形式引入下文在具体实施方式中进一步描述的概念精选。此发明内容并不打算识别所请求标的物的关键特征或实质特征，也不打算用于协助确定所请求标的物的范围。
附图说明
参考附图描述详细说明。在说明中的不同实例及各图中使用相同参考编号可指示类似或等同的物项。
图1是图解说明根据本发明的实例性实施方案的WLP装置的示意性部分横截面侧视立面图。
图2是图解说明安装到电子装置的印刷电路板的图1的WLP装置的示意性部分横截面立面图。
图3是图解说明用于制作例如图1中所示的WLP装置的WLP装置的实例性实施方案中的工艺的流程图。
图4A到图4K是图解说明根据图3中所示的工艺制作例如图1中所示的装置的WLP装置的示意性部分横截面侧视立面图。
具体实施方式
概述
电迁移减轻是WLP装置的制造中的重要设计考虑因素。电迁移涉及例如铜等导体的金属原子的渐进输送，这是由于流动穿过所述导体的电流所致。此原子输送可致使在所述导体内形成空洞、裂缝或其它缺陷。特定来说，WLP装置的凸块组合件(例如，焊料接合处)内的电迁移可导致凸块组合件的过早故障，从而减小WLP装置的可靠性。
一些WLP装置包括采用铜(Cu)柱结构的凸块组合件，其中所述凸块组合件包含沉积在再分布层(RDL)垫上的铜柱，所述铜柱上方形成有焊料凸块。在高温度及/或高电流的条件下，电迁移可致使铜柱的一部分溶解到凸块组合件的焊料中而呈铜-锡金属间化合物(IMC)的形式。裂缝、空洞或其它缺陷可在此金属间化合物内形成，从而导致凸块组合件的故障。
为了抑制WLP装置的采用铜柱结构的凸块组合件中的电迁移，可给铜柱的外表面施加由镍(Ni)形成的势垒层，使得所述势垒层变为焊料的润湿表面。镍与焊料中的锡的电迁移反应速率低于形成铜柱的铜与锡的电迁移反应速率。因此，镍势垒层的施加增加凸块组合件的电迁移寿命。
然而，已发现给具有铜柱结构的凸块组合件施加镍势垒层显著减小WLP装置的坠落测试(DT)可靠性。更具体来说，通常已使用无电镀敷工艺给铜柱施加镍势垒层(无电镍)。因此，磷(P)固有地存在于势垒层的镍中。此磷可阻碍焊料到镍势垒层的接合，从而导致弱化的连接及不良的坠落测试可靠性性能。
为了避免凸块组合件中的此磷相关弱性，可使用电解镀敷工艺来施加镍势垒层(电解镍)。然而，由于用来形成铜柱的镀敷工艺可展现出大的变化，因此可难以控制电解镍的厚度。因此，在环氧树脂研磨工艺期间可能将镍研磨掉，从而减小势垒层的有效性。此外，在采用电解镍的情况下，可在施加形成焊料凸块的焊料之前在势垒层的表面中发生氧化。此氧化(不容易通过常规技术(例如，通过给势垒层的表面施加助焊剂)移除)可致使焊料的润湿表面处的过量焊料空洞形成，从而阻碍在焊料与镍势垒层之间形成良好的接合。
因此，描述用于制作具有采用经配置以改进电迁移可靠性同时维持充足坠落测试可靠性的铜柱结构的凸块组合件的WLP装置的技术。在一个或一个以上实施方案中，给所述凸块组合件的铜柱施加使用电解镀敷工艺由例如镍(Ni)等金属形成的势垒层以抑制焊料凸块组合件的焊料中的电迁移。接着在所述势垒层上方施加由例如锡(Sn)等金属形成的防氧化帽。在WLP装置的制作期间，防氧化帽抑制在施加形成凸块组合件的焊料凸块的焊料之前势垒层的氧化，以便在焊料与下伏势垒层之间提供强互连。所述防氧化帽还充当可在环氧树脂研磨期间被研磨使得势垒层的厚度不受影响的牺牲层。以此方式，所得凸块组合件由于充足势垒层的添加而提供良好的电迁移减轻性能，而不会牺牲坠落测试可靠性。
实例性实施方案
图1图解说明根据本发明的实例性实施方案的WLP装置100的截面。如所展示，WLP装置100包含由衬底104构成的集成电路芯片102，衬底104的表面108中形成有一个或一个以上集成电路106。再分布结构110提供于表面108上在集成电路106上方。再分布结构110将集成电路106的外围RDL垫再分布成部署于集成电路芯片102的表面上方的一个或一个以上RDL垫112区域阵列。在所示的实施方案中，再分布结构110包含钝化层114及再分布层116。钝化层114形成于集成电路106上方以分离集成电路106与后续导电层(例如，再分布层116)。钝化层114可由例如聚酰亚胺树脂等聚合物材料、例如苯并环丁烯聚合物(BCB)、二氧化硅(SiO2)等电介质材料形成。再分布层116经图案化以形成RDL垫112且提供集成电路106的外围RDL垫到RDL垫112的电互连。在若干实施例中，再分布层116由铜(Cu)形成。然而，本发明涵盖再分布层116可由例如铝(Al)等其它金属、其它导电材料等等形成。
再分布结构110的配置及/或由再分布结构110提供的RDL垫112的数目及配置可取决于集成电路106的复杂性及配置、集成电路芯片102的大小及形状等等而变化。RDL垫112提供通过其将集成电路106互连到例如印刷电路板等外部组件的电触点。图2图解说明安装到电子装置的印刷电路板118的图1的WLP装置100。
WLP装置100包含一个或一个以上凸块组合件120以供设RDL垫112与形成于印刷电路板118的表面124上的对应垫122之间的机械及/或电互连。如所展示，WLP装置100包括采用铜(Cu)柱结构的凸块组合件120。因此，凸块组合件120采用形成于RDL垫112上的铜柱126。在一实例中，铜柱126可具有约45μm的厚度。然而，本发明涵盖具有不同厚度的铜柱126的形成。此外，在一些实施例中，可在铜柱126下方给RDL垫112施加粘合/势垒/籽晶层以改进互连界面的可靠性。
势垒层128提供于铜柱126的外表面130上。如先前所描述，势垒层128充当抑制(例如，消除、大致减少或减少)凸块组合件120内的电迁移的势垒。在若干实施例中，势垒层128由使用适合电解镀敷工艺沉积在铜柱126的外表面130上方的电解镍(Ni)形成。然而，本发明涵盖势垒层128可由例如钯(Pd)等其它金属形成。如所展示，势垒层128可至少大致覆盖铜柱126的外表面130且可具有足以抑制凸块组合件120中的电迁移的厚度。在一实例中，势垒层128可具有约10μm的厚度。然而，本发明涵盖具有不同厚度的势垒层128的施加。
防氧化帽132提供于势垒层128上方。如所展示，防氧化帽132可至少大致覆盖势垒层128的外表面134以抑制在凸块组合件120的制作期间势垒层128的氧化，如下文中更详细论述。在一个或一个以上实施例中，防氧化帽132由锡(Sn)形成。然而，在一些实施例中，本发明涵盖防氧化帽132可由可包含例如银(Ag)、铜(Cu)等等其它金属的锡合金形成。
焊料凸块136提供于防氧化帽132上方。在一个或一个以上实施例中，焊料凸块136可由例如锡-银-铜(Sn-Ag-Cu)合金焊料(即，SAC)、锡-银(Sn-Ag)合金焊料、锡-铜(Sn-Cu)合金焊料等等无铅焊料制作而成。举例来说，焊料凸块136可具有多种SAC组成。在一实例中，焊料凸块136可为SAC305(Sn3.0Ag0.5Cu)合金焊料、SAC405(Sn3.8Ag0.8Cu)合金焊料。可能有其它实例。然而，本发明涵盖可使用锡-铅(PbSn)焊料。下文更详细地描述用于使用晶片级封装技术来形成凸块组合件120的实例性工艺。
在图1及图2中，将防氧化帽132及焊料凸块136展示为所图解说明的凸块组合件120的不同组件或层。然而，将了解所述焊料凸块的焊料138由大比例的锡构成。因此，在一些实例中，防氧化帽132的锡可被至少部分地消耗在形成于焊料凸块136的焊料与势垒层128之间的镍-锡金属间化合物(IMC)中，且在回流之后与所述焊料汞合。因此，本发明涵盖，在此些实例中，在防氧化帽132与焊料凸块136之间明显边界可能为不可识别的。
在铜柱126之间于再分布结构110上方施加环氧树脂(聚环氧化物)138以保护再分布结构110并使其绝缘，且提供对铜柱126、势垒层128及防氧化帽132的机械支撑。给集成电路芯片102的与再分布结构110相对的表面142施加背侧涂层140以保护集成电路芯片102以免碎裂。
实例性制作工艺
图3图解说明采用晶片级封装技术来制作例如图1及图2中所示的WLP装置100的半导体装置的实例性工艺200。在所图解说明的工艺200中，在分割半导体晶片之前在所述晶片上形成具有铜(Cu)柱结构的凸块组合件。如所展示，首先使用微光刻技术处理所述半导体晶片(框202)以在所述晶片的表面中形成集成电路。图4A到图4K中图解说明实例性半导体晶片300的一部分以图解说明实例性凸块组合件302的形成。如所展示，在经处理时，半导体晶片300包含衬底304，衬底304的表面308中形成有一个或一个以上集成电路306。衬底304经配置以被分割(切割)成多个集成电路芯片310。在所图解说明的实施方案中，衬底304由硅制作而成。然而，本发明涵盖衬底304可代替地由例如锗、砷化镓、碳化硅等等其它半导体材料制作而成。
在所述晶片的表面上于所述集成电路上方形成再分布结构(框204)。图4A图解说明实例性再分布结构312的形成。如所展示，再分布结构312可具有将集成电路306的外围RDL垫再分布成部署于半导体晶片300的表面316上方的RDL垫314的多个层。举例来说，在所图解说明的实施方案中，将再分布结构312描绘为包含钝化层318及再分布层320。在集成电路306上方形成钝化层318以分离集成电路306与例如再分布层320等后续导电层。在若干实施例中，钝化层318可由例如聚酰亚胺等聚合物材料形成。然而，本发明涵盖所述钝化层还可由例如苯并环丁烯聚合物(BCB)、二氧化硅(SiO2)等其它电介质材料形成。在一实例中，钝化层318可具有约4μm的厚度。然而，本发明涵盖具有不同厚度的钝化层318的施加。
在钝化层318上方施加再分布层320。在若干实施例中，再分布层320由使用适合电镀工艺镀敷在钝化层318上方的铜(Cu)形成。然而，本发明涵盖再分布层320可由例如多晶硅等其它导电材料、例如铝的金属等等(使用适合于所述材料的工艺来施加的)形成。对再分布层320进行图案化以形成RDL垫314并提供集成电路306的外围接合垫到RDL垫314的电互连。举例来说，电镀工艺可采用施加给晶片300的表面的掩模322来对铜进行图案化以形成RDL垫314及再分布层320的任何其它互连结构。
接着在所述晶片上于所述再分布结构的RDL垫上方形成铜(Cu)柱(框206)。举例来说，如图4B中所示，可在再分布结构312上方给半导体晶片300施加第二掩模324。第二掩模324包含形成于再分布层320的RDL垫314上方的孔口326，所述孔口经确定大小及经成形以促进铜柱328的形成(参见图4C)。如所展示，第二掩模324可形成于在再分布层320的形成中使用的第一掩模322上方。然而，本发明涵盖，在一些实施方案中，可代替地在施加第二掩模324之前移除第一掩模322。在一个或一个以上实施例中，掩模322、324中的任一者或两者可由使用旋涂工艺施加给半导体晶片300并使用适合光学光刻技术图案化的光致抗蚀剂形成。然而，本发明涵盖掩模322、324可使用其它工艺由其它材料形成。在第二掩模324的孔口326内沉积铜330以形成如图4C中所示的铜柱328。在一个或一个以上实施例中，使用适合电镀工艺将铜镀敷到再分布层的RDL垫314上。然而，本发明涵盖可使用例如溅镀等等其它工艺来沉积铜。在一实例中，镀敷所述铜以形成具有约45μm的高度的铜柱328。然而，本发明涵盖具有不同高度的铜柱328的施加。
接下来，给所述铜柱施加势垒层(框208)。如图4D中所示，势垒层332至少大致覆盖所图解说明的铜柱328的外表面334。在一个或一个以上实施例中，势垒层332由利用适合电解镀敷工艺沉积在形成于第二掩模324中的孔口326内在铜柱328的外表面334上方的电解镍(Ni)形成。然而，本发明涵盖，在一些实施例中，势垒层128可由例如钯等等其它金属形成。在一实例中，镀敷镍以形成具有约10μm的厚度的势垒层332。然而，本发明涵盖具有不同厚度的势垒层332的施加。
接着给所述铜柱上方的势垒层施加防氧化帽(框210)。如图4E中所示，防氧化帽336可至少大致覆盖势垒层332的外表面338以抑制在对半导体晶片300执行的剩余制作操作期间势垒层332的氧化。在一个或一个以上实施例中，防氧化帽336由使用适合电镀镀敷工艺沉积在势垒层332的外表面338上的锡(Sn)形成。然而，本发明涵盖，在一些实施例中，防氧化帽336可由使用适合于所施加材料的工艺施加的可包含例如(Ag)、铜(Cu)等等其它金属的锡合金形成。在一实例中，可镀敷锡以形成具有约15μm的厚度(在环氧树脂研磨之前)的防氧化帽336。然而，本发明涵盖具有不同厚度的防氧化帽336的施加。
接下来，给所述晶片施加环氧树脂(聚环氧化物)(框212)。举例来说，如图4F中所示，首先从半导体晶片300移除掩模322及324(图4A到图4E)，从而暴露其上形成有相关联势垒层332及防氧化帽336的铜柱328。如图4G中所示，接着在再分布结构312上方于铜柱328(以及相关联势垒层332及防氧化帽336)之间及其上方施加环氧树脂340，以保护再分布结构312并使其绝缘且提供对铜柱328、势垒层332及防氧化帽336的机械支撑。
图4H图解说明在环氧树脂340及/或背侧涂层342的固化及研磨之后的半导体晶片300。如所展示，已采用环氧树脂研磨工艺来暴露防氧化帽336。在环氧树脂研磨期间，防氧化帽336可充当可被研磨(代替势垒层332的镍)使得势垒层332的厚度不受影响的牺牲层。在一实例中，环氧树脂340在环氧树脂研磨之后可具有约70μm的厚度。
可使所述晶片变薄(框214)。举例来说，可使所述晶片经受背磨或背部抛磨工艺、环氧树脂研磨工艺等等。可给所述晶片的与所述再分布结构相对的表面(所述表面可能已经受背磨或背部抛磨工艺)施加背侧涂层(框216)以保护背部表面。在一个或一个以上实施例中，所述背侧涂层可包括使用例如模板印刷、丝网印刷、旋涂等等沉积技术施加的环氧树脂(聚环氧化物)。进一步使所述晶片固化(框218)以使所述背侧涂层硬化。背侧涂层342可具有约25μm的厚度。然而，本发明涵盖具有不同厚度的环氧树脂340及/或背侧涂层342的施加。
接下来，在所述铜柱的防氧化帽上形成焊料凸块(框220)。可以多种方式来形成所述焊料凸块。在本文中所描述的实施方案中，使用滴球工艺来形成所述焊料凸块。因此，在以下论述中，描述一般滴球工艺的工艺操作特性。然而，本发明涵盖所使用的特定制作工艺可包含其它工艺操作而不背离本发明的范围及精神。此外，本发明涵盖可使用例如焊料膏印刷、蒸发、电镀、喷射、螺柱凸块形成等等其它技术来形成所述焊料凸块。
在如图3中所图解说明的滴球工艺中，首先给铜柱的防氧化帽施加助焊剂(框222)。助焊剂346(图4I中所图解说明)从防氧化帽336(其可为锡或锡合金)的表面348移除氧化物，且使焊料(例如，焊料球350)在回流之前保持到防氧化帽336。可使用多种施加技术来施加助焊剂346。举例来说，在一个或一个以上实施例中，可使用丝网印刷工艺来施加助焊剂346。
接着将焊料球(球体)放置(框224)到所述助焊剂上。可在每一凸块组合件的铜柱上放置焊料球。图4J图解说明在移除放置模板之后经由助焊剂346附加到防氧化帽336的焊料球350。
接下来，执行焊料回流(框226)。在回流期间，使晶片经受受控制的热(例如，经由焊料回流炉)，其使所述焊料球熔化，从而将焊料紧固到防氧化帽及/或势垒层。图4K图解说明在焊料回流之后的半导体晶片300。在图4K中，焊料球350已经回流以形成至少大致润湿防氧化帽336的整个表面348及/或势垒层332的焊料凸块352。也已移除在回流之后来自助焊剂346(图4J)的残余物。由于焊料含有高比例的锡，因此防氧化帽336的锡可至少部分地与焊料凸块352的焊料汞合。因此，本发明涵盖，在回流之后，在防氧化帽336与焊料凸块352之间可不存在明显边界。
在若干实施方案中，在发生势垒层332的任何实质氧化(例如，到以下程度的氧化：使得所述氧化实质上影响防氧化帽336到势垒层332(例如，锡到镍)及/或防氧化帽336到焊料凸块352的焊料(例如，SAC到锡)的附着的强度)之前在所述势垒层上方沉积防氧化帽336。然而，本发明涵盖，可在防氧化帽336的施加之前发生势垒层332的某一氧化。此外，本发明涵盖，可在防氧化帽336的施加之前从势垒层332移除氧化物。
如图4K中所示，防氧化帽336的施加允许环氧树脂340延伸超过势垒层332的外表面334，使得势垒层332被嵌入于环氧树脂340内在防氧化帽336下方。以此方式，防氧化帽336与环氧树脂340协作以防止氧到达势垒层金属(例如，镍)。在一实例中，防氧化帽336可在环氧树脂背磨之后具有至少约5μm且最高达约15μm的厚度。因此，势垒层332可被嵌入于防氧化帽336下方距环氧树脂340的表面354达至少约5μm的深度。如所提及，在回流之后，防氧化帽336的锡可被至少部分地消耗在形成于焊料凸块352与势垒层332之间的镍-焊料金属间化合物(IMC)中。因此，如图4K中所示，焊料凸块352的包含至少部分地消耗的防氧化帽336的部分可在环氧树脂340的表面354下面延伸，使得环氧树脂340可供设对焊料凸块352的额外机械支撑。
可接着分割(例如，切割)所述晶片以分离出个别WLP装置(框228)。在图4K中，图解说明在回流工艺之后准备使用分割工艺进行切割以形成例如图1及图2中所图解说明的WLP装置100的装置的半导体晶片300。
结论
虽然已以专用于结构特征及/或工艺操作的语言描述了标的物，但应理解，在所附权利要求书中界定的标的物未必限定于上述特定特征或动作。而是，上述特定特征及动作是作为实施权利要求书的实例性形式而揭示。

Claims (20)

1.一种WLP装置，其包括：
集成电路芯片；及
凸块组合件，其形成于所述集成电路芯片上，所述凸块组合件包含：铜柱，其具有外表面；势垒层，其形成于所述外表面上以抑制所述凸块组合件中的电迁移；防氧化帽，其形成于所述势垒层上方；及焊料凸块，其形成于所述防氧化帽上。
2.根据权利要求1所述的WLP装置，其中所述势垒层包括镍(Ni)。
3.根据权利要求2所述的WLP装置，其中所述防氧化帽包括锡(Sn)。
4.根据权利要求3所述的WLP装置，其中所述焊料凸块包括含有锡(Sn)的焊料。
5.根据权利要求4所述的WLP装置，其中所述焊料为SAC焊料。
6.根据权利要求4所述的WLP装置，其中所述防氧化帽的所述锡被至少部分地消耗在形成于所述焊料凸块与所述势垒层之间的镍-焊料金属间化合物中。
7.根据权利要求6所述的WLP装置，其中所述防氧化帽经配置以抑制在所述凸块组合件的制作期间所述势垒层的氧化。
8.一种电子装置，其包括：
印刷电路板；及
WLP装置，所述晶片级芯片尺寸封装装置包含集成电路芯片，所述集成电路芯上形成有凸块组合件以用于将所述WLP装置连接到所述印刷电路板，所述凸块组合件包含：铜柱，其具有外表面；势垒层，其形成于所述铜柱的所述外表面上以抑制所述凸块组合件中的电迁移；防氧化帽，其形成于所述势垒层上方；及焊料凸块，其形成于锡帽上方。
9.根据权利要求8所述的电子装置，其中所述势垒层包括镍(Ni)。
10.根据权利要求9所述的电子装置，其中所述防氧化帽包括锡(Sn)。
11.根据权利要求10所述的电子装置，其中所述焊料凸块包括含有锡(Sn)的焊料。
12.根据权利要求11所述的电子装置，其中所述焊料包括SAC焊料。
13.根据权利要求12所述的电子装置，其中所述防氧化帽的所述锡被至少部分地消耗在形成于所述焊料凸块与所述势垒层之间的镍-焊料金属间化合物中。
14.根据权利要求13所述的电子装置，其中所述防氧化帽经配置以抑制在所述凸块组合件的制作期间所述势垒层的氧化。
15.一种方法，其包括：
在经配置以被分割成若干集成电路芯片的半导体晶片的再分布层(RDL)垫上形成铜柱，所述铜柱中的每一者具有外表面；
在所述铜柱中的每一者的所述外表面上施加势垒层；
在所述铜柱中的每一者上的所述势垒层上方施加防氧化帽以抑制所述势垒层的氧化；
在所述防氧化帽上形成焊料凸块以在所述半导体晶片上形成凸块组合件，及
分割所述晶片以从所述晶片分离出集成电路芯片，所述集成电路芯片包含至少一个凸块组合件。
16.根据权利要求15所述的方法，其中所述势垒层的所述施加包括使用电解工艺在所述铜柱中的每一者的所述外表面上镀敷镍(Ni)。
17.根据权利要求16所述的方法，其中所述防氧化帽的所述施加包括在所述势垒层上镀敷锡(Sn)。
18.根据权利要求17所述的方法，其进一步包括：
在所述铜柱的所述形成之前给所述半导体晶片施加掩模，所述掩模经形成以包含暴露所述RDL垫的孔口；及
在所述防氧化帽的所述施加之后移除所述掩模。
19.根据权利要求17所述的方法，其中所述焊料凸块的所述形成包括：
给所述防氧化帽施加助焊剂；
在施加给每一防氧化帽的所述助焊剂上放置焊料球；及
使所述焊料球回流以形成所述焊料凸块。
20.根据权利要求17所述的方法，其进一步包括：
在所述防氧化帽的所述形成之后使所述半导体晶片变薄；及
给所述变薄的半导体晶片施加背侧涂层。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102543898A (zh) * 2012-01-17 2012-07-04 南通富士通微电子股份有限公司 一种柱状凸点封装结构
CN110211943A (zh) * 2018-02-28 2019-09-06 东芝存储器株式会社 半导体装置及其制造方法

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8598030B2 (en) * 2010-08-12 2013-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Process for making conductive post with footing profile
TWI467718B (zh) * 2011-12-30 2015-01-01 Ind Tech Res Inst 凸塊結構以及電子封裝接點結構及其製造方法
TWI458063B (zh) * 2012-04-03 2014-10-21 Advanced Semiconductor Eng 半導體封裝
CN102664174A (zh) * 2012-04-19 2012-09-12 日月光半导体制造股份有限公司 半导体封装构造
JP6326723B2 (ja) 2012-08-24 2018-05-23 Tdk株式会社 端子構造及び半導体素子
JP6155571B2 (ja) * 2012-08-24 2017-07-05 Tdk株式会社 端子構造、並びにこれを備える半導体素子及びモジュール基板
US8802556B2 (en) * 2012-11-14 2014-08-12 Qualcomm Incorporated Barrier layer on bump and non-wettable coating on trace
US10204876B2 (en) * 2013-03-07 2019-02-12 Maxim Integrated Products, Inc. Pad defined contact for wafer level package
KR101462770B1 (ko) * 2013-04-09 2014-11-20 삼성전기주식회사 인쇄회로기판과 그의 제조방법 및 그 인쇄회로기판을 포함하는 반도체 패키지
US9299686B1 (en) * 2015-01-16 2016-03-29 International Business Machines Corporation Implementing integrated circuit chip attach in three dimensional stack using vapor deposited solder Cu pillars
CN104979318A (zh) * 2015-05-19 2015-10-14 南通富士通微电子股份有限公司 晶圆级芯片封装结构及其封装方法
DE102016103585B4 (de) 2016-02-29 2022-01-13 Infineon Technologies Ag Verfahren zum Herstellen eines Package mit lötbarem elektrischen Kontakt
US11244918B2 (en) * 2017-08-17 2022-02-08 Semiconductor Components Industries, Llc Molded semiconductor package and related methods
US20190259722A1 (en) * 2018-02-21 2019-08-22 Rohm And Haas Electronic Materials Llc Copper pillars having improved integrity and methods of making the same
JP2019161003A (ja) * 2018-03-13 2019-09-19 株式会社東芝 半導体装置及びその製造方法
CN109729639B (zh) * 2018-12-24 2020-11-20 奥特斯科技(重庆)有限公司 在无芯基板上包括柱体的部件承载件
US10950531B2 (en) * 2019-05-30 2021-03-16 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6326701B1 (en) * 1999-02-24 2001-12-04 Sanyo Electric Co., Ltd. Chip size package and manufacturing method thereof
TW200501378A (en) * 2003-06-30 2005-01-01 Advanced Semiconductor Eng Under bump metallurgy structure
CN101211878A (zh) * 2006-12-28 2008-07-02 国际商业机器公司 互连结构及其形成方法
CN101278394A (zh) * 2005-10-03 2008-10-01 罗姆股份有限公司 半导体装置
TW200915457A (en) * 2007-09-04 2009-04-01 Kyocera Corp Semiconductor element, semiconductor element manufacturing method, and mounting structure having semiconductor element mounted thereon
US20090124075A1 (en) * 2007-11-08 2009-05-14 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing a wafer level package
US20090261473A1 (en) * 2001-03-05 2009-10-22 Megica Corporation Low fabrication cost, fine pitch and high reliability solder bump
CN101617396A (zh) * 2007-03-23 2009-12-30 英特尔公司 具有电迁移帽和镀覆焊料的铜管芯凸点

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050176233A1 (en) * 2002-11-15 2005-08-11 Rajeev Joshi Wafer-level chip scale package and method for fabricating and using the same
US7358174B2 (en) * 2004-04-13 2008-04-15 Amkor Technology, Inc. Methods of forming solder bumps on exposed metal pads
US7582556B2 (en) * 2005-06-24 2009-09-01 Megica Corporation Circuitry component and method for forming the same
US7335986B1 (en) * 2005-09-14 2008-02-26 Amkor Technology, Inc. Wafer level chip scale package
US8569887B2 (en) * 2009-11-05 2013-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Post passivation interconnect with oxidation prevention layer
US8610270B2 (en) * 2010-02-09 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and semiconductor assembly with lead-free solder
US8264089B2 (en) * 2010-03-17 2012-09-11 Maxim Integrated Products, Inc. Enhanced WLP for superior temp cycling, drop test and high current applications
US9598772B2 (en) * 2010-04-16 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating bump structure without UBM undercut
US8993431B2 (en) * 2010-05-12 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating bump structure

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6326701B1 (en) * 1999-02-24 2001-12-04 Sanyo Electric Co., Ltd. Chip size package and manufacturing method thereof
US20090261473A1 (en) * 2001-03-05 2009-10-22 Megica Corporation Low fabrication cost, fine pitch and high reliability solder bump
TW200501378A (en) * 2003-06-30 2005-01-01 Advanced Semiconductor Eng Under bump metallurgy structure
CN101278394A (zh) * 2005-10-03 2008-10-01 罗姆股份有限公司 半导体装置
CN101211878A (zh) * 2006-12-28 2008-07-02 国际商业机器公司 互连结构及其形成方法
CN101617396A (zh) * 2007-03-23 2009-12-30 英特尔公司 具有电迁移帽和镀覆焊料的铜管芯凸点
TW200915457A (en) * 2007-09-04 2009-04-01 Kyocera Corp Semiconductor element, semiconductor element manufacturing method, and mounting structure having semiconductor element mounted thereon
US20090124075A1 (en) * 2007-11-08 2009-05-14 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing a wafer level package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102543898A (zh) * 2012-01-17 2012-07-04 南通富士通微电子股份有限公司 一种柱状凸点封装结构
CN110211943A (zh) * 2018-02-28 2019-09-06 东芝存储器株式会社 半导体装置及其制造方法

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