CN101617396A - 具有电迁移帽和镀覆焊料的铜管芯凸点 - Google Patents

具有电迁移帽和镀覆焊料的铜管芯凸点 Download PDF

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CN101617396A
CN101617396A CN200880005748A CN200880005748A CN101617396A CN 101617396 A CN101617396 A CN 101617396A CN 200880005748 A CN200880005748 A CN 200880005748A CN 200880005748 A CN200880005748 A CN 200880005748A CN 101617396 A CN101617396 A CN 101617396A
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cap
layer
solder
equipment according
salient point
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CN101617396B (zh
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T·钟
V·迪宾
M·博尔
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Intel Corp
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Intel Corp
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Abstract

本发明的实施例包括涉及到具有电迁移帽和镀覆焊料的铜管芯凸点的设备和方法。在一个实施例中，一种设备包括：集成电路管芯；管芯表面上的多个铜凸点；基本覆盖铜凸点的配合面，能够控制铜凸点和焊料之间的金属间化合物的形成的电迁移(EM)帽；以及EM帽上的能够保护EM帽，防止其在封装之前被氧化的焊料镀层。

Description

具有电迁移帽和镀覆焊料的铜管芯凸点
技术领域
本发明的实施例涉及微电子封装技术。具体而言，本发明的实施例涉及具有铜管芯凸点的微电子器件，该凸点具有电迁移帽和镀覆焊料。
背景技术
在制成微电子芯片或管芯之后，通常在销售之前对其进行封装。封装提供了通往芯片内部电路的电连接、针对外部环境的保护以及热耗散。在一种封装系统中，将芯片“倒装芯片”连接到封装基板。在倒装芯片封装中，管芯上的电引线分布于其有源表面上，有源表面电连接到封装基板上的对应引线。
图1到3示出了用于对微电子芯片或管芯进行倒装芯片封装的现有技术方法。在图1中，示出了包括导电凸点140的微电子管芯100的一部分。微电子管芯100包括衬底105、器件层110、互连区域115和连接盘120。器件层110通常包括形成于半导体衬底材料中和半导体衬底材料上的多种电路元件，例如晶体管、导体和电阻器。互连区域115包括多层互连的金属通孔和金属线，它们由电介质材料分隔，提供器件层110的器件之间的电连接以及通往包括连接盘120的导电连接盘的电线路。典型地，在连接盘120上形成电介质层125、阻挡金属135和凸点140，其中凸点140提供用于从管芯100电连接到外部封装基板的结构。
如图2和3所示，在普通倒装芯片封装系统中，翻转或倒转微电子管芯100，并将其键合到封装基板150上，使得其包括凸点140的有源表面面向封装基板150的表面。凸点140与封装基板150的表面上的焊料凸点或焊球155对准，在凸点140和焊球155之间、接头160处形成电连接。如图所示，接头160通常包括被压入焊料凸点中的凸点140的部分。图3中还示出了提供于管芯100和封装基板150之间的底部填充材料170。
在一些工艺中，凸点140为铜。在这种系统中，接头160可能会在凸点140和焊球155之间造成孔隙。由于铜的电迁移，这些孔隙的生长可能导致很多问题。例如，可能会导致电阻增大，潜在地会导致互连断裂和器件故障。
附图说明
在附图的图示中以举例方式而非限制方式例示了本发明，在附图中类似的附图标记表示类似的元件，且其中：
图1是现有技术微电子管芯的一部分的截面图，其包括衬底、器件层、互连区域、连接盘、暴露一部分连接盘的电介质层以及阻挡金属和耦合到连接盘的凸点。
图2是现有技术倒装芯片结构的截面图，其包括管芯，管芯的凸点与具有焊料凸点的封装基板对准。
图3示出了附着管芯和封装基板之后的图2的结构，其包括底部填充材料。
图4是微电子管芯的一部分的截面图，其包括衬底、器件层、互连区域、连接盘、连接盘上方且包括暴露连接盘的一部分的开口的电介质层、以及形成于电介质层和连接盘上方的晶种层。
图5示出了具有包括形成于晶种层上方的开口的层的图4的结构。
图6示出了具有形成于开口中和晶种层上的凸点的图5的结构。
图7示出了具有形成于开口中和凸点上的帽的图6的结构。
图8示出了具有形成于开口中和帽上的镀层的图7的结构。
图9示出了层被去除的图8的结构。
图10示出了晶种层的暴露部分被去除的图9的结构。
图11是微电子管芯的截面图，该微电子管芯包括与具有焊料凸点的基板对准的楔形凸点，用于倒装芯片附着。
图12示出了附着管芯和封装基板之后的图11的结构，其包括底部填充材料。
具体实施方式
在各实施例中，描述了涉及到具有电迁移帽和镀覆焊料的铜管芯凸点的设备和方法。然而，可以不用一个或多个具体细节，或利用其他方法、材料或部件来实践各实施例。在其他情况下，未详细展示或描述公知的结构、材料或操作，以免使本发明各实施例的各方面不清楚。类似地，为了解释起见，阐述了具体数字、材料和配置，以便提供对本发明的透彻理解。尽管如此，可以无需所述具体细节来实践本发明。此外，要理解图中所示的各实施例为例示性表示，而未必是按照比例绘制的。
图4-12示出了用于其铜管芯凸点具有电迁移帽和镀覆焊料的倒装芯片封装系统的方法和结构。
图4示出了微电子管芯200的一部分，该微电子管芯200包括衬底205、器件层210、互连区域215、连接盘220、具有暴露连接盘220的一部分的开口230的电介质层225、以及电介质层225和连接盘220的暴露部分上的部分填充开口230的晶种层235。
通常，管芯可以是具有多个管芯的晶片的一部分，或者管芯可以是个体和独立的集成电路。衬底205包括用于形成有效器件的任何适当的一种或多种半导体材料。例如，衬底205可以包括单晶硅、锗、砷化镓、磷化铟或绝缘体上硅等。器件层210包括形成于衬底205中和衬底205上的器件，例如形成集成电路的晶体管、电阻器或导体。
互连区域215为器件层210的器件提供电互连。互连区域215包括金属化层的叠置体，其包括由层间电介质(ILD)材料分隔和绝缘的金属线。金属化层的金属线由导电通孔互连，导电通孔也是由电介质材料分隔和绝缘的。ILD材料包括任何适当的绝缘材料，包括低k ILD材料，这种材料具有低于二氧化硅的介电常数k(小于大约4)。低k ILD材料是有利的，因为它们减小了相邻金属线之间的电容，由此，例如通过减小RC延迟而改善了整体微电子器件的性能。不过，很多低k ILD材料较脆，且易于爆裂或脱层。因此，以下方法和结构可以通过减少这些材料上的应力而使得能够使用一些低k ILD材料或提高其可靠性。
连接盘220电连接到互连区域215的一个或多个金属线和通孔，并为接下来形成电引线或凸点提供导电连接盘或焊盘。在一些范例中，可以将连接盘220视为互连区域215的一部分，例如互连区域215的顶部金属化层。在其他范例中，连接盘220形成于互连区域215上方。连接盘220包括任何适当的导电材料，例如铜或铝。电介质层225(如图所示)形成于连接盘220上方或周围，包括任何适当的绝缘材料，例如钝化材料或绝缘材料。为了形成具有开口230的电介质层225，首先通过旋涂方法或其他适当的沉积方法形成体电介质层。然后，通过公知技术(例如光刻和蚀刻技术)在电介质材料225中形成开口230。
晶种层235包括为形成体导电材料提供适当晶种的任何适当材料或材料叠置体，如以下图6中所述。例如，为了形成体铜导体，使用铜晶种层。在形成晶种层235之前，可以提供阻挡层或粘附层。例如，阻挡层可以包括钽和氮化钽或钛和氮化钛。阻挡层和晶种层是通过公知技术形成的，例如原子层沉积(ALD)、物理气相沉积(PVD)和化学气相沉积(CVD)。
接下来，在晶种层235上方形成包括开口245的层240，从而暴露连接盘，如图5所示。这里，术语“上方”是指远离基板的表面，从而将基板用作参照系，在基板上构建“起”后续结构。因此，使用诸如底部、顶部、上方和侧面的术语是参考朝向结构底部的基板，而不是指参考地或任何其他参照系“向上”或“向下”。
如下所述，层240包括辅助形成开口245并为接下来形成凸点提供充分的结构的任何适当材料。例如，层240可以包括负性光致抗蚀剂，可以通过光刻处理形成开口245。
如图6所示，然后在开口245之内形成凸点248。凸点248包括任何适当的导电材料，例如铜，并且凸点248可以由任何适当技术形成。在一个范例中，凸点248是通过使用晶种层235的定时电镀法形成的。凸点248基本采取了层240中的开口的形式。在一个范例中，从上往下看，开口具有圆形。在一个实施例中，凸点248是受控塌陷芯片连接(C4)凸点。
接下来，如图7所示，在开口245中的凸点248上形成帽盖层244。帽盖层244包括能够控制凸点248与封装焊球的电迁移的金属，例如铁、镍、钴、锡、钯或铂。在一个实施例中，帽盖层244大约为6微米厚。可以通过电镀或无电镀覆形成帽盖层244。
如图8所示，在开口245中的帽盖层244上形成焊料层242。焊料层242包括能够在封装前的后续处理步骤期间基本防止帽盖层244的氧化的锡或锡合金焊料。在一个实施例中，焊料层242大约为2微米厚。可以通过电镀或无电镀形成焊料层242。
然后如图9所示去除层240，暴露被覆盖的凸点250。通过任何适当的技术，例如湿法蚀刻工艺、干法蚀刻工艺或抗蚀剂剥离工艺来去除层240。接下来，如图10所示，通过任何适当的技术去除晶种层235暴露(即未被楔形凸点覆盖)的部分。例如，可以通过湿法蚀刻处理步骤去除晶种层235的部分。如果凸点和晶种层是相同的材料，或者如果两种材料之间蚀刻选择性很小或没有选择性，湿法蚀刻处理步骤也可以去除凸点248的小部分。由于仅去除了凸点的小部分，所以对凸点的形状的不利影响很小或没有不利影响。为了去除晶种层的大部分而仅去除少量凸点，可以使用定时湿法蚀刻步骤。
如图11-12所示，可以将包括被覆盖的凸点250的微电子管芯200倒装芯片附着到包括焊料凸点265的基板260。在图11-12中，为了清楚起见，未示出图4-10中所示的若干元件。在一些范例中，在若干微电子管芯上在晶片处理结束时形成被覆盖的凸点250，在对衬底205进行划片以将多个集成电路分成分立管芯之后将管芯200附着到基板260。
基板260包括任何适当的封装基板，例如印刷电路板(PCB)、内插器、母板、卡等。焊料凸点265是任何适当的焊料材料，包括基于铅的焊料或无铅焊料。无铅焊料的范例包括锡和银的合金或锡和铟的合金。考虑到与在消费产品中使用铅有关的环境和健康问题，无铅焊料可能是有利的。
如图11所示，定位微电子管芯200和基板260，使得被覆盖的凸点250和相应的焊料凸点265基本对准，在高温下将管芯和基板设置在一起，使得焊料回流，在冷却时形成与被覆盖凸点250的接头，以将管芯200和基板260电耦合，如图12所示。而且，如图12所示，在管芯200和基板260之间形成底部填充材料280。在一个范例中，通过毛细底部填充过程提供底部填充材料280。然后可以将管芯封装290组装成计算装置，例如桌上型计算机、膝上型计算机、服务器、PDA、手机等，计算装置可以包括存储器件和网络控制器。
在整个说明书中提到“一个实施例”或“实施例”表示结合该实施例描述的特定特征、结构、材料或特性被包括在本发明的至少一个实施例中。于是，在整个说明书的不同地方出现“在一个实施例中”或“在实施例中”的短语未必是指本发明的同一实施例。此外，可以在一个或多个实施例中以任何适当方式组合特定的特征、结构、材料或特性。
要认识到，上述说明的意图是进行例示而非进行限制。对于本领域的普通技术人员而言，在阅读以上描述以后，很多其他实施例将是显而易见的。因此，应当根据所附权利要求，连同这种权利要求享有权利的等价物的整体范围来确定本发明的范围。

Claims (19)

1、一种设备，包括：
集成电路管芯；
所述管芯表面上的多个铜凸点；
基本覆盖所述铜凸点的配合表面的电迁移(EM)帽，其能够控制所述铜凸点和焊料之间的金属间化合物的形成；以及
所述EM帽上的焊料镀层，其能够保护所述EM帽，防止所述EM帽在封装之前被氧化。
2、根据权利要求1所述的设备，其中所述EM帽包括铁。
3、根据权利要求1所述的设备，其中所述EM帽包括钴。
4、根据权利要求1所述的设备，其中所述EM帽包括从锡、镍、钯和铂构成的组中选择的金属。
5、根据权利要求1所述的设备，其中所述焊料镀层包括基于锡的焊料。
6、根据权利要求1所述的设备，其中所述EM帽具有大约6微米的厚度。
7、根据权利要求1所述的设备，其中所述焊料镀层具有大约2微米的厚度。
8、根据权利要求1所述的设备，还包括焊接到所述管芯的集成电路封装。
9、根据权利要求8所述的设备，还包括：
存储器；以及
网络控制器。
10、一种方法，包括：
在集成电路晶片的表面上形成铜凸点；
在所述铜凸点的表面上形成帽盖层；以及
在所述帽盖层的表面上形成焊料层。
11、根据权利要求10所述的方法，还包括去除光致抗蚀剂材料。
12、根据权利要求11所述的方法，其中形成所述帽盖层包括电镀铁。
13、根据权利要求11所述的方法，其中形成所述焊料层包括电镀锡合金焊料。
14、根据权利要求11所述的方法，其中形成所述帽盖层包括镀覆从铁、钴、镍、铂和钯构成的组中选择的金属。
15、根据权利要求11所述的方法，其中形成所述焊料层包括无电镀覆锡合金焊料。
16、根据权利要求11所述的方法，还包括去除基底金属层。
17、根据权利要求11所述的方法，还包括对所述晶片进行划片。
18、根据权利要求17所述的方法，还包括将来自所述晶片的管芯焊接到封装。
19、根据权利要求18所述的方法，还包括将管芯封装插入到计算装置中。
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