TWI710090B - 半導體封裝結構及其製造方法 - Google Patents
半導體封裝結構及其製造方法 Download PDFInfo
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- TWI710090B TWI710090B TW108132224A TW108132224A TWI710090B TW I710090 B TWI710090 B TW I710090B TW 108132224 A TW108132224 A TW 108132224A TW 108132224 A TW108132224 A TW 108132224A TW I710090 B TWI710090 B TW I710090B
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Abstract
一種半導體封裝結構,其包括線路基板、至少一晶片、密封體、多個導電連接件、重佈線路層以及多個導電端子。線路基板具有第一表面以及相對於第一表面的第二表面。至少一晶片具有主動面以及相對於主動面的背面。至少一晶片以背面配置於線路基板。密封體包封至少一晶片。多個導電連接件圍繞至少一晶片。重佈線路層位於密封體上。多個導電端子位於第二表面上。至少一晶片經由重佈線路層、多個導電連接件以及線路基板電性連接至多個導電端子。另提供一種半導體封裝結構的製造方法。
Description
本發明是有關於一種封裝結構及其製造方法,且特別是有關於一種半導體封裝結構及其製造方法。
為了使電子產品設計實現輕、薄、短且小,半導體封裝技術正持續進步,以嘗試開發出體積較小、重量較輕、整合度較高且更具市場競爭力的產品。因此,對於本領域研究人員來說,如何在使半導體封裝結構具有高輸入/輸出(Input/output,I/O)連接的數目的同時降低製造成本已成為挑戰。
本發明提供一種半導體封裝結構及其製造方法,其可以在使半導體封裝結構具有高輸入/輸出連接的數目且提升電性能力及/或效能的同時降低製造成本。
本發明的提供一種半導體封裝結構,其包括線路基板、至少一晶片、密封體、多個導電連接件、重佈線路層以及多個導電端子。線路基板具有第一表面以及相對於第一表面的第二表面。至少一晶片具有主動面以及相對於主動面的背面。至少一晶片以背面配置於線路基板。密封體包封至少一晶片。多個導電連接件圍繞至少一晶片。重佈線路層位於密封體上。多個導電端子位於第二表面上。至少一晶片經由重佈線路層、多個導電連接件以及線路基板電性連接至多個導電端子。
本發明提供一種半導體封裝結構的製造方法,其至少包括以下步驟。提供線路基板。線路基板具有第一表面以及相對於第一表面的第二表面。配置至少一晶片於第一表面上。至少一晶片具有主動面以及相對於主動面的背面,且至少一晶片以背面配置於線路基板。形成密封體包封至少一晶片。形成多個導電連接件圍繞至少一晶片。形成重佈線路層於密封體上。形成多個導電端子於第二表面上。至少一晶片經由重佈線路層、多個導電連接件以及線路基板電性連接至多個導電端子。
基於上述,在半導體封裝結構中,由於線路基板不為暫時載板,因此,於半導體封裝結構的製造過程中可以省去使用暫時載板的成本且不用額外進行移除暫時載板的製程,進而可以降低半導體封裝結構的製造成本。此外,由於至少一晶片經由重佈線路層、多個導電連接件以及線路基板電性連接至多個導電端子,因此可以藉由重佈線路層、多個導電連接件以及線路基板使半導體封裝結構具有高輸入/輸出連接的數目,且將至少一晶片訊號進行重新配置擴展出去,進而可以提升半導體封裝結構的電性能力及/或效能。
本文所使用之方向用語(例如,上、下、右、左、前、後、頂部、底部)僅作為參看所繪圖式使用且不意欲暗示絕對定向。
除非另有明確說明,否則本文所述任何方法絕不意欲被解釋為要求按特定順序執行其步驟。
參照本實施例之圖式以更全面地闡述本發明。然而,本發明亦可以各種不同的形式體現,而不應限於本文中所述之實施例。圖式中的層或區域的厚度、尺寸或大小會為了清楚起見而放大。相同或相似之參考號碼表示相同或相似之元件,以下段落將不再一一贅述。
圖1A至圖1D是依據本發明一實施例的半導體封裝結構的部分製造方法的部分剖面示意圖。
請參照圖1A,本實施例中,半導體封裝結構100的製造過程可以包括以下步驟。首先,提供線路基板110。線路基板110具有第一表面110a以及相對於第一表面110a的第二表面110b,其中線路基板110可以具有導電線路112,以用於後續的電性連接。導電線路112可以是由多層線路層及連接多層線路層之間的通孔(through hole)或者是盲孔(blind hole)所組成,但本發明不限於此。
在一些實施例中,線路基板110可以為印刷電路板(Printed Circuit Board, PCB)、有機基板(organic substrate)或高密度內連線基板。然而,本發明不限制線路基板110的種類,只要線路基板110中具有適宜的導電線路112可以提供後續製程中所需的電性連接,皆屬於本發明的保護範圍。
值得說明的是,線路基板110為永久基板(Permanent substrate),換句話說,線路基板110非暫時載板,因此,於半導體封裝結構100的製造過程中可以省去使用暫時載板的成本且不用額外進行移除暫時載板的製程,進而可以降低半導體封裝結構100的製造成本。
請繼續參照圖1A,於線路基板110的第一表面110a配置至少一晶片,其中在圖1A至圖1D中示意地繪示出二個晶片(第一晶片120與第二晶片130),但本發明不限於此。在本實施例中,第一晶片120與第二晶片130可以具有不同功能。舉例而言,第一晶片120可以是系統單晶片(system on chip, SoC),而第二晶片130可以是動態隨機存取記憶體(DRAM),但本發明不限於此,在其他實施例中,第一晶片120與第二晶片130可以是其他適宜的半導體晶片。
第一晶片120與第二晶片130的尺寸可以不同。舉例而言,第一晶片120的尺寸可以是大於第二晶片130的尺寸。第一晶片120於第一表面110a上的正投影面積可以大於第二晶片130於第一表面110a上的正投影面積,但本發明不限於此。
至少一晶片具有主動面以及相對於主動面的背面。舉例而言,在本實施例中,第一晶片120具有主動面120a以及相對於主動面120a的背面120b,而第二晶片130具有主動面130a以及相對於主動面130a的背面130b。如圖1A所示,第一晶片120與第二晶片130以面朝上的方式配置於線路基板110。換句話說,第一晶片120以背面120b配置於線路基板110;而第二晶片130以背面130b配置於線路基板110。
至少一晶片可以經由黏著層附接在線路基板110上,使得黏著層夾於至少一晶片與線路基板110之間。舉例而言,在本實施例中,可以於第一晶片120的背面120b與第二晶片130的背面130b配置黏著層。黏著層可以增強晶片與線路基板110之間的黏著力,以防止晶片位移。黏著層可以包括由樹脂構成的晶粒黏著膜(die attach film, DAF)。然而,本發明不限於此。在一些替代實施例中,可以使用其他具有黏著特性的材料來作為黏著層的材料。
請繼續參照圖1A,至少一晶片中的每一者的主動面上可以具有多個導電凸塊。舉例而言,在本實施例中,第一晶片120的主動面120a上可以具有多個導電凸塊122;而第二晶片130的主動面130a上可以具有多個導電凸塊132。
多個導電凸塊可以包括多個第一導電凸塊與多個第二導電凸塊,多個第一導電凸塊的間距P1小於多個第二導電凸塊的間距P2。舉例而言,如圖1A所示,在本實施例中,多個導電凸塊122可以包括多個第一導電凸塊1221與多個第二導電凸塊1222;而多個導電凸塊132可以包括多個第一導電凸塊1321與多個第二導電凸塊1322。多個第一導電凸塊1221的間距P1小於多個第二導電凸塊1222的間距P2;而多個第一導電凸塊1321的間距P1小於多個第二導電凸塊1322的間距P2。在此,間距P1為兩相鄰的第一導電凸塊(兩相鄰的第一導電凸塊1221或兩相鄰的第一導電凸塊1321)的中心點之間的距離;而間距P2為兩相鄰的第二導電凸塊(兩相鄰的第二導電凸塊1222或兩相鄰的第二導電凸塊1322)的中心點之間的距離。
由於多個第一導電凸塊的間距P1小於多個第二導電凸塊的間距P2,因此,具有微間距的多個第一導電凸塊可以作為訊號輸入/輸出接點,而具有粗間距的多個第二導電凸塊可以作為電源/接地接點,但本發明不限於此。
請參照圖1B,於線路基板110的第一表面110a上形成密封體140,以包封至少一晶片。舉例而言,在本實施例中,密封體140可以包封第一晶片120與第二晶片130。在一實施例中,密封體140可以是藉由模塑製程(molding process)所形成的模塑化合物(molding compound)。在一實施例中,密封體140例如可以由環氧樹脂或其他適宜的樹脂等絕緣材料所形成的,但本發明不限於此。
在本實施例中,形成密封體140的步驟可以如下。首先,於線路基板110的第一表面110a上形成密封材料,以完全覆蓋第一晶片120與第二晶片130。接著,對密封材料進行平坦化製程,直到露出第一晶片120的主動面120a上的導電凸塊122以及第二晶片130的主動面130a上的導電凸塊132,使導電凸塊122的頂面、導電凸塊132的頂面與密封體140的頂面140a實質上共面(coplanar)。平坦化製程可以包括化學機械研磨製程(chemical-mechanical polishing, CMP)、機械研磨製程(mechanical grinding process)、蝕刻製程或其他適宜的製程。
請參照圖1C,於密封體140上形成重佈線路層150。在本實施例中,重佈線路層150可以包括多個介電層以及部分嵌入於介電層中的多個圖案化導電層,其中介電層可以包括鄰近密封體140的底介電層151,而圖案化導電層可以包括鄰近密封體140的多個導電圖案152。
在本實施例中,形成重佈線路層150的步驟可以如下。首先,於密封體140上形成介電材料。接著,於介電材料中形成多個第一開口與多個第二開口,其中多個第一開口暴露出至少一晶片(第一晶片120以及第二晶片130)中的每一者的主動面上的多個導電凸塊,而多個第二開口暴露出部分線路基板110的第一表面110a。然後,於多個第一開口與多個第二開口中形成導電材料,且導電材料至少覆蓋多個第二開口的側壁與底面,其中至少覆蓋多個第二開口的側壁與底面導電材料用以形成多個導電連接件160(於圖1C與圖1D中示意性繪示二個)。
多個導電連接件160圍繞至少一晶片。舉例而言,在本實施例中,多個導電連接件160圍繞第一晶片120以及第二晶片130。多個導電連接件160可以貫穿密封體140,且多個導電連接件160可以是由重佈線路層150延伸至線路基板110。密封體140可以填充於多個導電連接件160之間。多個導電連接件160可以為模塑通孔(through molding via;TMV)。
至少一晶片藉由多個導電凸塊與重佈線路層150電性連接。舉例而言,在本實施例中,第一晶片120可以藉由導電凸塊122與重佈線路層150電性連接,而第二晶片130可以藉由導電凸塊132與重佈線路層150電性連接。
在本實施例中,第一晶片120與第二晶片130上的多個第一導電凸塊藉由重佈線路層150電性連接。第一晶片120與第二晶片130上的多個第二導電凸塊藉由重佈線路層150以及多個導電連接件160與線路基板110電性連接。舉例而言,第一晶片120上的多個第一導電凸塊1221與第二晶片130上的多個第一導電凸塊1321可以藉由重佈線路層150電性連接。第一晶片120上的多個第二導電凸塊1222與第二晶片130上的多個第二導電凸塊1322可以藉由重佈線路層150以及多個導電連接件160與線路基板110電性連接。
由於多個第一導電凸塊的間距P1小於多個第二導電凸塊的間距P2,且第一晶片120與第二晶片130上的多個第一導電凸塊可以藉由重佈線路層150電性連接,而第一晶片上與第二晶片上的多個第二導電凸塊可以藉由重佈線路層150以及多個導電連接件160與線路基板110電性連接,因此,在本發明的半導體封裝結構100中具有不同間距的第一導電凸塊與第二導電凸塊可以有效地利用線路基板110來達成兩晶片之間不同的電性連接需求(訊號輸入/輸出及電源/接地)。舉例而言,具有微間距的多個第一導電凸塊藉由重佈線路層150電性連接以傳遞訊號,而具有粗間距的多個第二導電凸塊藉由重佈線路層150以及多個導電連接件160與線路基板110電性連接以連接電源/接地。如此,可以減少重佈線路層150所需形成的層數,進而可以降低半導體封裝結構100的製造成本。此外,上述配置方式也可以進一步使半導體封裝結構100具有更好的訊號完整性/電源完整性(signal integrity/power integrity, SI/PI)性能。
在一實施例中,重佈線路層150的細線距(line-and-space, L/S)可以是小於5微米/5微米。在一實施例中,重佈線路層150的細線距例如是小於2微米/2微米,因此可以具有較佳的訊號傳輸能力。
應說明的是,圖式中的線路佈局(layout)僅為示意用,因此,於圖式中,線路基板110以及重佈線路層150中部分未連接的線路實際上也可以視線路設計需求經由導通孔或其他方向的導電件進行電性連接。
請參照圖1D,於線路基板110的第二表面110b上形成多個導電端子170。至少一晶片(第一晶片120以及第二晶片130)經由重佈線路層150、多個導電連接件160以及線路基板110電性連接至多個導電端子170,因此可以藉由重佈線路層150、多個導電連接件160以及線路基板110使半導體封裝結構100具有高輸入/輸出連接的數目,且將至少一晶片(第一晶片120以及第二晶片130)訊號進行重新配置擴展出去,進而可以提升半導體封裝結構100的電性能力及/或效能。
導電端子170可以藉由植球製程(ball placement process)以及/或回焊製程(reflow process)來形成。導電端子170可以是焊球等的導電凸塊。然而,本發明不限於此。在一些替代的實施例中,基於設計需求,導電端子170可以具有其他可能的形式以及形狀。
經過上述製程後即可大致上完成本實施例之半導體封裝結構100的製作。半導體封裝結構100包括線路基板110、至少一晶片(第一晶片120以及第二晶片130)、密封體140、多個導電連接件160、重佈線路層150以及多個導電端子170。線路基板具有第一表面110a以及相對於第一表面110a的第二表面110b。至少一晶片(第一晶片120以及第二晶片130)具有主動面以及相對於主動面的背面。至少一晶片(第一晶片120以及第二晶片130)以背面配置於線路基板110。密封體140包封至少一晶片(第一晶片120以及第二晶片130)。多個導電連接件160圍繞至少一晶片(第一晶片120以及第二晶片130)。重佈線路層150位於密封體140上。多個導電端子170位於第二表面110b上。至少一晶片(第一晶片120以及第二晶片130)經由重佈線路層150、多個導電連接件160以及線路基板110電性連接至多個導電端子170。
在半導體封裝結構100中,由於線路基板110不為暫時載板,因此,於半導體封裝結構100的製造過程中可以省去使用暫時載板的成本且不用額外進行移除暫時載板的製程,進而可以降低半導體封裝結構100的製造成本。
此外,由於至少一晶片(第一晶片120以及第二晶片130)經由重佈線路層150、多個導電連接件160以及線路基板110電性連接至多個導電端子170,因此可以藉由重佈線路層150、多個導電連接件160以及線路基板110使半導體封裝結構100具有高輸入/輸出連接的數目,且將至少一晶片(第一晶片120以及第二晶片130)訊號進行重新配置擴展出去,進而可以提升半導體封裝結構100的電性能力及/或效能。
在此必須說明的是,以下實施例沿用上述實施例的元件標號與部分內容,其中採用相同或近似的標號來表示相同或近似的元件,並且省略了相同技術內容的說明,關於省略部分的說明可參考前述實施例,下述實施例不再重複贅述。
圖2A至圖2E是依據本發明另一實施例的半導體封裝結構的部分製造方法的部分剖面示意圖。在本實施例中,半導體封裝結構200與半導體封裝結構100相似,其類似的構件以相同的標號表示,且具有類似的功能、材質或形成方式,並省略描述。
請參照圖2A,提供線路基板210,其中線路基板210具有第一表面210a以及相對於第一表面210a的第二表面210b。在本實施例中,線路基板210類似於線路基板110,線路基板210與線路基板110的差異在於:線路基板210中可以包括預先形成的多個導電連接件260。換句話說,多個導電連接件260可以是線路基板210的一部分。線路基板210可以具有凹穴C,以形成後續可配置晶片的空間。在一實施例中,多個導電連接件260的頂面可以是與第一表面210a實質上共面。凹穴C的底面CS可以是位於線路基板210的第一表面210a與第二表面210b之間。
請參照圖2B,於線路基板110的凹穴C配置至少一晶片。舉例而言,在本實施例中,第一晶片120以背面120b配置於線路基板210的凹穴C;而第二晶片130以背面130b配置於線路基板210的凹穴C。第一晶片120與第二晶片130可以經由黏著層附接在凹穴C的底面CS上,使第一晶片120以及第二晶片130埋設於線路基板110中。在一實施例中,凹穴C的高度可以大於至少一晶片中的每一者的高度。
請參照圖2C,於凹穴C中形成密封體240,以包封至少一晶片(第一晶片120以及第二晶片130)。在本實施例中,密封體240類似於密封體140,密封體240與密封體140的差異在於形成密封體240的步驟可以如下。首先,於凹穴C與線路基板210的第一表面210a上形成密封材料,以完全覆蓋第一晶片120、第二晶片130以及多個導電連接件260。接著,對密封材料進行平坦化製程,直到露出第一晶片120的主動面120a上的導電凸塊122、第二晶片130的主動面130a上的導電凸塊132以及多個導電連接件260,使第一晶片120的主動面120a上的導電凸塊122的頂面、第二晶片130的主動面130a上的導電凸塊132的頂面、多個導電連接件260的頂面、密封體240的頂面240a與線路基板210的第一表面210a實質上共面。
請參照圖2D,於密封體240上形成重佈線路層250。重佈線路層250類似於重佈線路層150,重佈線路層250與重佈線路層150的差異在於:多個導電連接件260不延伸至重佈線路層250,部分線路基板210可以與重佈線路層250直接接觸,其中重佈線路層250可以包括鄰近密封體240的底介電層251,而圖案化導電層可以包括鄰近密封體240的多個導電圖案252。
在本實施例中,形成重佈線路層250的步驟可以如下。首先,於密封體240以及線路基板210的第一表面210a上形成介電材料。接著,於介電材料中形成多個第三開口,以暴露出至少一晶片(第一晶片120以及第二晶片130)中的每一者的主動面上的多個導電凸塊以及多個導電連接件260的頂面。然後,於多個第三開口中形成導電材料。重佈線路層250可以與至少一晶片(第一晶片120以及第二晶片130)中的每一者的主動面上的多個導電凸塊以及多個導電連接件260直接接觸。
請參照圖2E,於線路基板110的第二表面110b上形成多個導電端子170。至少一晶片(第一晶片120以及第二晶片130)經由重佈線路層250、多個導電連接件260以及線路基板210電性連接至多個導電端子170,因此可以藉由重佈線路層250、多個導電連接件260以及線路基板210使半導體封裝結構200具有高輸入/輸出連接的數目,且將至少一晶片(第一晶片120以及第二晶片130)訊號進行重新配置擴展出去,進而可以提升半導體封裝結構200的電性能力及/或效能。
經過上述製程後即可大致上完成本實施例之半導體封裝結構200的製作。半導體封裝結構200包括線路基板210、至少一晶片(第一晶片120以及第二晶片130)、密封體240、多個導電連接件260、重佈線路層250以及多個導電端子170。線路基板具有第一表面210a以及相對於第一表面210a的第二表面210b。至少一晶片(第一晶片120以及第二晶片130)具有主動面以及相對於主動面的背面。至少一晶片(第一晶片120以及第二晶片130)以背面配置於線路基板110。密封體240包封至少一晶片(第一晶片120以及第二晶片130)。多個導電連接件260圍繞至少一晶片(第一晶片120以及第二晶片130)。重佈線路層250位於密封體240上。多個導電端子170位於第二表面110b上。至少一晶片(第一晶片120以及第二晶片130)經由重佈線路層250、多個導電連接件260以及線路基板210電性連接至多個導電端子170。
在半導體封裝結構200中,由於線路基板210不為暫時載板,因此,於半導體封裝結構200的製造過程中可以省去使用暫時載板的成本且不用額外進行移除暫時載板的製程,進而可以降低半導體封裝結構200的製造成本。
此外,由於至少一晶片(第一晶片120以及第二晶片130)經由重佈線路層250、多個導電連接件260以及線路基板210電性連接至多個導電端子170,因此可以藉由重佈線路層250、多個導電連接件260以及線路基板210使半導體封裝結構200具有高輸入/輸出連接的數目,且將至少一晶片(第一晶片120以及第二晶片130)訊號進行重新配置擴展出去,進而可以提升半導體封裝結構200的電性能力及/或效能。
圖3A至圖3D是依據本發明又一實施例的半導體封裝結構的部分製造方法的部分剖面示意圖。在本實施例中,半導體封裝結構300與半導體封裝結構100相似,其類似的構件以相同的標號表示,且具有類似的功能、材質或形成方式,並省略描述。
請參照圖3A,提供線路基板110,其中線路基板110具有第一表面110a以及相對於第一表面110a的第二表面110b。接著,將預先形成的多個導電連接件360形成於第一表面110a上。然後,於第一表面110a上配置至少一晶片,其中在圖3A至圖3D中示意地繪示出一個晶片(第一晶片120),但本發明不限於此。
在本實施例中,預先形成的多個導電連接件360可以由銅、鋁、鎳、上述之組合、或是其他適宜的導電材料所製成。導電連接件360可以藉由電鍍或其他適宜的製程所形成。
請參照圖3B,於線路基板110的第一表面110a上形成密封體340,以包封至少一晶片(第一晶片120)。在本實施例中,密封體340類似於密封體140,密封體340與密封體140的差異在於形成密封體340的步驟可以如下。首先,於線路基板110的第一表面110a上形成密封材料,以完全覆蓋第一晶片120與多個導電連接件360。接著,對密封材料進行平坦化製程,直到露出第一晶片120的主動面120a上的導電凸塊122與多個導電連接件360的頂面,使第一晶片120的主動面120a上的導電凸塊122的頂面、多個導電連接件360的頂面與密封體340的頂面340a實質上共面。
請參照圖3C,於密封體340上形成重佈線路層350。重佈線路層350類似於重佈線路層150,重佈線路層350與重佈線路層150的差異在於:多個導電連接件360不延伸至重佈線路層350。重佈線路層350可以包括鄰近密封體340的底介電層351,而圖案化導電層可以包括鄰近密封體340的多個導電圖案352。
請參照圖3D,於線路基板110的第二表面110b上形成多個導電端子170。至少一晶片經由重佈線路層350、多個導電連接件360以及線路基板110電性連接至多個導電端子170,因此可以藉由重佈線路層350、多個導電連接件360以及線路基板110使半導體封裝結構300具有高輸入/輸出連接的數目,且將至少一晶片(第一晶片120)訊號進行重新配置擴展出去,進而可以提升半導體封裝結構300的電性能力及/或效能。
經過上述製程後即可大致上完成本實施例之半導體封裝結構300的製作。半導體封裝結構300包括線路基板110、至少一晶片(第一晶片120)、密封體340、多個導電連接件360、重佈線路層350以及多個導電端子170。線路基板具有第一表面110a以及相對於第一表面110a的第二表面110b。至少一晶片(第一晶片120)具有主動面以及相對於主動面的背面。至少一晶片(第一晶片120)以背面配置於線路基板110。密封體340包封至少一晶片(第一晶片120)。多個導電連接件360圍繞至少一晶片(第一晶片120)。重佈線路層350位於密封體340上。多個導電端子170位於第二表面110b上。至少一晶片(第一晶片120)經由重佈線路層350、多個導電連接件360以及線路基板110電性連接至多個導電端子170。
在半導體封裝結構300中,由於線路基板110不為暫時載板,因此,於半導體封裝結構300的製造過程中可以省去使用暫時載板的成本且不用額外進行移除暫時載板的製程,進而可以降低半導體封裝結構100的製造成本。
此外,由於至少一晶片(第一晶片120)經由重佈線路層350、多個導電連接件360以及線路基板110電性連接至多個導電端子170,因此可以藉由重佈線路層350、多個導電連接件360以及線路基板110使半導體封裝結構300具有高輸入/輸出連接的數目,且將至少一晶片(第一晶片120)訊號進行重新配置擴展出去,進而可以提升半導體封裝結構300的電性能力及/或效能。
綜上所述,在半導體封裝結構中,由於線路基板不為暫時載板,因此,於半導體封裝結構的製造過程中可以省去使用暫時載板的成本且不用額外進行移除暫時載板的製程,進而可以降低半導體封裝結構的製造成本。再者,由於至少一晶片經由重佈線路層、多個導電連接件以及線路基板電性連接至多個導電端子,因此可以藉由重佈線路層、多個導電連接件以及線路基板使半導體封裝結構具有高輸入/輸出連接的數目,且將至少一晶片訊號進行重新配置擴展出去,進而可以提升半導體封裝結構的電性能力及/或效能。此外,在至少一晶片為二個以上時,具有不同間距的第一導電凸塊與第二導電凸塊可以有效地利用線路基板來達成兩晶片之間不同的電性連接需求(訊號輸入/輸出及電源/接地),進而可以進一步使半導體封裝結構具有更好的訊號完整性/電源完整性性能。
100、200、300:半導體封裝結構
110、210:線路基板
110a、210a:第一表面
110b、210b:第二表面
112:導電線路
120:第一晶片
120a、130a:主動面
120b、130b:背面
122、1221、1222、132、1321、1322:導電凸塊
130:第二晶片
140、240、340:密封體
140a、240a、340a:頂面
150、250、350:重佈線路層
151、251、351:底介電層
152、252、352:導電圖案
160、260、360:導電連接件
170:導電端子
C:凹穴
CS:底面
P1、P2:間距
圖1A至圖1D是依據本發明一實施例的半導體封裝結構的部分製造方法的部分剖面示意圖。
圖2A至圖2E是依據本發明另一實施例的半導體封裝結構的部分製造方法的部分剖面示意圖。
圖3A至圖3D是依據本發明又一實施例的半導體封裝結構的部分製造方法的部分剖面示意圖。
100:半導體封裝結構
110:線路基板
120:第一晶片
120a、130a:主動面
130:第二晶片
140:密封體
150:重佈線路層
160:導電連接件
170:導電端子
Claims (9)
- 一種半導體封裝結構,包括:線路基板,具有第一表面以及相對於所述第一表面的第二表面;至少一晶片,具有主動面以及相對於所述主動面的背面,其中所述至少一晶片以所述背面配置於所述線路基板,所述至少一晶片中的每一者的所述主動面上具有多個導電凸塊,所述多個導電凸塊包括多個第一導電凸塊與多個第二導電凸塊,所述多個第一導電凸塊的間距小於所述多個第二導電凸塊的間距;密封體,包封所述至少一晶片;多個導電連接件,圍繞所述至少一晶片;重佈線路層,位於所述密封體上,且所述至少一晶片藉由所述多個導電凸塊與所述重佈線路層電性連接;以及多個導電端子,位於所述第二表面上,其中所述至少一晶片經由所述重佈線路層、所述多個導電連接件以及所述線路基板電性連接至所述多個導電端子。
- 如申請專利範圍第1項所述的半導體封裝結構,其中:所述至少一晶片包括第一晶片與第二晶片;所述第一晶片與所述第二晶片的所述多個第一導電凸塊藉由所述重佈線路層電性連接;以及 所述第一晶片與所述第二晶片上的所述多個第二導電凸塊藉由所述重佈線路層以及所述多個導電連接件與所述線路基板電性連接。
- 如申請專利範圍第1項所述的半導體封裝結構,其中所述多個導電連接件的頂面與所述密封體的頂面實質上共面。
- 如申請專利範圍第1項所述的半導體封裝結構,其中所述多個導電連接件由所述重佈線路層延伸至所述線路基板。
- 一種半導體封裝結構的製造方法,包括:提供線路基板,具有第一表面以及相對於所述第一表面的第二表面;配置至少一晶片於所述第一表面上,其中所述至少一晶片具有主動面以及相對於所述主動面的背面,且所述至少一晶片以所述背面配置於所述線路基板,且藉由所述線路基板承載所述至少一晶片;形成密封體包封所述至少一晶片;形成多個導電連接件圍繞所述至少一晶片;形成重佈線路層於所述密封體上;以及形成多個導電端子於所述第二表面上,其中所述至少一晶片經由所述重佈線路層、所述多個導電連接件以及所述線路基板電性連接至所述多個導電端子。
- 如申請專利範圍第5項所述的半導體封裝結構的製造方法,其中在形成所述密封體後形成所述多個導電連接件。
- 如申請專利範圍第5項所述的半導體封裝結構的製造方法,其中所述多個導電連接件為預先形成的導電柱。
- 如申請專利範圍第7項所述的半導體封裝結構的製造方法,其中所述預先形成的導電柱埋設於所述線路基板中。
- 如申請專利範圍第8項所述的半導體封裝結構的製造方法,其中所述線路基板具有凹穴,且所述至少一晶片配置於所述凹穴中。
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