TWI725902B - 半導體封裝結構及其製造方法 - Google Patents

半導體封裝結構及其製造方法 Download PDF

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TWI725902B
TWI725902B TW109126333A TW109126333A TWI725902B TW I725902 B TWI725902 B TW I725902B TW 109126333 A TW109126333 A TW 109126333A TW 109126333 A TW109126333 A TW 109126333A TW I725902 B TWI725902 B TW I725902B
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conductive
circuit substrate
circuit
chips
semiconductor package
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TW109126333A
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TW202127600A (zh
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林南君
徐宏欣
張簡上煜
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力成科技股份有限公司
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Abstract

一種半導體封裝結構，其包括線路基板、至少二晶片、密封體以及重佈線路層。線路基板具有第一表面以及相對於第一表面的第二表面。至少二晶片配置於第一表面上，其中至少二晶片中的每一者具有面向線路基板的主動面並包括配置於主動面上的多個第一導電連接件以及多個第二導電連接件。多個第一導電連接件的間距小於多個第二導電連接件的間距。密封體包封至少二晶片。重佈線路層位於第二表面上。多個第一導電連接件藉由線路基板與重佈線路層電性連接。多個第二導電連接件與線路基板電性連接。另提供一種半導體封裝結構的製造方法。

Description

半導體封裝結構及其製造方法
本發明是有關於一種封裝結構及其製造方法，且特別是有關於一種半導體封裝結構及其製造方法。
為了使電子產品設計實現輕、薄、短且小，半導體封裝技術正持續進步，以嘗試開發出體積較小、重量較輕、整合度較高且更具市場競爭力的產品。如何在降低半導體封裝結構的製造成本的同時還能夠提升半導體封裝結構的可靠度實為本領域的技術人員的一大挑戰。
本發明提供一種半導體封裝結構及其製造方法，其可以在降低半導體封裝結構的製造成本的同時還能夠提升半導體封裝結構的可靠度。
本發明的提供一種半導體封裝結構，其包括線路基板、至少二晶片、密封體以及重佈線路層。線路基板具有第一表面以及相對於第一表面的第二表面。至少二晶片配置於第一表面上，其中至少二晶片中的每一者具有面向線路基板的主動面並包括配置於主動面上的多個第一導電連接件以及多個第二導電連接件。多個第一導電連接件的間距小於多個第二導電連接件的間距。密封體包封至少二晶片。重佈線路層位於第二表面上。多個第一導電連接件藉由線路基板與重佈線路層電性連接。多個第二導電連接件與線路基板電性連接。
本發明提供一種半導體封裝結構的製造方法，其至少包括以下步驟。提供線路基板。線路基板具有第一表面以及相對於第一表面的第二表面。配置至少二晶片於第一表面上。至少二晶片中的每一者具有面向線路基板的主動面並包括配置於主動面上的多個第一導電連接件以及多個第二導電連接件。多個第一導電連接件相鄰兩者之間的間距小於多個第二導電連接件相鄰兩者之間的間距。形成密封體包封至少二晶片。形成重佈線路層於線路基板的第二表面上。多個第一導電連接件藉由線路基板與重佈線路層電性連接。多個第二導電連接件與線路基板電性連接。
基於上述，由於多個第一導電連接件的間距小於多個第二導電連接件的間距，且第一導電連接件藉由線路基板與重佈線路層電性連接，第二導電連接件與線路基板電性連接，因此，在本發明的半導體封裝結構中具有不同間距的第一導電連接件與第二導電連接件可以有效地利用線路基板來達成至少兩晶片之間不同的電性連接需求，進而可以減少重佈線路層所需形成的層數，降低半導體封裝結構的製造成本。此外，上述配置方式也可以在降低半導體封裝結構的製造成本的同時提升半導體封裝結構的可靠度（如改善信號完整性/電源完整性）。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
本文所使用之方向用語（例如，上、下、右、左、前、後、頂部、底部）僅作為參看所繪圖式使用且不意欲暗示絕對定向。
除非另有明確說明，否則本文所述任何方法絕不意欲被解釋為要求按特定順序執行其步驟。
參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施例。圖式中的層或區域的厚度、尺寸或大小會為了清楚起見而放大。相同或相似之參考號碼表示相同或相似之元件，以下段落將不再一一贅述。
圖1A至圖1E是依據本發明一實施例的半導體封裝結構的部分製造方法的部分剖面示意圖。
請參照圖1A，本實施例中，半導體封裝結構100的製造過程可以包括以下步驟。首先，提供線路基板110。線路基板110具有第一表面110a以及相對於第一表面110a的第二表面110b，且線路基板110可以包括導電線路112。
在一些實施例中，線路基板110可以為印刷電路板（Printed Circuit Board, PCB）、有機基板（organic substrate）或高密度內連線基板。然而，本發明不限制線路基板110的種類，只要線路基板110中具有適宜的導電線路112可以提供後續製程中所需的電性連接，皆屬於本發明的保護範圍。
請繼續參照圖1A，線路基板110可以包括中間區CR以及外圍區PR。在本實施例中，導電線路112可以包括位於中間區CR的多個疊孔結構1121。疊孔結構1121可以連接線路基板110的第一表面110a與第二表面110b。
在一實施例中，疊孔結構1121可以包括多個導通孔V，其中導通孔V可以於第一表面110a的法向量n上相互堆疊。在一實施例中，導通孔V於第一表面110a上的正投影可以完全重疊，因此，疊孔結構1121可以作為線路基板110中提供較短電連接路徑的垂直電連接結構。
請參照圖1B，於線路基板110的第一表面110a上配置至少二晶片，其中至少二晶片可以包括第一晶片120以及第二晶片130。在一實施例中，第一晶片120與第二晶片130可以具有不同功能。舉例而言，第一晶片120可以是系統單晶片（system on chip, SoC），而第二晶片130動態隨機存取記憶體（DRAM），但本發明不限於此，第一晶片120與第二晶片130可以是其他適宜的半導體晶片。在一實施例中，第一晶片120與第二晶片130的尺寸可以不同。
在本實施例中，至少二晶片中的每一者具有主動面以及相對於主動面的背面，其中主動面面向線路基板110的第一表面110a。舉例而言，第一晶片120具有主動面120a以及相對於主動面120a的背面120b，而第二晶片130具有主動面130a以及相對於主動面130a的背面130b，且第一晶片120以及第二晶片130例如是以覆晶（flip-chip）方式配置於線路基板110的第一表面110a上。
至少二晶片中的每一者可以包括配置於所述至少二晶片中的每一者的主動面上的多個第一導電連接件142以及多個第二導電連接件144，且多個第一導電連接件142以及多個第二導電連接件144與線路基板110電性連接。舉例而言，第一晶片120的主動面120a上可以配置有多個第一導電連接件1421以及多個第二導電連接件1441；而第二晶片130的主動面130a上可以配置有多個第一導電連接件1422以及多個第二導電連接件1442。
在本實施例中，多個第一導電連接件142相鄰兩者之間的間距P1小於多個第二導電連接件144相鄰兩者之間的間距P2。在此，間距P1為兩相鄰的第一導電連接件142的中心點之間的距離；而間距P2為兩相鄰的第二導電連接件144的中心點之間的距離。多個第一導電連接件142的間距P1可以稱為微間距（fine pitch），而多個第二導電連接件144的間距P2可以稱為粗間距（coarse pitch）。
由於多個第一導電連接件142相鄰兩者之間的間距P1小於多個第二導電連接件144相鄰兩者之間的間距P2，因此，具有微間距的多個第一導電連接件142可以作為信號輸入/輸出接點，而具有粗間距的多個第二導電連接件144可以作為電源/接地接點。
請繼續參照圖1B，在本實施例中，中間區CR可以是至少兩晶片中的一者靠近另一者的區域，外圍區PR可以是至少兩晶片中的一者遠離另一者的區域，如圖1B所示。多個第一導電連接件142位於中間區CR，多個第二導電連接件144位於外圍區PR。至少兩晶片的任一者中的多個第一導電連接件142可以是相較於多個第二導電連接件144靠近至少兩晶片的另一者。舉例而言，第一晶片120中的多個第一導電連接件1421相較於多個第二導電連接件1441靠近第二晶片130，而第二晶片130中的多個第一導電連接件1422相較於多個第二導電連接件1442靠近第一晶片120。
第一導電連接件142可以與疊孔結構1121電性連接，而第二導電連接件144可以與線路基板110中多個疊孔結構1121以外的導電線路112電性連接。在一實施例中，每一第一導電連接件142可以與對應的疊孔結構1121電性連接。舉例而言，第一導電連接件142與疊孔結構1121可以是以一對一方式配置，但本發明不限於此。在一實施例中，第一導電連接件142可以與對應的疊孔結構1121直接接觸。
在本實施例中，第一導電連接件142與第二導電連接件144例如是由接墊及導電凸塊所組成，但本發明不限於此，可以視實際需求而定。
請參照圖1C，將至少二晶片配置於線路基板110上後，於線路基板110的第一表面110a上形成密封體150，以包封至少二晶片。在本實施例中，密封體150可以完全覆蓋至少二晶片。舉例而言，密封體150可以覆蓋第一晶片120的背面120b與第二晶片130的背面130b。密封體150可以是藉由模塑製程（molding process）所形成的模塑化合物（molding compound）。在一實施例中，密封體150例如可以由環氧樹脂或其他適宜的樹脂等絕緣材料所形成的，但本發明不限於此。
在未繪示的實施例中，還可以進一步對密封體150進行研磨製程（grinding process），直到露出第一晶片120的背面120b以及第二晶片130的背面130b，使第一晶片120的背面120b與第二晶片130的背面130b基本上共面（coplanar）。
請參照圖1D，形成密封體150之後，將圖1C所繪示的結構上下翻面（flipped upside down）。接著，於線路基板110的第二表面110b上形成重佈線路層160，且第一導電連接件142藉由線路基板110與重佈線路層160電性連接。
由於多個第一導電連接件142的間距P1小於多個第二導電連接件144的間距P2，且第一導電連接件142藉由線路基板110與重佈線路層160電性連接，第二導電連接件144與線路基板110電性連接，因此，在本發明的半導體封裝結構100中具有不同間距的第一導電連接件142與第二導電連接件144可以有效地利用線路基板110來達成至少兩晶片之間不同的電性連接需求（信號輸入/輸出及電源/接地）。舉例而言，具有微間距的多個第一導電連接件142藉由線路基板110與重佈線路層160電性連接以傳遞信號，而具有粗間距的多個第二導電連接件144與線路基板110電性連接以連接電源/接地。如此，可以減少重佈線路層160所需形成的層數，進而可以降低半導體封裝結構100的製造成本。此外，上述配置方式也可以進一步提升半導體封裝結構100的可靠度。例如，半導體封裝結構100具有更好的信號完整性/電源完整性（signal integrity/power integrity, SI/PI）性能。
在一實施例中，重佈線路層160可以包括多個介電層以及部分嵌入於介電層中的多個圖案化導電層。介電層可以包括鄰近線路基板110的底介電層161，而圖案化導電層可以包括鄰近線路基板110的多個導電圖案162。
重佈線路層160的形成方法例如是於線路基板110的第二表面110b上形成具有多個開口的底介電層161，其中多個開口暴露出線路基板110中部分導電線路112。接著，於多個開口中形成導電圖案162，使導電圖案162電性連接至前述部分導電線路112。然後，可以重複上述步驟多次，以形成由交替堆疊的介電層與圖案化導電層所組成的重佈線路層160。
在一實施例中，多個導電圖案162可以分別對應於多個疊孔結構1121，其中多個導電圖案162可以形成直接電連接區域E。多個開口例如是暴露出線路基板110中部分導電線路112的多個疊孔結構1121，以使第一導電連接件142可以藉由線路基板110中的多個疊孔結構1121與重佈線路層160中的導電圖案162電性連接，以用於傳遞第一晶片120與第二晶片130之間的信號。舉例而言，第一晶片120與第二晶片130之間的信號傳遞路徑例如是依序經由第一晶片120上的第一導電連接件1421、疊孔結構1121、導電圖案162、疊孔結構1121以及第二晶片130上的第一導電連接件1422所傳遞。在一實施例中，每一多個開口對應多個疊孔結構1121中的其中之一。
由於多個疊孔結構1121可以是垂直電連接結構，因此，當第一晶片120與第二晶片130上的第一導電連接件1421與第一導電連接件1422藉由線路基板110中的多個疊孔結構1121以及重佈線路層160來傳遞信號時，傳輸路徑/距離可以顯著地縮短，進而半導體封裝結構100可以具有更好的信號完整性。
在一實施例中，重佈線路層160的細線距（line-and-space, L/S）可以是小於5微米/5微米。在一實施例中，重佈線路層160的細線距例如是小於2微米/2微米，因此可以具有較佳的信號傳輸能力。
此外，形成底介電層161於線路基板110上可以為線路基板110提供緩衝，進而可以進一步提升半導體封裝結構100的可靠度。
應說明的是，圖式中的線路佈局（layout）僅為示意用，因此，於圖式中，導電線路112以及重佈線路層160中部分未連接的線路實際上也可以視線路設計需求經由導通孔或其他方向的導電件進行電性連接。
請參照圖1E，形成重佈線路層160之後，於重佈線路層160上形成多個導電端子170，而導電端子170與重佈線路層160電性連接。在一實施例中，重佈線路層160位於至少二晶片與導電端子170之間。因此，至少二晶片可以藉由線路基板110及重佈線路層160與導電端子170電性連接。舉例而言，多個第二導電連接件144可以藉由線路基板110以及重佈線路層160與導電端子170電性連接。
在一實施例中，多個導電端子170相鄰兩者之間的間距P3可以大於多個第一導電連接件142相鄰兩者之間的間距P1。在此，間距P3為兩相鄰的導電端子170的中心點之間的距離。
導電端子170可以藉由植球製程（ball placement process）以及/或回焊製程（reflow process）來形成。導電端子170可以是焊球等的導電凸塊。然而，本發明不限於此。在一些替代的實施例中，基於設計需求，導電端子170可以具有其他可能的形式以及形狀。
經過上述製程後即可大致上完成本實施例之半導體封裝結構100的製作。半導體封裝結構100包括線路基板110、至少二晶片（第一晶片120以及第二晶片130）、密封體150以及重佈線路層160。線路基板110具有第一表面110a以及相對於第一表面110a的第二表面110b。至少二晶片配置於第一表面110a上，其中至少二晶片中的每一者具有面向線路基板110的主動面並包括配置於主動面上的多個第一導電連接件142以及多個第二導電連接件144。多個第一導電連接件142的間距小於多個第二導電連接件144的間距。密封體150包封至少二晶片。重佈線路層160位於第二表面110b上。多個第一導電連接件142藉由線路基板110與重佈線路層160電性連接。多個第二導電連接件144與線路基板110電性連接。
綜上所述，由於多個第一導電連接件的間距小於多個第二導電連接件的間距，且第一導電連接件藉由線路基板與重佈線路層電性連接，第二導電連接件與線路基板電性連接，因此，在本發明的半導體封裝結構中具有不同間距的第一導電連接件與第二導電連接件可以有效地利用線路基板來達成至少兩晶片之間不同的電性連接需求，進而可以減少重佈線路層所需形成的層數，降低半導體封裝結構的製造成本。此外，上述配置方式也可以在降低半導體封裝結構的製造成本的同時提升半導體封裝結構的可靠度（如改善信號完整性/電源完整性）。再者，第一晶片與第二晶片上的第一導電連接件藉由線路基板中的多個疊孔結構以及重佈線路層來傳遞信號時，傳輸路徑/距離可以顯著地縮短，進而半導體封裝結構可以具有更好的信號完整性。此外，本發明的半導體封裝結構中由於線路基板不為暫時性基板，因此，於半導體封裝結構的製造過程中可以省去使用暫時載板的成本且不用額外進行移除暫時載板的製程，進而可以進一步降低半導體封裝結構的製造成本。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100:半導體封裝結構 110:線路基板 110a:第一表面 110b:第二表面 112:導電線路 1121:疊孔結構 120:第一晶片 120a、130a:主動面 120b、130b:背面 130:第二晶片 142、1421、1422:第一導電連接件 144、1441、1442:第二導電連接件 150:密封體 160:重佈線路層 161:底介電層 162:導電圖案 170:導電端子 CR:中間區 E:直接電連接區域 PR:外圍區 n:法向量 V:導通孔 P1、P2、P3:間距
圖1A至圖1E是依據本發明一實施例的半導體封裝結構的部分製造方法的部分剖面示意圖。
100:半導體封裝結構
110:線路基板
110a:第一表面
110b:第二表面
112:導電線路
1121:疊孔結構
120:第一晶片
120a、130a:主動面
120b、130b:背面
130:第二晶片
142、1421、1422:第一導電連接件
144、1441、1442:第二導電連接件
150:密封體
160:重佈線路層
161:底介電層
162:導電圖案
170:導電端子
CR:中間區
E:直接電連接區域
PR:外圍區
P1、P2、P3:間距

Claims (7)

  1. 一種半導體封裝結構，包括：線路基板，具有第一表面以及相對於所述第一表面的第二表面，其中所述線路基板包括中間區與外圍區與多個疊孔結構；至少二晶片，配置於所述第一表面上，其中所述至少二晶片中的每一者具有面向所述線路基板的主動面並包括：多個第一導電連接件以及多個第二導電連接件，配置於所述主動面上；所述多個第一導電連接件的間距小於所述多個第二導電連接件的間距；以及所述多個第一導電連接件位於所述中間區，所述多個第二導電連接件位於所述外圍區密封體，包封所述至少二晶片；以及重佈線路層，位於所述第二表面上，其中所述多個第一導電連接件藉由所述線路基板的所述多個疊孔結構與所述重佈線路層電性連接，所述多個第二導電連接件與所述線路基板電性連接。
  2. 如請求項1所述的半導體封裝結構，其中所述多個疊孔結構位於所述中間區，且所述多個第一導電連接件與所述多個疊孔結構直接接觸。
  3. 如請求項1所述的半導體封裝結構，其中所述多個第二導電連接件與所述線路基板中所述多個疊孔結構以外的導電線路與電性連接。
  4. 如請求項1所述的半導體封裝結構，其中所述多個疊孔結構包括多個導通孔，所述多個導通孔於所述第一表面的法向量上相互堆疊。
  5. 如請求項1所述的半導體封裝結構，其中所述多個導通孔於所述第一表面上的正投影完全重疊。
  6. 如請求項1所述的半導體封裝結構，其中所述重佈線路層包括鄰近所述線路基板的多個導電圖案，且所述多個導電圖案對應於所述多個疊孔結構。
  7. 一種半導體封裝結構的製造方法，包括：提供線路基板，具有第一表面以及相對於所述第一表面的第二表面；配置至少二晶片於所述第一表面上，其中所述至少二晶片中的每一者具有面向所述線路基板的主動面並包括：多個第一導電連接件以及多個第二導電連接件，配置於所述主動面上；以及所述多個第一導電連接件相鄰兩者之間的間距小於所述多個第二導電連接件相鄰兩者之間的間距；形成密封體包封所述至少二晶片；以及形成重佈線路層於所述線路基板的所述第二表面上，其中所述多個第一導電連接件藉由所述線路基板與所述重佈線路層電性連接，所述多個第二導電連接件與所述線路基板電性連接，其中形成所述重佈線路層包括： 形成底介電層於所述第二表面上，且所述底介電層具有多個開口，暴露出所述線路基板中部分導電線路；以及形成導電圖案於所述開口中，使所述導電圖案電性連接至所述部分導電線路，其中所述部分導電線路包括多個疊孔結構，且所述多個開口暴露出所述多個疊孔結構。
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