TW202127597A - 封裝結構及其製造方法 - Google Patents

封裝結構及其製造方法 Download PDF

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TW202127597A
TW202127597A TW109119787A TW109119787A TW202127597A TW 202127597 A TW202127597 A TW 202127597A TW 109119787 A TW109119787 A TW 109119787A TW 109119787 A TW109119787 A TW 109119787A TW 202127597 A TW202127597 A TW 202127597A
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circuit board
package
top surface
conductive
circuit
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TW109119787A
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TWI764172B (zh
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張簡上煜
徐宏欣
洪嘉鍮
林南君
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力成科技股份有限公司
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Abstract

一種封裝結構，其包括第一線路板、第二線路板、模封體、多個導電端子以及封裝件。第一線路板具有第一頂面及相對於第一頂面的第一底面。第二線路板具有第二頂面及相對於第二頂面的第二底面。模封體包覆第一線路板及第二線路板。導電端子配置在第一底面或第二底面上且電性連接於第一線路板或第二線路板。封裝件配置在第一頂面或第二頂面上且電性連接於第一線路板及第二線路板。封裝件包括第一晶片、第二晶片、晶片模封體、線路層以及多個導電封裝端子。一種封裝結構的製造方法亦被提出。

Description

封裝結構及其製造方法
本發明是有關於一種封裝結構及其製造方法，且特別是有關於一種具有多個晶片及多個線路板的封裝結構及其製造方法。
近年來，電子設備對於人類的生活越來越重要。為了加速各種功能的整合，可以將多個主動晶片整合在一個封裝結構。因此，如何使具有多個主動晶片的封裝結構的製造良率或品質可以提升，或可以使多個主動晶片的封裝結構的製造成本可以降低，實已成目前亟欲解決的課題。
本發明提供一種封裝結構，其具有較佳的品質。
本發明提供一種封裝結構的製造方法，其具有較佳的良率或較低的成本。
本發明的封裝結構包括第一線路板、第二線路板、第一模封體、多個導電端子以及封裝件。第一線路板具有第一頂面及相對於第一頂面的第一底面。第二線路板具有第二頂面及相對於第二頂面的第二底面。第一模封體包覆第一線路板及第二線路板。多個導電端子配置在第一底面或第二底面上且電性連接於第一線路板或第二線路板。封裝件配置在第一頂面或第二頂面上且電性連接於第一線路板及第二線路板。封裝件包括第一晶片、第二晶片、晶片模封體、線路層以及多個導電封裝端子。晶片模封體包覆第一晶片及第二晶片。線路層位於晶片模封體上且電性連接於第一晶片及第二晶片。多個導電封裝端子位於線路層上且電性連接於第一線路板或第二線路板。
本發明的封裝結構的製造方法包括以下步驟：提供第一線路板，其具有第一頂面及相對於第一頂面的第一底面；提供第二線路板，其具有第二頂面及相對於第二頂面的第二底面；形成第一模封體，其包覆第一線路板及第二線路板；配置封裝件在第一頂面或第二頂面上，封裝件電性連接於第一線路板及第二線路板，其中封裝件包括第一晶片、第二晶片、晶片模封體、線路層以及多個導電封裝端子，晶片模封體包覆第一晶片及第二晶片，線路層位於晶片模封體上且電性連接於第一晶片及第二晶片，多個導電封裝端子位於線路層上且電性連接於第一線路板或第二線路板；形成多個導電端子在第一底面或第二底面上，且多個導電端子電性連接於第一線路板或第二線路板。
基於上述，在具有多晶片的封裝結構中，藉由多個線路板電性連接於多晶片的方式，對於封裝結構的製造方法可以較為簡單且/或成本也可以較為低廉。並且，對於封裝結構的整體線路佈局中可以降低連接於晶片之間的線路層的負載，而可以提升封裝結構的品質。
本文所使用之方向用語（例如，上、下、右、左、前、後、頂部、底部）僅作為參看所繪圖式使用且不意欲暗示絕對定向。另外，為求清楚表示，於圖式中可能省略繪示了部分的膜層或構件。
除非另有明確說明，否則本文所述任何方法絕不意欲被解釋為要求按特定順序執行其步驟。
參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施例。圖式中的層或區域的厚度、尺寸或大小會為了清楚起見而放大。相同或相似之參考號碼表示相同或相似之元件，以下段落將不再一一贅述。
圖1A至圖1I是依照本發明的第一實施例的一種封裝結構的部分製造方法的部分剖視示意圖。圖1J是依照本發明的第一實施例的一種封裝結構的部分剖視示意圖。圖1K是依照本發明的第一實施例的一種封裝結構的部分上視示意圖。
請參照圖1A，在本實施例中，可以提供線路母板190。線路母板190可以是無矽基底（Si-substrate-free）線路板。舉例而言，線路母板190中的絕緣材193例如可以包括環氧樹脂預浸片（epoxy prepreg sheet）、聚芳醯胺預浸片（aramid prepreg sheet）或其他類似的高分子預浸片（polymer prepreg sheet）。
在本實施例中，線路母板190可以包括多個線路層191以及位於線路層191之間的導電微孔（conductive microvia）192。在一實施例中，導電微孔192的側壁192c基本上垂直於所連接的線路層191的表面191a。
在一實施例中，線路母板190可以是高密度連接板（high density interconnect substrate；HDI substrate）。
請參照圖1A至圖1B，在本實施例中，可以對線路母板190進行單一化製程（singulation process），以構成多個的第一線路板110或第二線路板120。在本實施例中，可以構成至少一個第一線路板110及至少一個第二線路板120，但本發明不限於此。在一實施例中，藉由前述的方式，可以對相似於線路母板190的線路母板190進行單一化製程，以構成多個第一線路板110。在一實施例中，藉由前述的方式，可以對相似於線路母板190的線路母板190進行單一化製程，以構成多個第二線路板120。
在本實施例中，單一化製程例如可以包括切割製程（dicing process/cutting process）以至少切穿線路母板190的絕緣材193，但本發明不限於此。
值得注意的是，前述對於第一線路板110及/或第二線路板120的形成方式只是示例性的說明，本發明並未限定需以前述的方式形成或提供第一線路板110及/或第二線路板120。另外，藉由相同或相似於前述的方式，也可以形成或提供其他相同或相似於第一線路板110或第二線路板120的線路板。
請參照圖1B及圖1C，提供第一線路板110。第一線路板110具有第一頂面110a、第一底面110b及第一側面110c。第一底面110b相對於第一頂面110a。第一側面110c連接於第一頂面110a與第一底面110b。
在本實施例中，第一線路板110可以是無矽基底線路板。舉例而言，第一線路板110中的絕緣材113例如可以包括環氧樹脂預浸片、聚芳醯胺預浸片或其他類似的高分子預浸片。
在一實施例中，第一線路板110可以包括多個線路層111以及位於線路層111之間的導電微孔112。在一實施例中，導電微孔112的側壁112c基本上垂直於所連接的線路層111的表面111a。
在一實施例中，第一線路板110可以是高密度連接板。
在本實施例中，可以在第一線路板110的第一頂面110a上形成多個第一導電連接件161。第一導電連接件161可以電性連接於第一線路板110中對應的線路。
在一實施例中，第一導電連接件161可以包括導電柱、焊球（solder ball）、導電凸塊或具有其他形式或形狀的導電連接件。第一導電連接件161可以經由電鍍、沉積、置球（ball placement）、迴焊（reflow）及/或其他適宜的製程來形成且配置於第一線路板110的第一頂面110a上。
在一實施例中，第一導電連接件161可以是在對前述線路母板190（標示於圖1A）進行單一化製程之前即被形成。在一實施例中，第一導電連接件161可以是在對前述線路母板190（標示於圖1A）進行單一化製程之後才被形成。
請參照圖1B及圖1C，提供第二線路板120。第二線路板120具有第二頂面120a、第二底面120b及第二側面120c。第二底面120b相對於第二頂面120a。第二側面120c連接於第二頂面120a與第二底面120b。
在本實施例中，第二線路板120可以是無矽基底線路板。舉例而言，第二線路板120中的絕緣材123例如可以包括環氧樹脂預浸片、聚芳醯胺預浸片或其他類似的高分子預浸片。
在一實施例中，第二線路板120可以包括多個線路層121以及位於線路層121之間的導電微孔122。在一實施例中，導電微孔122的側壁122c基本上垂直於所連接的線路層121的表面121a。
在一實施例中，第二線路板120可以是高密度連接板。
在本實施例中，可以在第二線路板120的第二頂面120a上形成多個第二導電連接件162。第二導電連接件162可以電性連接於第二線路板120中對應的線路。
在一實施例中，第二導電連接件162可以包括導電柱、焊球、導電凸塊或具有其他形式或形狀的導電連接件。第二導電連接件162可以經由電鍍、沉積、置球、迴焊及/或其他適宜的製程來形成且配置於第二線路板120的第二頂面120a上。
在一實施例中，第二導電連接件162可以是在對前述線路母板190（標示於圖1A）進行單一化製程之前即被形成。在一實施例中，第二導電連接件162可以是在對前述線路母板190（標示於圖1A）進行單一化製程之後才被形成。
請參照圖1C，在本實施例中，可以將第一線路板110及/或第二線路板120配置於載板91上。載板91可以由玻璃、晶圓基板、金屬或其他適宜的材料所製成，只要前述的材料能夠於後續的製程中，承載形成於其上的結構或構件。
在本實施例中，載板91上可以具有離型層92。離型層92可以為光熱轉換（light to heat conversion，LTHC）黏著層，但本發明不限於此。
值得注意的是，本發明並未限定第一線路板110及第二線路板120的配置順序。
在圖1C所繪示的剖面中，僅示例性地繪示二個第一線路板110及二個第二線路板120，但本發明對於配置於載板91上的第一線路板110及第二線路板120的數量並不加以限制。
另外，在其他未繪示的剖面上，可能可以具有其他的線路板。舉例而言，可以將其他相同或相似於第一線路板110或第二線路板120的線路板（如：圖1J中所繪示的線路板178、179）配置於載板91上。
在一實施例中，可以在將第一線路板110配置於載板91上之前形成第一導電連接件161。在一實施例中，可以在將第一線路板110配置於載板91上之後形成第一導電連接件161。
在一實施例中，可以在將第二線路板120配置於載板91上之前形成第二導電連接件162。在一實施例中，可以在將第二線路板120配置於載板91上之後形成第二導電連接件162。
在一實施例中，被配置於載板91上的第一線路板110及/或第二線路板120可以為已知合格基板（known good substrate，KGS）。舉例而言，在將第一線路板110及/或第二線路板120配置於載板91上之前，可以對第一線路板110及/或第二線路板120進行電性測試（如：斷短路測試（Open/Short test；O/S test））、外觀檢查（如：自動光學辨識（Auto Optical Inspection；AOI））或其他適宜的檢查或測試步驟。如此一來，可以確認被配置於載板91上的第一線路板110及/或第二線路板120具有良好的功能，而可以提升封裝結構100（標示於圖1J或圖1K）的良率。
請參照圖1D至1E，於載板91上形成包覆第一線路板110及第二線路板120的第一模封體140。
在一實施例中，形成第一模封體140的步驟舉例如下。
舉例而言，請參照圖1D，可以形成覆蓋第一線路板110及第二線路板120的模封材料（molding material）149。在一實施例中，模封材料149例如是藉由模塑製程或其他適宜的方法將熔融的模塑化合物形成於載板91上。然後，使熔融的模塑化合物冷卻並且固化。
在本實施例中，模封材料149可以更包覆第一導電連接件161或第二導電連接件162，但本發明不限於此。
請參照圖1D至1E，在形成模封材料149（標示於圖1D）之後，可以進行減薄製程，以移除部分的模封材料149，以形成側向覆蓋第一線路板110及第二線路板120的第一模封體140（標示於圖1E）。在本實施例中，第一模封體140可以暴露出第一導電連接件161的第一導電頂面161a及第二導電連接件162的第二導電頂面162a。
在一實施例中，減薄製程例如包括化學機械研磨（chemical mechanical polishing；CMP）、機械研磨（mechanical grinding）、蝕刻（etching）或其他適宜的製程，但本發明不限於此。
在一實施例中，在經由上述的減薄製程之後，第一導電連接件161的第一導電頂面161a、第二導電連接件162的第二導電頂面162a及第一模封體140的模封頂面140a可以基本上共面（coplaner）。
在一實施例中，在上述的減薄製程中，部分的第一導電連接件161及/或部分的第二導電連接件162可能可以被些微地移除。
在本實施例中，第一模封體140可以直接接觸第一線路板110的第一側面110c及/或第二線路板120的第二側面120c。在本實施例中，部分的第一模封體140可以位於第一線路板110及第二線路板120之間。
在本實施例中，第一模封體140可以直接接觸第一線路板110的第一頂面110a及/或第二線路板120的第二頂面120a。
在一實施例中，藉由第一導電連接件161，可以降低在形成第一模封體140的步驟中對第一線路板110的第一頂面110a所造成的損傷或損壞。如此一來，可以提升封裝結構100（標示於圖1J或圖1K）的良率。
在一實施例中，藉由第二導電連接件162，可以降低在形成第一模封體140的步驟中對第二線路板120的第二頂面120a所造成的損傷或損壞。如此一來，可以提升封裝結構100（標示於圖1J或圖1K）的良率。
請參照圖1F，在本實施例中，可以在第一線路板110的第一頂面110a或第二線路板120的第二頂面120a上形成絕緣層130。在本實施例中，絕緣層130可以更位於第一模封體140的模封頂面140a上。
在本實施例中，絕緣層130的開口131可以暴露出第一導電連接件161的第一導電頂面161a。舉例而言，絕緣層130可以直接接觸第一導電連接件161的部分第一導電頂面161a，且絕緣層130的開口131可以暴露出第一導電連接件161的其餘部分第一導電頂面161a。
在本實施例中，絕緣層130的開口132可以暴露出第二導電連接件162的第二導電頂面162a。舉例而言，絕緣層130可以直接接觸第二導電連接件162的部分第二導電頂面162a，且絕緣層130的開口132可以暴露出第二導電連接件162的其餘部分第二導電頂面162a。
請參照圖1G，配置封裝件150於第一線路板110的第一頂面110a或第二線路板120的第二頂面120a上，且使封裝件150電性連接於第一線路板110中對應的線路及第二線路板120中對應的線路。
封裝件150包括第一晶片151、第二晶片152、晶片模封體154、線路層153以及多個導電封裝端子156。晶片模封體154包覆第一晶片151及第二晶片152。線路層153位於晶片模封體154上。第一晶片151電性連接於線路層153中對應的線路。第二晶片152電性連接於線路層153中對應的線路。導電封裝端子156位於線路層153上且電性連接於線路層153中對應的線路。第一晶片151可以藉由線路層153中對應的線路及對應的導電封裝端子156電性連接於第一線路板110中對應的線路及/或第二線路板120中對應的線路。第二晶片152可以藉由線路層153中對應的線路及對應的導電封裝端子156電性連接於第一線路板110中對應的線路及/或第二線路板120中對應的線路。
在本實施例中，封裝件150可以更包括電子元件155。電子元件155可以配置於線路層153上且在相對於第一晶片151及第二晶片152的一側。電子元件155可以電性連接於線路層153中對應的線路。在一實施例中，電子元件155可以是被動元件，但本發明不限於此。
在一實施例中，第一晶片151或第二晶片152可以是電力管理晶片（power management integrated circuit，PMIC）、微機電系統晶片（micro-electro-mechanical-system，MEMS）、特殊應用積體電路晶片（Application-specific integrated circuit，ASIC）、動態隨機存取記憶體晶片（dynamic random access memory，DRAM）、靜態隨機存取記憶體晶片（static random access memory，SRAM）、高頻寬記憶體（High Bandwidth Memory，HBM）晶片、系統晶片（system on chip，SoC）或其他類似的高效能運算（High Performance Computing，HPC）晶片，但本發明不限於此。
在一實施例中，第一晶片151與第二晶片152之間可以是同質的（homogeneous）晶片也可以是異質的（heterogeneous）晶片，於本發明並不加以限制。
在一實施例中，封裝件150可以是扇出封裝件（fan-out package）、晶圓級晶片尺寸封裝件（Wafer Level Chip Scale Package；WLCSP）、覆晶晶片尺寸級封裝件（Flip Chip Chip Scale Package；FCCSP）、窗型球閘陣列封裝件（Window BGA package；wBGA package）或其他適宜的封裝件，於本發明並不加以限制。
在一實施例中，被配置於第一線路板110或第二線路板120上的封裝件150可以為已知合格封裝件（known good package，KGP）。舉例而言，在將封裝件150配置於第一線路板110或第二線路板120上之前，可以對封裝件150進行電性測試（如：斷短路測試）、外觀檢查（如：自動光學辨識）或其他適宜的檢查或測試步驟。如此一來，可以確認被配置於第一線路板110或第二線路板120上的封裝件150具有良好的功能，而可以提升封裝結構100（標示於圖1J或圖1K）的良率。
在本實施例中，可以在封裝件150與第一線路板110/第二線路板120之間形成填充層159，但本發明不限於此。填充層159例如是毛細填充膠或其他適宜的填充材料，但本發明不限於此。
值得注意的是，在圖1G中，僅示例性地繪示二個封裝件150，但本發明對於配置於第一線路板110或第二線路板120上的封裝件150的數量並不加以限制。
請參照圖1H，在本實施例中，可以配置殼體171於第一模封體140的模封頂面140a上。
在本實施例中，殼體171可以位於絕緣層130上。在一實施例中，殼體171與絕緣層130之間可以具有黏著材，而可以使殼體171可以與絕緣層130相黏接。
請參照圖1H至圖1I，可以移除載板91（標示於圖1H），以暴露出第一線路板110的第一底面110b及第二線路板120的第二底面120b。
請參照圖1I，配置第一導電端子163於第一線路板110的第一底面110b上，且使第一導電端子163電性連接於第一線路板110中對應的線路。
請參照圖1I，配置第二導電端子164於第二線路板120的第二底面120b上，且使第二導電端子164電性連接於第二線路板120中對應的線路。
在本實施例中，第一導電端子163或第二導電端子164可以包括焊球或具有其他形式或形狀的導電端子。第一導電端子163或第二導電端子164可以經由置球、迴焊及/或其他適宜的製程來形成。
值得注意的是，本發明並未限定配置第一導電端子163的步驟以及配置第二導電端子164的步驟的先後順序。
請參照圖1H至圖1I，在本實施例中，可以經由單一化製程（singulation process），以構成多個封裝結構100。單一化製程例如可以包括切割製程（dicing process/cutting process）以至少切穿第一模封體140。
值得注意的是，在進行單一化製程之後，相似的元件符號將用於單一化後的元件。舉例而言，第一線路板110（如圖1H所示）於單一化後可以為第一線路板110（如圖1I所示），第二線路板120（如圖1H所示）於單一化後可以為第二線路板120（如圖1I所示），第一模封體140（如圖1H所示）於單一化後可以為第一模封體140（如圖1I所示），第一導電端子163（如圖1H所示）於單一化後可以為第一導電端子163（如圖1I所示），第二導電端子164（如圖1H所示）於單一化後可以為第二導電端子164（如圖1I所示），封裝件150（如圖1H所示）於單一化後可以為封裝件150（如圖1I所示），諸如此類。其他單一化後的元件將依循上述相同的元件符號規則，於此不加以贅述或特別繪示。
值得注意的是，本發明並未限定配置殼體171的步驟以及進行單一化製程的步驟的先後順序。
經過上述步驟後即可大致上完成本實施例的封裝結構100的製作。
請參照圖1F及圖1G，封裝結構100包括第一線路板110、第二線路板120、第一模封體140、多個導電端子163、164以及封裝件150。第一線路板110具有第一頂面110a及相對於第一頂面110a的第一底面110b。第二線路板120具有第二頂面120a及相對於第二頂面120a的第二底面120b。第一模封體140包覆第一線路板110及第二線路板120。導電端子163、164可以包括第一導電端子163或第二導電端子164。第一導電端子163配置在第一線路板110的第一底面110b上。第一導電端子163電性連接於第一線路板110中對應的線路。第二導電端子164配置在第二線路板120的第二底面120b上。第二導電端子164電性連接於第二線路板120中對應的線路。封裝件150包括第一晶片151、第二晶片152、晶片模封體154、線路層153以及多個導電封裝端子156。封裝件150配置在第一線路板110的第一頂面110a或第二線路板120的第二頂面120a上。封裝件150電性連接於第一線路板110中對應的線路及第二線路板120中對應的線路。
在本實施例中，第一線路板110的第一頂面110a、第一線路板110的第一底面110b、第二線路板120的第二頂面120a及第二線路板120的第二底面120b中的至少其中兩者基本上平行，但本發明不限於此。
在本實施例中，在垂直於第一線路板110的第一頂面110a或第二線路板120的第二頂面120a的投影方向D1上，第一線路板110及第二線路板120不重疊。在一實施例中，第一線路板110及第二線路板120可以是以側向（side by side）方式配置。
在本實施例中，在垂直於第一線路板110的第一頂面110a或第二線路板120的第二頂面120a的投影方向D1上，第一線路板110及第二線路板120重疊於封裝件150。在一實施例中，在投影方向D1上，第一線路板110部分重疊於封裝件150，且第二線路板120部分重疊於封裝件150。
在本實施例中，部分的第一模封體140可以位於第一線路板110及封裝件150之間。
在本實施例中，封裝結構100可以更包括第一導電連接件161。第一導電連接件161可以配置在第一線路板110的第一頂面110a上。封裝件150可以藉由對應的第一導電連接件161電性連接於第一線路板110中對應的線路。第一導電連接件161可以嵌入位於第一線路板110及封裝件150之間的部分第一模封體140。也就是說，位於第一線路板110及封裝件150之間的部分第一模封體140可以側向覆蓋第一導電連接件161。
在本實施例中，部分的第一模封體140可以位於第二線路板120及封裝件150之間。
在本實施例中，封裝結構100可以更包括第二導電連接件162。第二導電連接件162可以配置在第二線路板120的第二頂面120a上。封裝件150可以藉由對應的第二導電連接件162電性連接於第二線路板120中對應的線路。第二導電連接件162可以嵌入位於第二線路板120及封裝件150之間的部分第一模封體140。也就是說，位於第二線路板120及封裝件150之間的部分第一模封體140可以側向覆蓋第二導電連接件162。
在本實施例中，封裝結構100可以更包括絕緣層130。
在本實施例中，絕緣層130可以位於第一線路板110的第一頂面110a上。封裝件150中對應的導電封裝端子156可以嵌入絕緣層130，以使封裝件150中對應的導電封裝端子156可以藉由對應的第一導電連接件161電性連接於第一線路板110中對應的線路。
在一實施例中，第一導電連接件161的相對兩端可以直接接觸封裝件150的導電封裝端子156及第一線路板110中對應的線路。
在一實施例中，封裝件150與第一線路板110之間的訊號傳輸距離基本上相同於封裝件150與第一線路板110之間的物理距離。舉例而言，封裝件150與第一線路板110之間的訊號可以藉由對應的導電件（如：第一導電連接件161）傳輸，且封裝件150與第一線路板110之間的距離基本上等於前述的導電件的高度或厚度（如：對應的第一導電連接件161的高度）。如此一來，可能可以提升封裝件150與第一線路板110之間訊號傳輸的品質及效率。
在本實施例中，絕緣層130可以位於第二線路板120的第二頂面120a上。封裝件150中對應的導電封裝端子156可以嵌入絕緣層130，以使封裝件150中對應的導電封裝端子156可以藉由對應的第二導電連接件162電性連接於第二線路板120中對應的線路。
在一實施例中，第二導電連接件162的相對兩端可以直接接觸封裝件150的導電封裝端子156及第二線路板120中對應的線路。
在一實施例中，封裝件150與第二線路板120之間的訊號傳輸距離基本上相同於封裝件150與第二線路板120之間的物理距離。舉例而言，封裝件150與第二線路板120之間的訊號可以藉由對應的導電件（如：第二導電連接件162）傳輸，且封裝件150與第二線路板120之間的距離基本上等於前述的導電件的高度或厚度（如：對應的第二導電連接件162的高度）。如此一來，可能可以提升封裝件150與第二線路板120之間訊號傳輸的品質及效率。
在一實施例中，封裝件150與第一線路板110之間以及封裝件150與第二線路板120之間可以不具有重佈線路（redistribution circuit）。並且，在封裝結構100的製造過程中，在將封裝件150結合至第一線路板110以及第二線路板120之間，可以藉由適宜的檢查或測試步驟以確認封裝件150為已知合格封裝件，且第一線路板110以及第二線路板120為已知合格基板。如此一來，可以提升封裝結構100在製造過程中的良率。
在本實施例中，第一模封體140可以不直接接觸封裝件150，但本發明不限於此。舉例而言，第一模封體140與封裝件150之間可以藉由絕緣層130而彼此分離。
在本實施例中，封裝結構100可以更包括殼體171。殼體171配置於第一模封體140的模封頂面140a上。殼體171具有容置空間171a，且封裝件150位於容置空間171a內。
在一實施例中，殼體171可以包括硬質的材質。如此一來，可以藉由殼體171保護位於其內的構件（如：封裝件150）。
在一實施例中，殼體171可以包括導電材質。在一可能的實施例中，導電的殼體171可以作為電磁干擾屏蔽（electromagnetic interference shielding；EMI shielding），而可以降低電磁干擾，但本發明不限於此。在一可能的實施例中，殼體171的導電部分可以作為天線，但本發明不限於此。
在一實施例中，殼體171可以包括導熱材質。導熱的殼體171可以熱耦接於封裝件150。
在本實施例中，殼體171與封裝件150之間可以具有空氣間隙（air gap）171b。
在本實施例中，在具有包含多晶片（如：第一晶片151及第二晶片152）的封裝件150的封裝結構100中，多個晶片之間（如：第一晶片151及第二晶片152之間）需藉由對應的線路進行電源或訊號（如：封裝件150中的線路層153）的傳輸，且各個晶片需藉由對應的線路與外界（如：第一晶片151及第二晶片152藉由對應的線路板與連接於導電端子的外部電子元件）進行電源或訊號的傳輸。因此，藉由多個線路板（如：第一線路板110及第二線路板120）的方式，可以使封裝結構100的製造方法可以較為簡單且/或成本也可以較為低廉。並且，對於封裝結構100的整體線路佈局中可以降低封裝件150的線路層153的負載（如：可以降低線路層153的導電層層數、容易最佳化線路層153的導電層線寬、線距及/或線路佈局）。如此一來，可以提升封裝結構100的品質。舉例而言，可以藉由封裝件150及線路板110、120的導電層層數進行整體線路佈局、成本及/或製程之間的最佳化調配；若考量線路板110、120的導電層層數太多而可能導致良率降低，則可以藉由封裝件150的線路層153上的細線寬（fine pitch）條整或線寬/線距（Line/Space；L/S）條整，降低線路板110、120的導電層層數；或是，若封裝件150的線路層153的層數太多而可能導致成本提升或製程中的翹曲度（warpage）較難，則可藉由線路佈局的方式將一些線路調整至線路板110、120。
圖2是依照本發明的第二實施例的一種封裝結構的部分剖視示意圖。第二實施例的封裝結構200的製造方法與第一實施例的封裝結構100的製造方法相似，其類似的構件以相同的標號表示，且具有類似的功能、材質或形成方式，並省略描述。
請參照圖2，在本實施例中，封裝結構200包括第一線路板110、第二線路板120、第一模封體140、多個導電端子163、164、封裝件150以及加強支撐件（stiffening support member）272。加強支撐件272可以嵌入於第一模封體140。也就是說，第一模封體140可以覆蓋部分的加強支撐件272。
在一實施例中，加強支撐件272可以包括支撐用晶粒（supporting die）。舉例而言，可以將不合格晶粒（ugly die）、失效晶粒（failed die）或其他類似的廢晶粒（dummy die）作為支撐用晶粒。如此一來，可以降低製作上的成本。
在一實施例中，加強支撐件272可以包括硬質支撐環。舉例而言，加強支撐件272可以包括環型的金屬條。
在一實施例中，加強支撐件272可以降低結構的翹曲（warpage）。
圖3是依照本發明的第三實施例的一種封裝結構的部分剖視示意圖。第三實施例的封裝結構300的製造方法與第一實施例的封裝結構100的製造方法相似，其類似的構件以相同的標號表示，且具有類似的功能、材質或形成方式，並省略描述。
請參照圖3，在本實施例中，封裝結構300包括第一線路板110、第二線路板120、第一模封體140、多個導電端子163、164、封裝件150以及第二模封體374。第二模封體374可以位於第一模封體140的模封頂面140a上。第二模封體374可以包覆封裝件150。
第二模封體374的材質或形成方式可以相同或相似於第一模封體140，故於此不加以贅述。
在本實施例中，第二模封體374可以不直接接觸第一模封體140，但本發明不限於此。舉例而言，第一模封體140與第二模封體374之間可以藉由絕緣層130而彼此分離。
圖4是依照本發明的第四實施例的一種封裝結構的部分剖視示意圖。第四實施例的封裝結構400的製造方法與第一實施例的封裝結構100的製造方法相似，其類似的構件以相同的標號表示，且具有類似的功能、材質或形成方式，並省略描述。
請參照圖4，在本實施例中，封裝結構400包括第一線路板110、第二線路板120、第一模封體140、多個導電端子163、164以及封裝件450。封裝件450包括第一晶片151、第二晶片152、晶片模封體454、線路層153以及多個導電封裝端子156。晶片模封體454可以暴露出部分的第一晶片151及/或部分的第二晶片152。舉例而言，晶片模封體454可以暴露出部分的第一晶片151的背面及/或第二晶片152的背面。
在本實施例中，殼體171與封裝件450之間可以具有熱界面材料（thermal interface material；TIM）476。熱界面材料476可以熱耦接於殼體171及封裝件450。舉例而言，熱界面材料476可以熱耦接於殼體171及封裝件450中的第一晶片151及/或第二晶片152。如此一來，在第一晶片151及/或第二晶片152運作時，所產生的熱量可以較容易地藉由熱界面材料476逸散至殼體171。
綜上所述，在本發明具有包含多晶片（如：第一晶片及第二晶片）的封裝件的封裝結構中，多個晶片之間（如：第一晶片及第二晶片之間）需藉由對應的線路進行電源或訊號（如：封裝件中的線路層）的傳輸，且各個晶片需藉由對應的線路與外界（如：第一晶片及第二晶片藉由對應的線路板與連接於導電端子的外部電子元件）進行電源或訊號的傳輸。因此，藉由多個線路板（如：第一線路板及第二線路板）的方式，可以使封裝結構的製造方法可以較為簡單且/或成本也可以較為低廉。並且，對於封裝結構的整體線路佈局中可以降低封裝件的線路層的負載（如：可以降低線路層的導電層層數、容易最佳化線路層的導電層線寬、線距及/或線路佈局）。如此一來，可以提升封裝結構的品質。
100、200、300、400:封裝結構 110:第一線路板 110a:第一頂面 110b:第一底面 110c:第一側面 111:線路層 111a:表面 112:導電微孔 112c:側壁 113:絕緣材 120:第二線路板 120a:第二頂面 120b:第二底面 120c:第二側面 121:線路層 121a:表面 122:導電微孔 122c:側壁 123:絕緣材 130:絕緣層 131、132:開口 149:模封材料 140:第一模封體 140a:模封頂面 150、450:封裝件 151:第一晶片 152:第二晶片 153:線路層 154、454:晶片模封體 155:電子元件 156:導電封裝端子 159:填充層 161:第一導電連接件 161a:第一導電頂面 162:第二導電連接件 162a:第二導電頂面 163:第一導電端子 164:第二導電端子 171:殼體 171a:容置空間 171b:空氣間隙 272:加強支撐件 374:第二模封體 476：熱界面材料 178、179:線路板 D1:投影方向 190:線路母板 191:線路層 191a:表面 192:導電微孔 192c:側壁 193:絕緣材 91:載板 92:離型層
圖1A至圖1I是依照本發明的第一實施例的一種封裝結構的部分製造方法的部分剖視示意圖。 圖1J是依照本發明的第一實施例的一種封裝結構的部分剖視示意圖。 圖1K是依照本發明的第一實施例的一種封裝結構的部分上視示意圖。 圖2是依照本發明的第二實施例的一種封裝結構的部分剖視示意圖。 圖3是依照本發明的第三實施例的一種封裝結構的部分剖視示意圖。 圖4是依照本發明的第四實施例的一種封裝結構的部分剖視示意圖。
100:封裝結構
110:第一線路板
110a:第一頂面
110b:第一底面
110c:第一側面
120:第二線路板
120a:第二頂面
120b:第二底面
120c:第二側面
140:第一模封體
140a:模封頂面
150:封裝件
151:第一晶片
152:第二晶片
153:線路層
154:晶片模封體
155:電子元件
156:導電封裝端子
159:填充層
163:第一導電端子
164:第二導電端子
171:殼體
171a:容置空間
171b:空氣間隙
D1:投影方向

Claims (10)

  1. 一種封裝結構，包括： 第一線路板，具有第一頂面及相對於所述第一頂面的第一底面； 第二線路板，具有第二頂面及相對於所述第二頂面的第二底面； 第一模封體，包覆所述第一線路板及所述第二線路板； 多個導電端子，配置在所述第一底面或所述第二底面上，且電性連接於所述第一線路板或所述第二線路板；以及 封裝件，配置在所述第一頂面或所述第二頂面上且電性連接於所述第一線路板及所述第二線路板，且所述封裝件包括： 第一晶片； 第二晶片； 晶片模封體，包覆所述第一晶片及所述第二晶片； 線路層，位於所述晶片模封體上且電性連接於所述第一晶片及所述第二晶片；以及 多個導電封裝端子，位於所述線路層上且電性連接於所述第一線路板或所述第二線路板。
  2. 如請求項1所述的封裝結構，其中所述第一線路板及所述第一線路板為無矽基底線路板。
  3. 如請求項1所述的封裝結構，其中在垂直於所述第一頂面或所述第二頂面的投影方向上，所述第一線路板及所述第二線路板不重疊。
  4. 如請求項3所述的封裝結構，其中在所述投影方向上，所述第一線路板及所述第二線路板重疊於所述封裝件。
  5. 如請求項1所述的封裝結構，其中部分的所述第一模封體位於所述第一線路板及所述封裝件之間或位於所述第二線路板及所述封裝件之間。
  6. 如請求項5所述的封裝結構，更包括： 多個導電連接件，配置在所述第一頂面或所述第二頂面上且嵌入部分的所述第一模封體，所述封裝件藉由對應的所述多個導電連接件電性連接於所述第一線路板或所述第二線路板。
  7. 如請求項1所述的封裝結構，其中所述第一模封體不直接接觸所述封裝件。
  8. 如請求項1所述的封裝結構，更包括： 絕緣層，位於所述第一頂面或所述第二頂面上，且所述封裝件的所述多個導電封裝端子嵌入所述絕緣層。
  9. 如請求項8所述的封裝結構，更包括： 多個導電連接件，配置在所述第一頂面或所述第二頂面上，且所述絕緣層更位於所述多個導電連接件上且暴露出各個所述多個導電連接件的一部分，所述封裝件藉由對應的所述多個導電連接件電性連接於所述第一線路板或所述第二線路板。
  10. 一種封裝結構的製造方法，包括： 提供第一線路板，其具有第一頂面及相對於所述第一頂面的第一底面； 提供第二線路板，其具有第二頂面及相對於所述第二頂面的第二底面； 形成第一模封體，其包覆所述第一線路板及所述第二線路板； 配置封裝件在所述第一頂面或所述第二頂面上，所述封裝件電性連接於所述第一線路板及所述第二線路板，且所述封裝件包括： 第一晶片； 第二晶片； 晶片模封體，包覆所述第一晶片及所述第二晶片； 線路層，位於所述晶片模封體上且電性連接於所述第一晶片及所述第二晶片；以及 多個導電封裝端子，位於所述線路層上且電性連接於所述第一線路板或所述第二線路板；以及 形成多個導電端子在所述第一底面或所述第二底面上，且所述多個導電端子電性連接於所述第一線路板或所述第二線路板。
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