TWI733542B - 封裝結構及其製造方法 - Google Patents

封裝結構及其製造方法 Download PDF

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TWI733542B
TWI733542B TW109126211A TW109126211A TWI733542B TW I733542 B TWI733542 B TW I733542B TW 109126211 A TW109126211 A TW 109126211A TW 109126211 A TW109126211 A TW 109126211A TW I733542 B TWI733542 B TW I733542B
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circuit board
chip
circuit
connection surface
redistributed
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TW109126211A
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TW202127607A (zh
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徐宏欣
林南君
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力成科技股份有限公司
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Abstract

一種封裝結構，其包括重佈線路結構、第一晶片、第二晶片、第一線路板、第二線路板以及多個導電端子。重佈線路結構具有第一連接面及相對於第一連接面的第二連接面。第一晶片及第二晶片配置在第一連接面上且電性連接於重佈線路結構。第一線路板及第二線路板配置在第二連接面上且電性連接於重佈線路結構。多個導電端子配置在第一線路板或第二線路板上。導電端子電性連接於第一線路板或第二線路板。一種封裝結構的製造方法亦被提出。

Description

封裝結構及其製造方法
本發明是有關於一種封裝結構及其製造方法，且特別是有關於一種具有多個晶片及多個線路板的封裝結構及其製造方法。
近年來，電子設備對於人類的生活越來越重要。為了加速各種功能的整合，可以將多個主動晶片整合在一個封裝結構。因此，如何使具有多個主動晶片的封裝結構的製造良率或品質可以提升，或可以使多個主動晶片的封裝結構的製造成本可以降低，實已成目前亟欲解決的課題。
本發明提供一種封裝結構，其具有較佳的品質。
本發明提供一種封裝結構的製造方法，其具有較佳的良率或較低的成本。
本發明的封裝結構包括重佈線路結構、第一晶片、第二晶片、第一線路板、第二線路板以及多個導電端子。重佈線路結構具有第一連接面及相對於第一連接面的第二連接面。第一晶片配置在第一連接面上且電性連接於重佈線路結構。第二晶片配置在第一連接面上且電性連接於重佈線路結構。第一線路板配置在第二連接面上且電性連接於重佈線路結構。第二線路板配置在第二連接面上且電性連接於重佈線路結構。多個導電端子配置在第一線路板或第二線路板上。導電端子電性連接於第一線路板或第二線路板。
本發明的封裝結構的製造方法包括以下步驟：形成重佈線路結構，其具有第一連接面及相對於第一連接面的第二連接面；配置第一晶片於第一連接面上，且使第一晶片電性連接於重佈線路結構；配置第二晶片於第一連接面上，且使第二晶片電性連接於重佈線路結構；配置第一線路板於第二連接面上，且使第一線路板電性連接於重佈線路結構；配置第二線路板於第二連接面上，且使第二線路板電性連接於重佈線路結構；以及配置多個導電端子於第一線路板或第二線路板上，且使多個導電端子電性連接於第一線路板或第二線路板。
基於上述，在具有多晶片的封裝結構中，藉由多個線路板配置於重佈線路結構上的方式，對於封裝結構的製造方法可以較為簡單且/或成本也可以較為低廉。並且，對於封裝結構的整體線路佈局中可以降低重佈線路結構的負載，而可以提升封裝結構的品質。
本文所使用之方向用語（例如，上、下、右、左、前、後、頂部、底部）僅作為參看所繪圖式使用且不意欲暗示絕對定向。另外，為求清楚表示，於圖式中可能省略繪示了部分的膜層或構件。
除非另有明確說明，否則本文所述任何方法絕不意欲被解釋為要求按特定順序執行其步驟。
參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施例。圖式中的層或區域的厚度、尺寸或大小會為了清楚起見而放大。相同或相似之參考號碼表示相同或相似之元件，以下段落將不再一一贅述。
圖1A至圖1F是依照本發明的第一實施例的一種封裝結構的部分製造方法的部分剖視示意圖。圖1G是依照本發明的第一實施例的一種封裝結構的部分上視示意圖。
請參照圖1A，形成重佈線路結構110。舉例而言，可以藉由一般常用的半導體製程，以於第一載板91上形成重佈線路結構110。第一載板91可以由玻璃、晶圓基板、金屬或其他適宜的材料所製成，只要前述的材料能夠於後續的製程中，承載形成於其上的結構或構件。
在本實施例中，重佈線路結構110可以具有第一連接面110a及第二連接面110b。第二連接面110b相對於第一連接面110a，且第二連接面110b面向第一載板91。
在本實施例中，第一載板91上可以具有離型層94。離型層94可以為光熱轉換（light to heat conversion，LTHC）黏著層，但本發明不限於此。
請參照圖1B，配置第一晶片120於重佈線路結構110的第一連接面110a上，且使第一晶片120電性連接於重佈線路結構110中對應的線路。
在本實施例中，第一晶片120可以包括基材121以及線路結構122。基材121的一側具有元件區（未繪示）。元件區所位於的第一晶片120的表面可以被稱為主動面120a。線路結構122可以位於主動面120a上。在一般晶片設計中，元件區內的元件（如：第一晶片120的元件區內的元件）可以藉由對應的後段金屬內連線（Back End of Line Interconnect；BEOL Interconnect）電性連接於線路結構122中對應的線路。
在本實施例中，第一晶片120的主動面120a（可以被稱為：第一主動面120a）可以面向重佈線路結構110的第一連接面110a。第一晶片120可以藉由對應的第一晶片連接件175電性連接於重佈線路結構110中對應的線路。
在一實施例中，第一晶片連接件175可以包括導電柱（conductive pillar）、焊球（solder ball）、導電凸塊（conductive bump）或具有其他形式或形狀的導電連接件。第一晶片連接件175可以經由電鍍、沉積、置球（ball placement）、迴焊（reflow）及/或其他適宜的製程來形成。
值得注意的是，在圖1B中，僅示例性地繪示一個第一晶片120，但本發明不限於此。在一未繪示的實施例中，配置於第一連接面110a上的第一晶片120的數量可以是多個。
請參照圖1B，配置第二晶片130於重佈線路結構110的第一連接面110a上，且使第二晶片130電性連接於重佈線路結構110中對應的線路。
在本實施例中，第二晶片130可以包括基材131以及線路結構132。基材131的一側具有元件區（未繪示）。元件區所位於的第二晶片130的表面可以被稱為主動面130a。線路結構132可以位於主動面130a上。在一般晶片設計中，元件區內的元件（如：第二晶片130的元件區內的元件）可以藉由對應的後段金屬內連線電性連接於線路結構132中對應的線路。
在本實施例中，第二晶片130的主動面130a（可以被稱為：第二主動面130a）可以面向重佈線路結構110的第一連接面110a。第二晶片130可以藉由對應的第二晶片連接件176電性連接於重佈線路結構110中對應的線路。
在一實施例中，第二晶片連接件176可以包括導電柱、焊球、導電凸塊或具有其他形式或形狀的導電連接件。第二晶片連接件176可以經由電鍍、沉積、置球、迴焊及/或其他適宜的製程來形成。
值得注意的是，在圖1B中，僅示例性地繪示一個第二晶片130，但本發明不限於此。在一未繪示的實施例中，配置於第一連接面110a上的第二晶片130的數量可以是多個。
請參照圖1B，在本實施例中，可以配置加強支撐件（stiffening support member）181於重佈線路結構110於第一連接面110a上。加強支撐件181可以直接地或間接地連接重佈線路結構110。舉例而言，加強支撐件181可以嵌入重佈線路結構110，而可以使加強支撐件181直接地連接重佈線路結構110。又舉例而言，加強支撐件181與重佈線路結構110之間可以具有黏著材，而可以使加強支撐件181間接地連接重佈線路結構110。
在一實施例中，加強支撐件181可以包括支撐用晶粒（supporting die）。舉例而言，可以將不合格晶粒（ugly die）、失效晶粒（failed die）或其他類似的廢晶粒（dummy die）作為支撐用晶粒。如此一來，可以降低製作上的成本。
在一實施例中，加強支撐件181可以包括硬質支撐環。舉例而言，加強支撐件181可以包括環型的金屬條。
在一實施例中，加強支撐件181可以與重佈線路結構110電性分離。也就是說，加強支撐件181可以不與重佈線路結構110電性連接。
值得注意的是，本發明並未限定第一晶片120、第二晶片130及/或加強支撐件181（若有）的配置順序。
在一實施例中，於後續的製程或結構中，加強支撐件181可以降低結構的翹曲（warpage）。
在一實施例中，被配置於重佈線路結構110上的第一晶片120及/或第二晶片130可以為已知合格晶片（known good die，KGD）。舉例而言，在將第一晶片120及/或第二晶片130配置於重佈線路結構110上之前，可以對第一晶片120及/或第二晶片130進行電性測試（如：斷短路測試（Open/Short test；O/S test））、外觀檢查（如：自動光學辨識（Auto Optical Inspection；AOI））或其他適宜的檢查或測試步驟。如此一來，可以確認被配置於重佈線路結構110上的第一晶片120及/或第二晶片130具有良好的功能，而可以提升封裝結構100（標示於圖1F或圖1G）的良率。
請參照圖1C，在本實施例中，可以形成覆蓋第一晶片120及第二晶片130的第一模封體141。在一實施例中，例如是藉由模塑製程（molding process）或其他適宜的方法將熔融的模塑化合物（molding compound）形成於重佈線路結構110的第一連接面110a上。然後，使熔融的模塑化合物冷卻並且固化，而可以形成第一模封體141。
在本實施例中，第一晶片120的背面120b（即，相對於主動面120a的表面，可以被稱為：第一背面120b）及第二晶片130的背面130b（即，相對於主動面130a的表面，可以被稱為：第二背面130b）並不會被暴露於第一模封體141之外，但本發明不限於此。在一實施例中，例如可以藉由化學機械研磨（chemical mechanical polishing；CMP）、機械研磨（mechanical grinding）、蝕刻（etching）或其他適宜的減薄製程，以暴露出第一晶片120的背面120b或第二晶片130的背面130b。
在本實施例中，第一模封體141可以更覆蓋加強支撐件181，但本發明不限於此。
請參照圖1C至圖1D，在形成第一模封體141之後，第一載板91（繪示於圖1C）上的結構可以藉由一般常用的載板轉移接合製程（carrier transfer bonding process）轉移至第二載板92（繪示於圖1D）上。並且，可以移除第一載板91，以暴露出重佈線路結構110的第二連接面110b。第二載板92可以由玻璃、晶圓基板、金屬或其他適宜的材料所製成，只要前述的材料能夠於後續的製程中，承載形成於其上的結構或構件。
在本實施例中，第二載板92上可以具有離型層95。離型層95可以為光熱轉換黏著層，但本發明不限於此。
請參照圖1E，配置第一線路板150於重佈線路結構110的第二連接面110b上，且使第一線路板150電性連接於重佈線路結構110中對應的線路。
在本實施例中，第一線路板150可以是無矽基底（Si-substrate-free）線路板。舉例而言，第一線路板150中的絕緣材153例如可以包括環氧樹脂預浸片（epoxy prepreg sheet）、聚芳醯胺預浸片（aramid prepreg sheet）或其他類似的高分子預浸片（polymer prepreg sheet）。
在一實施例中，第一線路板150可以包括多個線路層151以及位於線路層151之間的導電微孔（conductive microvia）152。在一實施例中，導電微孔152的側壁152c基本上垂直於所連接的線路層151的表面151a。
在一實施例中，第一線路板150可以是高密度連接板（high density interconnect substrate；HDI substrate）。
在本實施例中，第一線路板150可以藉由對應的第三導電連接件173電性連接於重佈線路結構110中對應的線路。
在一實施例中，第三導電連接件173可以包括導電柱、焊球、導電凸塊或具有其他形式或形狀的導電連接件。第三導電連接件173可以經由電鍍、沉積、置球、迴焊及/或其他適宜的製程來形成且配置於第一線路板150上。
在本實施例中，可以在第一線路板150與重佈線路結構110之間形成填充層159，但本發明不限於此。填充層159例如是毛細填充膠（Capillary Underfill，CUF）或其他適宜的填充材料，但本發明不限於此。
值得注意的是，在圖1E中，僅示例性地繪示一個第一線路板150，但本發明不限於此。在一未繪示的實施例中，配置於第二連接面110b上的第一線路板150的數量可以是多個。
請參照圖1E，配置第二線路板160於重佈線路結構110的第二連接面110b上，且使第二線路板160電性連接於重佈線路結構110中對應的線路。
在本實施例中，第二線路板160可以是無矽基底線路板。舉例而言，第二線路板160中的絕緣材163例如可以包括環氧樹脂預浸片、聚芳醯胺預浸片或其他類似的高分子預浸片。
在一實施例中，第二線路板160可以包括多個線路層161以及位於線路層161之間的導電微孔162。在一實施例中，導電微孔162的側壁162c基本上垂直於所連接的線路層161的表面161a。
在一實施例中，第二線路板160可以是高密度連接板。
在本實施例中，第二線路板160可以藉由對應的第四導電連接件174電性連接於重佈線路結構110中對應的線路。
在一實施例中，第四導電連接件174可以包括導電柱、焊球、導電凸塊或具有其他形式或形狀的導電連接件。第四導電連接件174可以經由電鍍、沉積、置球、迴焊及/或其他適宜的製程來形成且配置於第二線路板160上。
在本實施例中，可以在第二線路板160與重佈線路結構110之間形成填充層169，但本發明不限於此。填充層169例如是毛細填充膠或其他適宜的填充材料，但本發明不限於此。
值得注意的是，在圖1E中，僅示例性地繪示一個第二線路板160，但本發明不限於此。在一未繪示的實施例中，配置於第二連接面110b上的第二線路板160的數量可以是多個。
值得注意的是，本發明並未限定第一線路板150及第二線路板160的配置順序。
在一實施例中，在將第一線路板150及第二線路板160配置於重佈線路結構110上之前，可以對重佈線路結構110進行電性測試（如：斷短路測試）、外觀檢查（如：自動光學辨識）或其他適宜的檢查或測試步驟。如此一來，可以確認重佈線路結構110、電性連接於重佈線路結構110的第一晶片120及/電性連接於重佈線路結構110的第二晶片130具有良好的功能，而可以提升封裝結構100（標示於圖1F或圖1G）的良率。
在一實施例中，被配置於重佈線路結構110上的第一線路板150及/或第二線路板160可以為已知合格基板（known good substrate，KGS）。舉例而言，在將第一線路板150及/或第二線路板160配置於重佈線路結構110上之前，可以對第一線路板150及/或第二線路板160進行電性測試（如：斷短路測試）、外觀檢查（如：自動光學辨識）或其他適宜的檢查或測試步驟。如此一來，可以確認被配置於重佈線路結構110上的第一線路板150及/或第二線路板160具有良好的功能，而可以提升封裝結構100（標示於圖1F或圖1G）的良率。
在一實施例中，在將前述的線路板（如：第一線路板150及第二線路板160的至少其中之一）配置於重佈線路結構110上之後，可以對前述的線路板進行電性測試（如：斷短路測試）、外觀檢查（如：自動光學辨識）或其他適宜的檢查或測試步驟。在一實施例中，若在進行前述的檢查或測試步驟之後，需要對前述的線路板進行再一次地檢查或測試步驟、重工（re-work）步驟及/或報廢，則由於是將多個線路板（如：第一線路板150及第二線路板160）配置於重佈線路結構110上，因此在步驟上可以較為簡單，且/或成本也可以較為低廉。
請參照圖1F，配置第一導電端子177於第一線路板150上，且使第一導電端子177電性連接於第一線路板150中對應的線路。
請參照圖1F，配置第二導電端子178於第二線路板160上，且使第二導電端子178電性連接於第二線路板160中對應的線路。
在本實施例中，第一導電端子177或第二導電端子178可以包括焊球或具有其他形式或形狀的導電連接件。第一導電端子177或第二導電端子178可以經由置球、迴焊及/或其他適宜的製程來形成。
值得注意的是，本發明並未限定第一導電端子177及第二導電端子178的配置順序。
在一實施例中，於配置第一導電端子177或配置第二導電端子178之後，可以移除第二載板92，但本發明不限於此。
經過上述步驟後即可大致上完成本實施例的封裝結構100的製作。
請參照圖1F及圖1G，封裝結構100可以包括重佈線路結構110、第一晶片120、第二晶片130、第一線路板150、第二線路板160以及多個導電端子177、178。重佈線路結構110具有第一連接面110a及第二連接面110b。第二連接面110b相對於第一連接面110a。第一晶片120配置在重佈線路結構110的第一連接面110a上且電性連接於重佈線路結構110。第二晶片130配置在重佈線路結構110的第一連接面110a上且電性連接於重佈線路結構110。第一線路板150配置在重佈線路結構110的第二連接面110b上且電性連接於重佈線路結構110。第二線路板160配置在重佈線路結構110的第二連接面110b上且電性連接於重佈線路結構110。導電端子177、178可以包括第一導電端子177或第二導電端子178。第一導電端子177可以配置在第一線路板150上且電性連接於第一線路板150。第二導電端子178可以配置在第二線路板160上且電性連接於第二線路板160。
在一實施例中，第一晶片120或第二晶片130可以是電力管理晶片（power management integrated circuit，PMIC）、微機電系統晶片（micro-electro-mechanical-system，MEMS）、特殊應用積體電路晶片（Application-specific integrated circuit，ASIC）、動態隨機存取記憶體晶片（dynamic random access memory，DRAM）、靜態隨機存取記憶體晶片（static random access memory，SRAM）、高頻寬記憶體（High Bandwidth Memory，HBM）晶片、系統晶片（system on chip，SoC）或其他類似的高效能運算（High Performance Computing，HPC）晶片，但本發明不限於此。
在一實施例中，第一晶片120與第二晶片130之間可以是同質的（homogeneous）晶片也可以是異質的（heterogeneous）晶片，於本發明並不加以限制。
在本實施例中，重佈線路結構110的第一連接面110a及第二連接面110b基本上平行，但本發明不限於此。
在本實施例中，在垂直於第一連接面110a或第二連接面110b的投影方向D1上（如：圖1G所繪示的方向上），第一晶片120及第二晶片130不重疊。在一實施例中，第一晶片120及第二晶片130可以是以側向（side by side）方式配置。
在本實施例中，在垂直於第一連接面110a或第二連接面110b的投影方向D1上，第一線路板150及第二線路板160不重疊。在一實施例中，第一線路板150及第二線路板160可以是以側向方式配置。
在本實施例中，在垂直於第一連接面110a或第二連接面110b的投影方向D1上，第一線路板150及第二線路板160完全重疊於重佈線路結構110。
在本實施例中，封裝結構100可以更包括加強支撐件181，但本發明不限於此。
在本實施例中，加強支撐件181可以為環型。第一晶片120及第二晶片130位於環型的加強支撐件181內。
在本實施例中，在垂直於第一連接面110a或第二連接面110b的投影方向D1上，加強支撐件181可以重疊於第一線路板150或第二線路板160。舉例而言，加強支撐件181可以部分重疊於第一線路板150，且加強支撐件181可以部分重疊於第二線路板160。
在本實施例中，封裝結構100可以更包括第一模封體141，但本發明不限於此。
在本實施例中，第一模封體141可以包覆第一晶片120。在一實施例中，部分的第一模封體141可以位於第一晶片120與重佈線路結構110之間。在一實施例中，第一模封體141可以覆蓋第一晶片120的主動面120a、背面120b以及側面120c（即，連接主動面120a與背面120b的表面）。
在本實施例中，封裝結構100可以更包括第一晶片連接件175。第一晶片連接件175可以位於第一晶片120與重佈線路結構110之間。在一實施例中，第一模封體141可以更覆蓋第一晶片連接件175。
在本實施例中，第一模封體141可以包覆第二晶片130。在一實施例中，部分的第一模封體141可以位於第二晶片130與重佈線路結構110之間。在一實施例中，第一模封體141可以覆蓋第二晶片130的主動面130a、背面130b以及側面130c（即，連接主動面130a與背面130b的表面）。
在本實施例中，封裝結構100可以更包括第二晶片連接件176。第二晶片連接件176可以位於第二晶片130與重佈線路結構110之間。在一實施例中，第一模封體141可以更覆蓋第二晶片連接件176。
在本實施例中，在具有多晶片（如：第一晶片120及第二晶片130）的封裝結構100中，多個晶片之間（如：第一晶片120及第二晶片130之間）需藉由對應的線路進行電源或訊號的傳輸，且各個晶片需藉由對應的線路與外界（如：第一晶片120及第二晶片130藉由對應的導電端子177、188與連接於導電端子177、188的外部電子元件）進行電源或訊號的傳輸。因此，藉由多個線路板（如：第一線路板150及第二線路板160）配置於重佈線路結構110上的方式，對於封裝結構100的製造方法可以較為簡單且/或成本也可以較為低廉。並且，對於封裝結構100的整體線路佈局中可以降低重佈線路結構110的負載（如：可以降低重佈線路結構110的導電層層數、容易最佳化重佈線路結構110的導電層線寬、線距及/或線路佈局）。如此一來，可以提升封裝結構100的品質。
圖2A至圖2C是依照本發明的第二實施例的一種封裝結構的部分製造方法的部分剖視示意圖。第二實施例的封裝結構200的製造方法與第一實施例的封裝結構100的製造方法相似，其類似的構件以相同的標號表示，且具有類似的功能、材質或形成方式，並省略描述。舉例而言，圖2A可以是繪示接續圖1E的步驟的封裝結構的製造方法的剖面示意圖。
接續圖1E，請參照圖2A，在本實施例中，可以配置多個第一導電連接件271於第一線路板150上。第一導電連接件271可以電性連接於第一線路板150中對應的線路。
在一實施例中，第一導電連接件271可以包括預先成型（pre-formed）的導電件。舉例而言，第一導電連接件271可以包括預先成型的導電柱（pre-formed conductive pillar），但本發明不限於此。
請參照圖2A，在本實施例中，可以配置多個第二導電連接件272於第二線路板160上。第二導電連接件272可以電性連接於第二線路板160中對應的線路。
在一實施例中，第二導電連接件272可以包括預先成型的導電件。舉例而言，第二導電連接件272可以包括預先成型的導電柱，但本發明不限於此。
值得注意的是，本發明並未限定第一導電連接件271及第二導電連接件272的配置順序。
請參照圖2B，可以形成第二模封體242於重佈線路結構110的第二連接面110b上。第二模封體242可以包覆第一線路板150及第二線路板160，且第二模封體242可以暴露出第一導電連接件271及第二導電連接件272。
舉例而言，可以形成覆蓋第一線路板150及第二線路板160的第二模封材料。在一實施例中，第二模封材料例如是藉由模塑製程或其他適宜的方法將熔融的模塑化合物形成於重佈線路結構110的第二連接面110b上。然後，使熔融的模塑化合物冷卻並且固化。然後，在形成前述的第二模封材料之後，可以進行減薄製程，以移除部分的第二模封材料，以暴露出第一導電連接件271及第二導電連接件272。減薄製程例如包括化學機械研磨、機械研磨、蝕刻或其他適宜的製程，但本發明不限於此。
在本實施例中，第二模封體242至少側向覆蓋第一線路板150及第二線路板160。在一實施例中，第二模封體242至少直接接觸第一線路板150的側面及第二線路板160的側面。在一實施例中，部分的第二模封體242位於第一線路板150及第二線路板160之間。
在一實施例中，第二模封體242的模封頂面242a、第一導電連接件271的第一導電頂面271a以及第二導電連接件272的第二導電頂面272a可以基本上共面（coplanar）。
請參照圖2C，配置第一導電端子177於第一線路板150上，且配置第二導電端子178於第二線路板160上。第一導電端子177可以藉由第一導電連接件271電性連接於第一線路板150中對應的線路。第二導電端子178可以藉由第二導電連接件272電性連接於第二線路板160中對應的線路。
經過上述步驟後即可大致上完成本實施例的封裝結構200的製作。
請參照圖2C，封裝結構100可以包括重佈線路結構110、第一晶片120、第二晶片130、第一線路板150、第二線路板160、多個導電端子177、178、第一模封體141、第二模封體242、第一導電連接件271以及第二導電連接件272。第二模封體242包覆第一線路板150及第二線路板160。第一導電連接件271可以位於第一線路板150及第一導電端子177之間。第二導電連接件272可以位於第二線路板160及第二導電端子178之間。
圖3A至圖3F是依照本發明的第三實施例的一種封裝結構100的部分製造方法的部分剖視示意圖。第三實施例的封裝結構300的製造方法與第一實施例的封裝結構100或第二實施例的封裝結構200的製造方法相似，其類似的構件以相同的標號表示，且具有類似的功能、材質或形成方式，並省略描述。
請參照圖3A，形成重佈線路結構110。舉例而言，可以藉由一般常用的半導體製程，以於第二載板92上形成重佈線路結構110，且第一連接面110a面向第二載板92。
請參照圖3B，類似於圖1E所繪示的步驟，配置第一線路板150於重佈線路結構110的第二連接面110b上，且配置第二線路板160於重佈線路結構110的第二連接面110b上。
在本實施例中，可以在第一線路板150與重佈線路結構110之間形成填充層159，但本發明不限於此。
在本實施例中，可以在第二線路板160與重佈線路結構110之間形成填充層169，但本發明不限於此。
請參照圖3B，類似於圖2A所繪示的步驟，可以配置多個第一導電連接件271於第一線路板150上，且/或可以配置多個第二導電連接件272於第二線路板160上。
在一實施例中，被配置於重佈線路結構110上的第一線路板150及/或第二線路板160可以為已知合格基板。舉例而言，在將第一線路板150及/或第二線路板160配置於重佈線路結構110上之前，可以對第一線路板150及/或第二線路板160進行電性測試（如：斷短路測試）、外觀檢查（如：自動光學辨識）或其他適宜的檢查或測試步驟。如此一來，可以確認被配置於重佈線路結構110上的第一線路板150及/或第二線路板160具有良好的功能，而可以提升封裝結構300（標示於圖3F）的良率。
在一實施例中，在將前述的線路板（如：第一線路板150及第二線路板160的至少其中之一）配置於重佈線路結構110上之後，可以對前述的線路板進行電性測試（如：斷短路測試）、外觀檢查（如：自動光學辨識）或其他適宜的檢查或測試步驟。在一實施例中，若在進行前述的檢查或測試步驟之後，需要對前述的線路板進行再一次地檢查或測試步驟、重工步驟及/或報廢，則由於是將多個線路板（如：第一線路板150及第二線路板160）配置於重佈線路結構110上，因此在步驟上可以較為簡單，且/或成本也可以較為低廉。
請參照圖3C，類似於圖2B所繪示的步驟，可以形成第二模封體242於重佈線路結構110的第二連接面110b上。
請參照圖3C至圖3D，在形成第二模封體242之後，第二載板92上的結構可以藉由一般常用的載板轉移接合製程（carrier transfer bonding process）轉移至第三載板93上。並且，可以移除第二載板92，以暴露出重佈線路結構110的第一連接面110a。第三載板93可以由玻璃、晶圓基板、金屬或其他適宜的材料所製成，只要前述的材料能夠於後續的製程中，承載形成於其上的結構或構件。
在本實施例中，第三載板93上可以具有離型層94、95、96。離型層94、95、96可以為光熱轉換黏著層，但本發明不限於此。
請參照圖3D，類似於圖1B所繪示的步驟，配置第一晶片120於重佈線路結構110的第一連接面110a上，且配置第二晶片130於重佈線路結構110的第一連接面110a上。
請參照圖3D，在本實施例中，可以配置加強支撐件181於重佈線路結構110於第一連接面110a上。
在一實施例中，在將第一晶片120及第二晶片130配置於重佈線路結構110上之前，可以對重佈線路結構110進行電性測試（如：斷短路測試）、外觀檢查（如：自動光學辨識）或其他適宜的檢查或測試步驟。如此一來，可以確認重佈線路結構110、電性連接於重佈線路結構110的第一線路板150及/電性連接於重佈線路結構110的第二線路板160具有良好的功能，而可以提升封裝結構300（標示於圖3F）的良率。
在一實施例中，被配置於重佈線路結構110上的第一晶片120及/或第二晶片130可以為已知合格晶片（known good die，KGD）。舉例而言，在將第一晶片120及/或第二晶片130配置於重佈線路結構110上之前，可以對第一晶片120及/或第二晶片130進行電性測試（如：斷短路測試）、外觀檢查（如：自動光學辨識）或其他適宜的檢查或測試步驟。如此一來，可以確認被配置於重佈線路結構110上的第一晶片120及/或第二晶片130具有良好的功能，而可以提升封裝結構300（標示於圖3F）的良率。
請參照圖3E，類似於圖1C所繪示的步驟，可以形成覆蓋第一晶片120及第二晶片130的第一模封體341。第一模封體341的形成方式可以相同或相似於前述實施例的第一模封體141，故於此不加以贅述。
在本實施例中，可以進行減薄製程，以使第一模封體341暴露出第一晶片120或第二晶片130，但本發明不限於此。
請參照圖3F，在形成第一模封體341之後，可以移除第三載板93，以暴露出第二模封體242的模封頂面、第一導電連接件271的第一導電頂面271a以及第二導電連接件272的第二導電頂面272a。
請參照圖3F，類似於圖2C所繪示的步驟，配置第一導電端子177於第一線路板150上，且配置第二導電端子178於第二線路板160上。
經過上述步驟後即可大致上完成本實施例的封裝結構300的製作。
請參照圖3F，封裝結構300可以包括重佈線路結構110、第一晶片120、第二晶片130、第一線路板150、第二線路板160、多個導電端子177、178、第一模封體341、第二模封體242、第一導電連接件271以及第二導電連接件272。
就結構上而言，本實施例的封裝結構300與第二實施例的封裝結構200可能相似。
在本實施例中，第一模封體341可以包覆第一晶片120。在一實施例中，部分的第一模封體341可以位於第一晶片120與重佈線路結構110之間。在一實施例中，第一模封體341可以覆蓋第一晶片120的主動面120a以及側面120c。在一實施例中，第一模封體341可以暴露出第一晶片120的背面120b。在一實施例中，第一模封體341可以更覆蓋第一晶片連接件175。
在本實施例中，第一模封體341可以包覆第二晶片130。在一實施例中，部分的第一模封體341可以位於第二晶片130與重佈線路結構110之間。在一實施例中，第一模封體341可以覆蓋第二晶片130的主動面130a以及側面130c。在一實施例中，第一模封體341可以暴露出第二晶片130的背面130b。在一實施例中，第一模封體341可以更覆蓋第二晶片連接件176。
圖4A至圖4B是依照本發明的第四實施例的一種封裝結構的部分製造方法的部分剖視示意圖。第四實施例的封裝結構400的製造方法與第三實施例的封裝結構300的製造方法相似，其類似的構件以相同的標號表示，且具有類似的功能、材質或形成方式，並省略描述。舉例而言，圖4A可以是繪示接續圖3D的步驟的封裝結構100的製造方法的剖面示意圖。
接續圖3D，請參照圖4A，在本實施例中，可以配置殼體482於重佈線路結構110的第一連接面110a上。殼體482可以直接地或間接地連接重佈線路結構110。舉例而言，殼體482可以嵌入重佈線路結構110，而可以使殼體482直接地連接重佈線路結構110。又舉例而言，殼體482與重佈線路結構110之間可以具有黏著材，而可以使殼體482間接地連接重佈線路結構110。
請參照圖4B，類似於圖3F所繪示的步驟，可以在移除第三載板93之後，配置第一導電端子177於第一線路板150上，且配置第二導電端子178於第二線路板160上。
經過上述步驟後即可大致上完成本實施例的封裝結構400的製作。
請參照圖4B，封裝結構400可以包括重佈線路結構110、第一晶片120、第二晶片130、第一線路板150、第二線路板160、多個導電端子177、178、第二模封體242、第一導電連接件271、第二導電連接件272以及殼體482。殼體482可以配置於重佈線路結構110的第一連接面110a上。第一晶片120及第二晶片130可以位於殼體482的容置空間482c內。
在一實施例中，殼體482可以包括硬質的材質。如此一來，可以藉由殼體482保護位於其內的構件（如：第一晶片120、第二晶片130及/或加強支撐件181）。
在一實施例中，殼體482可以包括導電材質。在一可能的實施例中，導電的殼體482可以作為電磁干擾屏蔽（electromagnetic interference shielding；EMI shielding），而可以降低電磁干擾，但本發明不限於此。在一可能的實施例中，殼體482的導電部分可以作為天線，但本發明不限於此。
綜上所述，在本發明具有多晶片（如：第一晶片及第二晶片）的封裝結構中，多個晶片之間（如：第一晶片及第二晶片之間）需藉由對應的線路進行電源或訊號的傳輸，且各個晶片需藉由對應的線路與外界（如：第一晶片及第二晶片藉由對應的導電端子與連接於導電端子的外部電子元件）進行電源或訊號的傳輸。因此，藉由多個線路板（如：第一線路板及第二線路板）配置於重佈線路結構上的方式，對於封裝結構的製造方法可以較為簡單且/或成本也可以較為低廉。並且，對於封裝結構的整體線路佈局中可以降低重佈線路結構的負載（如：可以降低重佈線路結構的導電層層數、容易最佳化重佈線路結構的導電層線寬、線距及/或線路佈局）。如此一來，可以提升封裝結構的品質。
100、200、300、400:封裝結構 91:第一載板 94:離型層 92:第二載板 95:離型層 93:第三載板 96:離型層 110:重佈線路結構 110a:第一連接面 110b:第二連接面 120:第一晶片 121:基材 122:線路結構 120a:主動面 120b:背面 120c:側面 130:第二晶片 131:基材 132:線路結構 130a:主動面 130b:背面 130c:側面 141、341:第一模封體 242:第二模封體 242a:模封頂面 150:第一線路板 151:線路層 151a:表面 152:導電微孔 152c:側壁 153:絕緣材 159:填充層 160:第二線路板 161:線路層 161a:表面 162:導電微孔 162c:側壁 163:絕緣材 169:填充層 271:第一導電連接件 271a:第一導電頂面 272:第二導電連接件 272a:第二導電頂面 173:第三導電連接件 174:第四導電連接件 175:第一晶片連接件 176:第二晶片連接件 177:第一導電端子 178:第二導電端子 181:加強支撐件 482:殼體 482c:容置空間 D1:投影方向
圖1A至圖1F是依照本發明的第一實施例的一種封裝結構的部分製造方法的部分剖視示意圖。 圖1G是依照本發明的第一實施例的一種封裝結構的部分上視示意圖。 圖2A至圖2C是依照本發明的第二實施例的一種封裝結構的部分製造方法的部分剖視示意圖。 圖3A至圖3F是依照本發明的第三實施例的一種封裝結構的部分製造方法的部分剖視示意圖。 圖4A至圖4B是依照本發明的第四實施例的一種封裝結構的部分製造方法的部分剖視示意圖。
100:封裝結構
110:重佈線路結構
110a:第一連接面
110b:第二連接面
120:第一晶片
120a:主動面
120b:背面
120c:側面
130:第二晶片
130a:主動面
130b:背面
130c:側面
141:第一模封體
150:第一線路板
151:線路層
152:導電微孔
153:絕緣材
159:填充層
160:第二線路板
161:線路層
162:導電微孔
163:絕緣材
169:填充層
173:第三導電連接件
174:第四導電連接件
175:第一晶片連接件
176:第二晶片連接件
177:第一導電端子
178:第二導電端子
181:加強支撐件
D1:投影方向

Claims (9)

  1. 一種封裝結構，包括：重佈線路結構，具有第一連接面及相對於所述第一連接面的第二連接面；第一晶片，配置在所述第一連接面上且電性連接於所述重佈線路結構；第二晶片，配置在所述第一連接面上且電性連接於所述重佈線路結構；第一線路板，配置在所述第二連接面上且電性連接於所述重佈線路結構；第二線路板，配置在所述第二連接面上且電性連接於所述重佈線路結構；以及多個導電端子，配置在所述第一線路板或所述第二線路板上，且電性連接於所述第一線路板或所述第二線路板，其中所述第一線路板及所述第二線路板為無矽基底線路板。
  2. 如請求項1所述的封裝結構，其中在垂直於所述第一連接面或所述第二連接面的投影方向上，所述第一晶片及所述第二晶片不重疊，且所述第一線路板及所述第二線路板不重疊。
  3. 如請求項2所述的封裝結構，其中在所述投影方向上，所述第一線路板及所述第二線路板完全重疊於所述重佈線路結構。
  4. 如請求項1所述的封裝結構，更包括： 加強支撐件，配置所述第一連接面上且連接所述重佈線路結構。
  5. 如請求項4所述的封裝結構，其中所述加強支撐件為環型，且所述第一晶片及所述第二晶片位於環型的所述加強支撐件內。
  6. 如請求項4所述的封裝結構，其中在垂直於所述第一連接面或所述第二連接面的投影方向上，所述加強支撐件重疊於所述第一線路板或所述第二線路板。
  7. 如請求項1所述的封裝結構，更包括：模封體，包覆所述第一晶片及所述第二晶片或包覆所述第一線路板及所述第二線路板。
  8. 如請求項7所述的封裝結構，其中所述模封體包覆所述第一線路板及所述第二線路板，且封裝結構更包括：多個導電連接件，配置在所述第一線路板或所述第二線路板上，且所述多個導電端子藉由對應的所述多個導電連接件電性連接於所述第一線路板或所述第二線路板。
  9. 一種封裝結構的製造方法，包括：形成重佈線路結構，其具有第一連接面及相對於所述第一連接面的第二連接面；配置第一晶片於所述第一連接面上，且使所述第一晶片電性連接於所述重佈線路結構；配置第二晶片於所述第一連接面上，且使所述第二晶片電性 連接於所述重佈線路結構；配置第一線路板於所述第二連接面上，且使所述第一線路板電性連接於所述重佈線路結構；配置第二線路板於所述第二連接面上，且使所述第二線路板電性連接於所述重佈線路結構；以及配置多個導電端子於所述第一線路板或所述第二線路板上，且使所述多個導電端子電性連接於所述第一線路板或所述第二線路板，其中所述第一線路板及所述第二線路板為無矽基底線路板。
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