CN113130436A - 半导体封装结构及其制造方法 - Google Patents

半导体封装结构及其制造方法 Download PDF

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CN113130436A
CN113130436A CN202011109211.0A CN202011109211A CN113130436A CN 113130436 A CN113130436 A CN 113130436A CN 202011109211 A CN202011109211 A CN 202011109211A CN 113130436 A CN113130436 A CN 113130436A
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conductive
circuit substrate
semiconductor package
package structure
chips
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CN113130436B (zh
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林南君
徐宏欣
张简上煜
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Powertech Technology Inc
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Powertech Technology Inc
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Abstract

本发明提供一种半导体封装结构，其包括线路基板、至少二芯片、密封体以及重布线路层。线路基板具有第一表面以及相对于第一表面的第二表面。至少二芯片配置于第一表面上，其中至少二芯片中的每一者具有面向线路基板的有源面并包括配置于有源面上的多个第一导电连接件以及多个第二导电连接件。多个第一导电连接件的间距小于多个第二导电连接件的间距。密封体包封至少二芯片。重布线路层位于第二表面上。多个第一导电连接件通过线路基板与重布线路层电性连接。多个第二导电连接件与线路基板电性连接。另提供一种半导体封装结构的制造方法。

Description

半导体封装结构及其制造方法
技术领域
本发明涉及一种封装结构及其制造方法，尤其涉及一种半导体封装结构及其制造方法。
背景技术
为了使电子产品设计实现轻、薄、短且小，半导体封装技术正持续进步，以尝试开发出体积较小、重量较轻、整合度较高且更具市场竞争力的产品。如何在降低半导体封装结构的制造成本的同时还能够提升半导体封装结构的可靠度实为本领域的技术人员的一大挑战。
发明内容
本发明是针对一种半导体封装结构及其制造方法，其可以在降低半导体封装结构的制造成本的同时还能够提升半导体封装结构的可靠度。
根据本发明的实施例，一种半导体封装结构，其包括线路基板、至少二芯片、密封体以及重布线路层。线路基板具有第一表面以及相对于第一表面的第二表面。至少二芯片配置于第一表面上，其中至少二芯片中的每一者具有面向线路基板的有源面并包括配置于有源面上的多个第一导电连接件以及多个第二导电连接件。多个第一导电连接件的间距小于多个第二导电连接件的间距。密封体包封至少二芯片。重布线路层位于第二表面上。多个第一导电连接件通过线路基板与重布线路层电性连接。多个第二导电连接件与线路基板电性连接。
根据本发明的实施例，一种半导体封装结构的制造方法，其至少包括以下步骤。提供线路基板。线路基板具有第一表面以及相对于第一表面的第二表面。配置至少二芯片于第一表面上。至少二芯片中的每一者具有面向线路基板的有源面并包括配置于有源面上的多个第一导电连接件以及多个第二导电连接件。多个第一导电连接件相邻两者之间的间距小于多个第二导电连接件相邻两者之间的间距。形成密封体包封至少二芯片。形成重布线路层于线路基板的第二表面上。多个第一导电连接件通过线路基板与重布线路层电性连接。多个第二导电连接件与线路基板电性连接。
基于上述，由于多个第一导电连接件的间距小于多个第二导电连接件的间距，且第一导电连接件通过线路基板与重布线路层电性连接，第二导电连接件与线路基板电性连接，因此，在本发明的半导体封装结构中具有不同间距的第一导电连接件与第二导电连接件可以有效地利用线路基板来达成至少两芯片之间不同的电性连接需求，进而可以减少重布线路层所需形成的层数，降低半导体封装结构的制造成本。此外，上述配置方式也可以在降低半导体封装结构的制造成本的同时提升半导体封装结构的可靠度(如改善信号完整性/电源完整性)。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1A至图1E是依据本发明一实施例的半导体封装结构的部分制造方法的部分剖面示意图。
具体实施方式
现将详细地参考本发明的示范性实施例，示范性实施例的实例说明于附图中。只要有可能，相同元件符号在附图和描述中用来表示相同或相似部分。
本文所使用的方向用语(例如，上、下、右、左、前、后、顶部、底部)仅作为参看所绘附图使用且不意欲暗示绝对定向。
除非另有明确说明，否则本文所述任何方法绝不意欲被解释为要求按特定顺序执行其步骤。
参照本实施例的附图以更全面地阐述本发明。然而，本发明亦可以各种不同的形式体现，而不应限于本文中所述的实施例。附图中的层或区域的厚度、尺寸或大小会为了清楚起见而放大。相同或相似的参考号码表示相同或相似的元件，以下段落将不再一一赘述。
图1A至图1E是依据本发明一实施例的半导体封装结构的部分制造方法的部分剖面示意图。
请参照图1A，本实施例中，半导体封装结构100的制造过程可以包括以下步骤。首先，提供线路基板110。线路基板110具有第一表面110a以及相对于第一表面110a的第二表面110b，且线路基板110可以包括导电线路112。
在一些实施例中，线路基板110可以为印刷电路板(Printed Circuit Board,PCB)、有机基板(organic substrate)或高密度内连线基板。然而，本发明不限制线路基板110的种类，只要线路基板110中具有适宜的导电线路112可以提供后续工艺中所需的电性连接，皆属于本发明的保护范围。
请继续参照图1A，线路基板110可以包括中间区CR以及外围区PR。在本实施例中，导电线路112可以包括位于中间区CR的多个叠孔结构1121。叠孔结构1121可以连接线路基板110的第一表面110a与第二表面110b。
在一实施例中，叠孔结构1121可以包括多个导通孔V，其中导通孔V可以于第一表面110a的法向量n上相互堆叠。在一实施例中，导通孔V于第一表面110a上的正投影可以完全重叠，因此，叠孔结构1121可以作为线路基板110中提供较短电连接路径的垂直电连接结构。
请参照图1B，于线路基板110的第一表面110a上配置至少二芯片，其中至少二芯片可以包括第一芯片120以及第二芯片130。在一实施例中，第一芯片120与第二芯片130可以具有不同功能。举例而言，第一芯片120可以是系统单芯片(system on chip,SoC)，而第二芯片130动态随机存取存储器(DRAM)，但本发明不限于此，第一芯片120与第二芯片130可以是其他适宜的半导体芯片。在一实施例中，第一芯片120与第二芯片130的尺寸可以不同。
在本实施例中，至少二芯片中的每一者具有有源面以及相对于有源面的背面，其中有源面面向线路基板110的第一表面110a。举例而言，第一芯片120具有有源面120a以及相对于有源面120a的背面120b，而第二芯片130具有有源面130a以及相对于有源面130a的背面130b，且第一芯片120以及第二芯片130例如是以覆晶(flip-chip)方式配置于线路基板110的第一表面110a上。
至少二芯片中的每一者可以包括配置于所述至少二芯片中的每一者的有源面上的多个第一导电连接件142以及多个第二导电连接件144，且多个第一导电连接件142以及多个第二导电连接件144与线路基板110电性连接。举例而言，第一芯片120的有源面120a上可以配置有多个第一导电连接件1421以及多个第二导电连接件1441；而第二芯片130的有源面130a上可以配置有多个第一导电连接件1422以及多个第二导电连接件1442。
在本实施例中，多个第一导电连接件142相邻两者之间的间距P1小于多个第二导电连接件144相邻两者之间的间距P2。在此，间距P1为两相邻的第一导电连接件142的中心点之间的距离；而间距P2为两相邻的第二导电连接件144的中心点之间的距离。多个第一导电连接件142的间距P1可以称为微间距(fine pitch)，而多个第二导电连接件144的间距P2可以称为粗间距(coarse pitch)。
由于多个第一导电连接件142相邻两者之间的间距P1小于多个第二导电连接件144相邻两者之间的间距P2，因此，具有微间距的多个第一导电连接件142可以作为信号输入/输出接点，而具有粗间距的多个第二导电连接件144可以作为电源/接地接点。
请继续参照图1B，在本实施例中，中间区CR可以是至少两芯片中的一者靠近另一者的区域，外围区PR可以是至少两芯片中的一者远离另一者的区域，如图1B所示。多个第一导电连接件142位于中间区CR，多个第二导电连接件144位于外围区PR。至少两芯片的任一者中的多个第一导电连接件142可以是相较于多个第二导电连接件144靠近至少两芯片的另一者。举例而言，第一芯片120中的多个第一导电连接件1421相较于多个第二导电连接件1441靠近第二芯片130，而第二芯片130中的多个第一导电连接件1422相较于多个第二导电连接件1442靠近第一芯片120。
第一导电连接件142可以与叠孔结构1121电性连接，而第二导电连接件144可以与线路基板110中多个叠孔结构1121以外的导电线路112电性连接。在一实施例中，每一第一导电连接件142可以与对应的叠孔结构1121电性连接。举例而言，第一导电连接件142与叠孔结构1121可以是以一对一方式配置，但本发明不限于此。在一实施例中，第一导电连接件142可以与对应的叠孔结构1121直接接触。
在本实施例中，第一导电连接件142与第二导电连接件144例如是由接垫及导电凸块所组成，但本发明不限于此，可以视实际需求而定。
请参照图1C，将至少二芯片配置于线路基板110上后，于线路基板110的第一表面110a上形成密封体150，以包封至少二芯片。在本实施例中，密封体150可以完全覆盖至少二芯片。举例而言，密封体150可以覆盖第一芯片120的背面120b与第二芯片130的背面130b。密封体150可以是通过模塑工艺(molding process)所形成的模塑化合物(moldingcompound)。在一实施例中，密封体150例如可以由环氧树脂或其他适宜的树脂等绝缘材料所形成的，但本发明不限于此。
在未示出的实施例中，还可以进一步对密封体150进行研磨工艺(grindingprocess)，直到露出第一芯片120的背面120b以及第二芯片130的背面130b，使第一芯片120的背面120b与第二芯片130的背面130b基本上共面(coplanar)。
请参照图1D，形成密封体150之后，将图1C所示出的结构上下翻面(flippedupside down)。接着，于线路基板110的第二表面110b上形成重布线路层160，且第一导电连接件142通过线路基板110与重布线路层160电性连接。
由于多个第一导电连接件142的间距P1小于多个第二导电连接件144的间距P2，且第一导电连接件142通过线路基板110与重布线路层160电性连接，第二导电连接件144与线路基板110电性连接，因此，在本发明的半导体封装结构100中具有不同间距的第一导电连接件142与第二导电连接件144可以有效地利用线路基板110来达成至少两芯片之间不同的电性连接需求(信号输入/输出及电源/接地)。举例而言，具有微间距的多个第一导电连接件142通过线路基板110与重布线路层160电性连接以传递信号，而具有粗间距的多个第二导电连接件144与线路基板110电性连接以连接电源/接地。如此，可以减少重布线路层160所需形成的层数，进而可以降低半导体封装结构100的制造成本。此外，上述配置方式也可以进一步提升半导体封装结构100的可靠度。例如，半导体封装结构100具有更好的信号完整性/电源完整性(signal integrity/power integrity,SI/PI)性能。
在一实施例中，重布线路层160可以包括多个介电层以及部分嵌入于介电层中的多个图案化导电层。介电层可以包括邻近线路基板110的底介电层161，而图案化导电层可以包括邻近线路基板110的多个导电图案162。
重布线路层160的形成方法例如是于线路基板110的第二表面110b上形成具有多个开口的底介电层161，其中多个开口暴露出线路基板110中部分导电线路112。接着，于多个开口中形成导电图案162，使导电图案162电性连接至前述部分导电线路112。然后，可以重复上述步骤多次，以形成由交替堆叠的介电层与图案化导电层所组成的重布线路层160。
在一实施例中，多个导电图案162可以分别对应于多个叠孔结构1121，其中多个导电图案162可以形成直接电连接区域E。多个开口例如是暴露出线路基板110中部分导电线路112的多个叠孔结构1121，以使第一导电连接件142可以通过线路基板110中的多个叠孔结构1121与重布线路层160中的导电图案162电性连接，以用于传递第一芯片120与第二芯片130之间的信号。举例而言，第一芯片120与第二芯片130之间的信号传递路径例如是依序经由第一芯片120上的第一导电连接件1421、叠孔结构1121、导电图案162、叠孔结构1121以及第二芯片130上的第一导电连接件1422所传递。在一实施例中，每一多个开口对应多个叠孔结构1121中的其中之一。
由于多个叠孔结构1121可以是垂直电连接结构，因此，当第一芯片120与第二芯片130上的第一导电连接件1421与第一导电连接件1422通过线路基板110中的多个叠孔结构1121以及重布线路层160来传递信号时，传输路径/距离可以显着地缩短，进而半导体封装结构100可以具有更好的信号完整性。
在一实施例中，重布线路层160的细线距(line-and-space,L/S)可以是小于5微米/5微米。在一实施例中，重布线路层160的细线距例如是小于2微米/2微米，因此可以具有较佳的信号传输能力。
此外，形成底介电层161于线路基板110上可以为线路基板110提供缓冲，进而可以进一步提升半导体封装结构100的可靠度。
应说明的是，附图中的线路布局(layout)仅为示意用，因此，于附图中，导电线路112以及重布线路层160中部分未连接的线路实际上也可以视线路设计需求经由导通孔或其他方向的导电件进行电性连接。
请参照图1E，形成重布线路层160之后，于重布线路层160上形成多个导电端子170，而导电端子170与重布线路层160电性连接。在一实施例中，重布线路层160位于至少二芯片与导电端子170之间。因此，至少二芯片可以通过线路基板110及重布线路层160与导电端子170电性连接。举例而言，多个第二导电连接件144可以通过线路基板110以及重布线路层160与导电端子170电性连接。
在一实施例中，多个导电端子170相邻两者之间的间距P3可以大于多个第一导电连接件142相邻两者之间的间距P1。在此，间距P3为两相邻的导电端子170的中心点之间的距离。
导电端子170可以通过植球工艺(ball placement process)以和/或回焊工艺(reflow process)来形成。导电端子170可以是焊球等的导电凸块。然而，本发明不限于此。在一些替代的实施例中，基于设计需求，导电端子170可以具有其他可能的形式以及形状。
经过上述工艺后即可大致上完成本实施例的半导体封装结构100的制作。半导体封装结构100包括线路基板110、至少二芯片(第一芯片120以及第二芯片130)、密封体150以及重布线路层160。线路基板110具有第一表面110a以及相对于第一表面110a的第二表面110b。至少二芯片配置于第一表面110a上，其中至少二芯片中的每一者具有面向线路基板110的有源面并包括配置于有源面上的多个第一导电连接件142以及多个第二导电连接件144。多个第一导电连接件142的间距小于多个第二导电连接件144的间距。密封体150包封至少二芯片。重布线路层160位于第二表面110b上。多个第一导电连接件142通过线路基板110与重布线路层160电性连接。多个第二导电连接件144与线路基板110电性连接。
综上所述，由于多个第一导电连接件的间距小于多个第二导电连接件的间距，且第一导电连接件通过线路基板与重布线路层电性连接，第二导电连接件与线路基板电性连接，因此，在本发明的半导体封装结构中具有不同间距的第一导电连接件与第二导电连接件可以有效地利用线路基板来达成至少两芯片之间不同的电性连接需求，进而可以减少重布线路层所需形成的层数，降低半导体封装结构的制造成本。此外，上述配置方式也可以在降低半导体封装结构的制造成本的同时提升半导体封装结构的可靠度(如改善信号完整性/电源完整性)。再者，第一芯片与第二芯片上的第一导电连接件通过线路基板中的多个叠孔结构以及重布线路层来传递信号时，传输路径/距离可以显着地缩短，进而半导体封装结构可以具有更好的信号完整性。此外，本发明的半导体封装结构中由于线路基板不为暂时性基板，因此，于半导体封装结构的制造过程中可以省去使用暂时载板的成本且不用额外进行移除暂时载板的工艺，进而可以进一步降低半导体封装结构的制造成本。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (10)

1.一种半导体封装结构，其特征在于，包括：
线路基板，具有第一表面以及相对于所述第一表面的第二表面；
至少二芯片，配置于所述第一表面上，其中所述至少二芯片中的每一者具有面向所述线路基板的有源面并包括：
多个第一导电连接件以及多个第二导电连接件，配置于所述有源面上；以及
所述多个第一导电连接件的间距小于所述多个第二导电连接件的间距；
密封体，包封所述至少二芯片；以及
重布线路层，位于所述第二表面上，其中所述多个第一导电连接件通过所述线路基板与所述重布线路层电性连接，所述多个第二导电连接件与所述线路基板电性连接。
2.根据权利要求1所述的半导体封装结构，其特征在于，所述线路基板包括中间区与外围区，且所述多个第一导电连接件位于所述中间区，所述多个第二导电连接件位于所述外围区。
3.根据权利要求2所述的半导体封装结构，其特征在于，所述线路基板包括多个叠孔结构，且所述多个第一导电连接件通过所述多个叠孔结构与所述重布线路层电性连接。
4.根据权利要求3所述的半导体封装结构，其特征在于，所述多个叠孔结构位于所述中间区，且所述多个第一导电连接件与所述多个叠孔结构直接接触。
5.根据权利要求3所述的半导体封装结构，其特征在于，所述多个第二导电连接件与所述线路基板中所述多个叠孔结构以外的导电线路与电性连接。
6.根据权利要求3所述的半导体封装结构，其特征在于，所述多个叠孔结构包括多个导通孔，所述多个导通孔于所述第一表面的法向量上相互堆叠。
7.根据权利要求3所述的半导体封装结构，其特征在于，所述多个导通孔于所述第一表面上的正投影完全重叠。
8.根据权利要求3所述的半导体封装结构，其特征在于，所述重布线路层包括邻近所述线路基板的多个导电图案，且所述多个导电图案对应于所述多个叠孔结构。
9.一种半导体封装结构的制造方法，其特征在于，包括：
提供线路基板，具有第一表面以及相对于所述第一表面的第二表面；
配置至少二芯片于所述第一表面上，其中所述至少二芯片中的每一者具有面向所述线路基板的有源面并包括：
多个第一导电连接件以及多个第二导电连接件，配置于所述有源面上；以及
所述多个第一导电连接件相邻两者之间的间距小于所述多个第二导电连接件相邻两者之间的间距；
形成密封体包封所述至少二芯片；以及
形成重布线路层于所述线路基板的所述第二表面上，其中所述多个第一导电连接件通过所述线路基板与所述重布线路层电性连接，所述多个第二导电连接件与所述线路基板电性连接。
10.根据权利要求9所述的半导体封装结构的制造方法，其特征在于，形成所述重布线路层包括：
形成底介电层于所述第二表面上，且所述底介电层具有多个开口，暴露出所述线路基板中部分导电线路；以及
形成导电图案于所述开口中，使所述导电图案电性连接至所述部分导电线路，其中所述部分导电线路包括多个叠孔结构，且所述多个开口暴露出所述多个叠孔结构。
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