TWI728924B - 封裝結構及其製造方法 - Google Patents

封裝結構及其製造方法 Download PDF

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TWI728924B
TWI728924B TW109135315A TW109135315A TWI728924B TW I728924 B TWI728924 B TW I728924B TW 109135315 A TW109135315 A TW 109135315A TW 109135315 A TW109135315 A TW 109135315A TW I728924 B TWI728924 B TW I728924B
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circuit board
circuit
package
connection surface
redistributed
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TW109135315A
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English (en)
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TW202127601A (zh
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張簡上煜
林南君
徐宏欣
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力成科技股份有限公司
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Priority to US16/952,044 priority Critical patent/US11545423B2/en
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Publication of TWI728924B publication Critical patent/TWI728924B/zh
Publication of TW202127601A publication Critical patent/TW202127601A/zh

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Abstract

一種封裝結構，其包括重佈線路結構、第一線路板、第二線路板、第一絕緣體、多個導電端子以及封裝件。重佈線路結構具有第一連接面及相對於第一連接面的第二連接面。第一線路板及第二線路板配置在第一連接面上且電性連接於重佈線路結構。第一絕緣體位於第一連接面上且包覆第一線路板及第二線路板。導電端子配置在第一線路板或第二線路板上且電性連接於第一線路板或第二線路板。封裝件配置在第二連接面上且電性連接於重佈線路結構。封裝件包括至少一晶片、模封體、線路層以及多個導電封裝端子。一種封裝結構的製造方法亦被提出。

Description

封裝結構及其製造方法
本發明是有關於一種封裝結構及其製造方法，且特別是有關於一種具有多個晶片及多個線路板的封裝結構及其製造方法。
近年來，電子設備對於人類的生活越來越重要。為了加速各種功能的整合，可以將多個主動晶片整合在一個封裝結構。因此，如何使具有多個主動晶片的封裝結構的製造良率或品質可以提升，或可以使多個主動晶片的封裝結構的製造成本可以降低，實已成目前亟欲解決的課題。
本發明提供一種封裝結構，其具有較佳的品質。
本發明提供一種封裝結構的製造方法，其具有較佳的良率或較低的成本。
本發明的封裝結構包括重佈線路結構、第一線路板、第二線路板、第一絕緣體、多個導電端子以及封裝件。重佈線路結構具有第一連接面及相對於第一連接面的第二連接面。第一線路板配置在第一連接面上且電性連接於重佈線路結構。第二線路板配置在第一連接面上且電性連接於重佈線路結構。第一絕緣體位於第一連接面上且包覆第一線路板及第二線路板。多個導電端子配置在第一線路板或第二線路板上，且多個導電端子電性連接於第一線路板或第二線路板。封裝件配置在第二連接面上且電性連接於重佈線路結構。封裝件包括至少一晶片、模封體、線路層以及多個導電封裝端子。模封體包覆晶片。線路層位於模封體上且電性連接於晶片。多個導電封裝端子位於線路層上且電性連接於重佈線路結構。
本發明的封裝結構的製造方法包括以下步驟：形成重佈線路結構，其具有第一連接面及相對於第一連接面的第二連接面；配置第一線路板於第一連接面上，且使第一線路板電性連接於重佈線路結構；配置第二線路板於第一連接面上，且使第二線路板電性連接於重佈線路結構；形成第一絕緣體於第一連接面上，且第一絕緣體包覆第一線路板及第二線路板；形成多個導電端子於第一線路板或第二線路板上，且多個導電端子電性連接於第一線路板或第二線路板；以及配置封裝件於第二連接面上，封裝件電性連接於重佈線路結構。封裝件包括至少一晶片、模封體、線路層以及多個導電封裝端子。模封體包覆晶片。線路層位於模封體上且電性連接於晶片。多個導電封裝端子位於線路層上且電性連接於重佈線路結構。
基於上述，在具有多晶片的封裝結構中，藉由多個線路板配置於重佈線路結構上的方式，對於封裝結構的製造方法可以較為簡單且/或成本也可以較為低廉。並且，對於封裝結構的整體線路佈局中可以降低重佈線路結構的負載，而可以提升封裝結構的品質。
本文所使用之方向用語（例如，上、下、右、左、前、後、頂部、底部）僅作為參看所繪圖式使用且不意欲暗示絕對定向。另外，為求清楚表示，於圖式中可能省略繪示了部分的膜層或構件。
除非另有明確說明，否則本文所述任何方法絕不意欲被解釋為要求按特定順序執行其步驟。
參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施例。圖式中的層或區域的厚度、尺寸或大小會為了清楚起見而放大。相同或相似之參考號碼表示相同或相似之元件，以下段落將不再一一贅述。
圖1A至圖1F是依照本發明的第一實施例的一種封裝結構的部分製造方法的部分剖視示意圖。圖1G是依照本發明的第一實施例的一種封裝結構的部分上視示意圖。
請參照圖1A，形成重佈線路結構130。舉例而言，可以藉由一般常用的半導體製程，以於載板91上形成重佈線路結構130。載板91可以由玻璃、晶圓基板、金屬或其他適宜的材料所製成，只要前述的材料能夠於後續的製程中，承載形成於其上的結構或構件。
在本實施例中，重佈線路結構130可以具有第一連接面130a及第二連接面130b。第二連接面130b相對於第一連接面130a，且第二連接面130b面向載板91。
在本實施例中，載板91上可以具有離型層92。離型層92可以為光熱轉換（light to heat conversion，LTHC）黏著層，但本發明不限於此。
請參照圖1B，配置第一線路板110於重佈線路結構130上，且使第一線路板110電性連接於重佈線路結構130中對應的線路。第一線路板110具有第一頂面110a、第一底面110b以及第一側面110c。第一底面110b相對於第一頂面110a。第一側面110c連接於第一頂面110a與第一底面110b。第一線路板110可以是以其第一底面110b面向重佈線路結構130的第一連接面130a的方式配置於重佈線路結構130的第一連接面130a上。
在本實施例中，第一線路板110無矽基底（Si-substrate-free）線路板。舉例而言，第一線路板110中的絕緣材113例如可以包括環氧樹脂預浸片（epoxy prepreg sheet）、聚芳醯胺預浸片（aramid prepreg sheet）或其他類似的高分子預浸片（polymer prepreg sheet）。
在一實施例中，第一線路板110可以包括多個線路層111以及位於線路層111之間的導電微孔（conductive microvia）112。在一實施例中，導電微孔112的側壁112c基本上垂直於所連接的線路層111的表面111a。
在一實施例中，第一線路板110可以是高密度連接板（high density interconnect substrate；HDI substrate）。
在本實施例中，第一線路板110可以藉由對應的第一導電連接件161電性連接於重佈線路結構130中對應的線路。
在一實施例中，第一導電連接件161可以包括導電柱、焊球、導電凸塊或具有其他形式或形狀的導電連接件。第一導電連接件161可以經由電鍍、沉積、置球、迴焊及/或其他適宜的製程來形成且配置於第一線路板110上。
在一未繪示的實施例中，可以在第一線路板110與重佈線路結構130之間形成填充層，但本發明不限於此。填充層例如是毛細填充膠（Capillary Underfill，CUF）或其他適宜的填充材料，但本發明不限於此。
值得注意的是，在圖1B中，僅示例性地繪示二個第一線路板110，但本發明對於配置於第一連接面130a上的第一線路板110的數量並不加以限制。
請參照圖1B，配置第二線路板120於重佈線路結構130上，且使第二線路板120電性連接於重佈線路結構130中對應的線路。第二線路板120具有第二頂面120a、第二底面120b以及第二側面120c。第二底面120b相對於第二頂面120a。第二側面120c連接於第二頂面120a與第二底面120b。第二線路板120可以是以其第二底面120b面向重佈線路結構130的第一連接面130a的方式配置於重佈線路結構130的第一連接面130a上。
在本實施例中，第二線路板120無矽基底線路板。舉例而言，第二線路板120中的絕緣材123例如可以包括環氧樹脂預浸片、聚芳醯胺預浸片或其他類似的高分子預浸片。
在一實施例中，第二線路板120可以包括多個線路層121以及位於線路層121之間的導電微孔122。在一實施例中，導電微孔122的側壁122c基本上垂直於所連接的線路層121的表面121a。
在一實施例中，第二線路板120可以是高密度連接板。
在本實施例中，第二線路板120可以藉由對應的第二導電連接件162電性連接於重佈線路結構130中對應的線路。
在一實施例中，第二導電連接件162可以包括導電柱、焊球、導電凸塊或具有其他形式或形狀的導電連接件。第二導電連接件162可以經由電鍍、沉積、置球、迴焊及/或其他適宜的製程來形成且配置於第二線路板120上。
在一未繪示的實施例中，可以在第二線路板120與重佈線路結構130之間形成填充層，但本發明不限於此。填充層例如是毛細填充膠或其他適宜的填充材料，但本發明不限於此。
值得注意的是，在圖1B中，僅示例性地繪示二個第二線路板120，但本發明對於配置於第一連接面130a上的第二線路板120的數量並不加以限制。
值得注意的是，本發明並未限定第一線路板110及第二線路板120的配置順序。
在一實施例中，在將第一線路板110及第二線路板120配置於重佈線路結構130上之前，可以對重佈線路結構130進行電性測試（如：斷短路測試（Open/Short test；O/S test））、外觀檢查（如：自動光學辨識（Auto Optical Inspection；AOI））或其他適宜的檢查或測試步驟。如此一來，可以確認重佈線路結構130具有良好的功能，而可以提升封裝結構100（標示於圖1F或圖1G）的良率。
在一實施例中，被配置於重佈線路結構130上的第一線路板110及/或第二線路板120可以為已知合格基板（known good substrate，KGS）。舉例而言，在將第一線路板110及/或第二線路板120配置於重佈線路結構130上之前，可以對第一線路板110及/或第二線路板120進行電性測試（如：斷短路測試）、外觀檢查（如：自動光學辨識）或其他適宜的檢查或測試步驟。如此一來，可以確認被配置於重佈線路結構130上的第一線路板110及/或第二線路板120具有良好的功能，而可以提升封裝結構100（標示於圖1F或圖1G）的良率。
在一實施例中，在將前述的線路板（如：第一線路板110及第二線路板120的至少其中之一）配置於重佈線路結構130上之後，可以對前述的線路板進行電性測試（如：斷短路測試）、外觀檢查（如：自動光學辨識）或其他適宜的檢查或測試步驟。在一實施例中，若在進行前述的檢查或測試步驟之後，需要對前述的線路板進行再一次地檢查或測試步驟、重工（re-work）步驟及/或報廢，則由於是將多個線路板（如：第一線路板110及第二線路板120）配置於重佈線路結構130上，因此可以針對特定的線路板測試步驟、重工（re-work）步驟及/或移除後加以報廢。如此一來，在步驟上可以較為簡單，且/或成本也可以較為低廉。
請參照圖1C，可以形成第一絕緣體140於重佈線路結構130的第一連接面130a上。第一絕緣體140可以覆蓋第一線路板110及第二線路板120，且第一絕緣體140可以暴露出部分的第一線路板110及部分的第二線路板120。
在一實施例中，第一絕緣體140可以由模封材料（molding material）所形成。舉例而言，可以形成覆蓋第一線路板110及第二線路板120的模封材料。在一實施例中，模封材料例如是藉由模塑製程或其他適宜的方法將熔融的模塑化合物形成於重佈線路結構130的第一連接面130a上。然後，使熔融的模塑化合物冷卻並且固化。在一實施例中，至少藉由上述的步驟，可以形成第一絕緣體140。
在本實施例中，第一絕緣體140至少側向覆蓋第一線路板110及第二線路板120。在一實施例中，第一絕緣體140至少直接接觸第一線路板110的第一側面110c及第二線路板120的第二側面120c。在一實施例中，部分的第一絕緣體140位於第一線路板110及第二線路板120之間。在一實施例中，第一絕緣體140暴露出第一線路板110的第一頂面110a及第二線路板120的第二頂面120a。
在本實施例中，部分的第一絕緣體140可以更位於第一線路板110與重佈線路結構130之間。在一實施例中，位於第一線路板110與重佈線路結構130之間的部分第一絕緣體140可以更直接接觸第一線路板110的第一底面110b。
在本實施例中，部分的第一絕緣體140可以更位於第二線路板120與重佈線路結構130之間。在一實施例中，位於第二線路板120與重佈線路結構130之間的部分第一絕緣體140可以更直接接觸第二線路板120的第二底面120b。
請參照圖1C至圖1D，可以移除載板91（標示於圖1C），以暴露出重佈線路結構130的第二連接面130b。
請參照圖1D，配置第一導電端子163於第一線路板110上，且使第一導電端子163電性連接於第一線路板110中對應的線路。
請參照圖1D，配置第二導電端子164於第二線路板120上，且使第二導電端子164電性連接於第二線路板120中對應的線路。
在本實施例中，第一導電端子163或第二導電端子164可以包括焊球（solder ball）或具有其他形式或形狀的導電連接件。第一導電端子163或第二導電端子164可以經由置球（ball placement）、迴焊（reflow）及/或其他適宜的製程來形成。
值得注意的是，本發明並未限定移除載板91的步驟、配置第一導電端子163的步驟以及配置第二導電端子164的步驟的先後順序。
請參照圖1E，配置封裝件150於重佈線路結構130的第二連接面130b上，且使封裝件150電性連接於重佈線路結構130中對應的線路。
封裝件150包括第一晶片151、第二晶片152、模封體154、線路層153以及多個導電封裝端子156。模封體154包覆第一晶片151及第二晶片152。線路層153位於模封體154上。第一晶片151電性連接於線路層153中對應的線路。第二晶片152電性連接於線路層153中對應的線路。導電封裝端子156位於線路層153上且電性連接於線路層153中對應的線路。第一晶片151可以藉由線路層153中對應的線路、對應的導電封裝端子156電性連接於重佈線路結構130中對應的線路。第二晶片152可以藉由線路層153中對應的線路、對應的導電封裝端子156電性連接於重佈線路結構130中對應的線路。
在本實施例中，封裝件150所包括的晶片是以第一晶片151及第二晶片152為例，但本發明不限於此。在一實施例中，封裝件150中的晶片可以為僅有一個（如：第一晶片151或第二晶片152的其中之一）。在一實施例中，封裝件150中的晶片可以更包括其他相同或相似於第一晶片151或第二晶片152的晶片。
在本實施例中，封裝件150可以更包括電子元件155。電子元件155可以配置於線路層153上且在相對於第一晶片151及第二晶片152的一側。電子元件155可以電性連接於線路層153中對應的線路。在一實施例中，電子元件155可以是被動元件，但本發明不限於此。
在一實施例中，第一晶片151或第二晶片152可以是電力管理晶片（power management integrated circuit，PMIC）、微機電系統晶片（micro-electro-mechanical-system，MEMS）、特殊應用積體電路晶片（Application-specific integrated circuit，ASIC）、動態隨機存取記憶體晶片（dynamic random access memory，DRAM）、靜態隨機存取記憶體晶片（static random access memory，SRAM）、高頻寬記憶體（High Bandwidth Memory，HBM）晶片、系統晶片（system on chip，SoC）或其他類似的高效能運算（High Performance Computing，HPC）晶片，但本發明不限於此。
在一實施例中，第一晶片151與第二晶片152之間可以是同質的（homogeneous）晶片也可以是異質的（heterogeneous）晶片，於本發明並不加以限制。
在一實施例中，封裝件150可以是扇出封裝件（fan-out package）、晶圓級晶片尺寸封裝件（Wafer Level Chip Scale Package；WLCSP）、覆晶晶片尺寸級封裝件（Flip Chip Chip Scale Package；FCCSP）、窗型球閘陣列封裝件（Window BGA package；wBGA package）或其他適宜的封裝件，於本發明並不加以限制。
在一實施例中，被配置於重佈線路結構130上的封裝件150可以為已知合格封裝件（known good package，KGP）。舉例而言，在將封裝件150配置於重佈線路結構130上之前，可以對封裝件150進行電性測試（如：斷短路測試）、外觀檢查（如：自動光學辨識）或其他適宜的檢查或測試步驟。如此一來，可以確認被配置於重佈線路結構130上的封裝件150具有良好的功能，而可以提升封裝結構100（標示於圖1F或圖1G）的良率。
在本實施例中，可以在配置第一線路板110的步驟及配置第二線路板120的步驟之後，進行配置封裝件150的步驟。
在本實施例中，可以在封裝件150與重佈線路結構130之間形成填充層159，但本發明不限於此。填充層159例如是毛細填充膠或其他適宜的填充材料，但本發明不限於此。
值得注意的是，在圖1E中，僅示例性地繪示二個封裝件150，但本發明對於配置於第二連接面130b上的封裝件150的數量並不加以限制。
請參照圖1E至圖1F，在本實施例中，可以經由單一化製程（singulation process），以構成多個封裝結構100。單一化製程例如可以包括切割製程（dicing process/cutting process）以至少切穿重佈線路結構130及第一絕緣體140。
值得注意的是，在進行單一化製程之後，相似的元件符號將用於單一化後的元件。舉例而言，重佈線路結構130（如圖1E所示）於單一化後可以為重佈線路結構130（如圖1F所示），第一線路板110（如圖1E所示）於單一化後可以為第一線路板110（如圖1F所示），第二線路板120（如圖1E所示）於單一化後可以為第二線路板120（如圖1F所示），第一絕緣體140（如圖1E所示）於單一化後可以為第一絕緣體140（如圖1F所示），多個導電端子163、164（如圖1E所示）於單一化後可以為多個導電端子163、164（如圖1F所示），封裝件150（如圖1E所示）於單一化後可以為封裝件150（如圖1F所示），諸如此類。其他單一化後的元件將依循上述相同的元件符號規則，於此不加以贅述或特別繪示。
請參照圖1F，在本實施例中，可以配置殼體171於重佈線路結構130的第二連接面130b上。殼體171可以直接地或間接地連接重佈線路結構130。舉例而言，殼體171可以嵌入重佈線路結構130，而可以使殼體171直接地連接重佈線路結構130。又舉例而言，殼體171與重佈線路結構130之間可以具有黏著材，而可以使殼體171間接地連接重佈線路結構130。
值得注意的是，本發明並未限定單一化製程（若有）或配置殼體171的步驟（若有）的先後順序。
經過上述步驟後即可大致上完成本實施例的封裝結構100的製作。
請參照圖1F及圖1G，封裝結構100包括重佈線路結構130、第一線路板110、第二線路板120、第一絕緣體140、多個導電端子163、164以及封裝件150。重佈線路結構130具有第一連接面130a及第二連接面130b。第二連接面130b相對於第一連接面130a。第一線路板110配置在重佈線路結構130的第一連接面130a上且電性連接於重佈線路結構130。第二線路板120配置在重佈線路結構130的第一連接面130a上且電性連接於重佈線路結構130。第一絕緣體140位於重佈線路結構130的第一連接面130a上且包覆第一線路板110及第二線路板120。導電端子可以包括第一導電端子163或第二導電端子164。第一導電端子163可以配置在第一線路板110上且電性連接於第一線路板110。第二導電端子164可以配置在第二線路板120上且電性連接於第二線路板120。封裝件150包括第一晶片151、第二晶片152、模封體154、線路層153以及多個導電封裝端子156。封裝件150配置在重佈線路結構130的第二連接面130b上且電性連接於重佈線路結構130。
在本實施例中，重佈線路結構130的第一連接面130a及第二連接面130b基本上平行，但本發明不限於此。
在本實施例中，在垂直於第一連接面130a或第二連接面130b的投影方向D1上，第一線路板110及第二線路板120不重疊。在一實施例中，第一線路板110及第二線路板120可以是以側向（side by side）方式配置。
在本實施例中，在垂直於第一連接面130a或第二連接面130b的投影方向D1上，第一線路板110及第二線路板120完全重疊於重佈線路結構130。
在本實施例中，封裝結構100可以更包括殼體171。殼體171配置於重佈線路結構130的第二連接面130b上。殼體171具有容置空間171a，且封裝件150位於容置空間171a內。
在一實施例中，殼體171可以包括硬質的材質。如此一來，可以藉由殼體171保護位於其內的構件（如：封裝件150）。
在一實施例中，殼體171可以包括導電材質。在一可能的實施例中，導電的殼體171可以作為電磁干擾屏蔽（electromagnetic interference shielding；EMI shielding），而可以降低電磁干擾，但本發明不限於此。在一可能的實施例中，殼體171的導電部分可以作為天線，但本發明不限於此。
在一實施例中，殼體171可以包括導熱材質。導熱的殼體171可以熱耦接於封裝件150。
在本實施例中，殼體171與封裝件150之間可以具有空氣間隙（air gap）171b。
在本實施例中，在具有包含多晶片（如：第一晶片151及第二晶片152）的封裝件150的封裝結構100中，多個晶片之間（如：第一晶片151及第二晶片152之間）需藉由對應的線路進行電源或訊號的傳輸，且各個晶片需藉由對應的線路與外界（如：第一晶片151及第二晶片152藉由對應的線路板110、120與連接於導電端子163、164的外部電子元件）進行電源或訊號的傳輸。因此，藉由多個線路板（如：第一線路板110及第二線路板120）配置於重佈線路結構130上的方式，對於封裝結構100的製造方法可以較為簡單且/或成本也可以較為低廉。並且，對於封裝結構100的整體線路佈局中可以降低重佈線路結構130及/或封裝件150的線路層153的負載（如：可以降低重佈線路結構130及/或線路層153的導電層層數、容易最佳化重佈線路結構130及/或線路層153的導電層線寬、線距及/或線路佈局）。如此一來，可以提升封裝結構100的品質。
在本實施例中，藉由多個線路板（如：第一線路板110及第二線路板120）以及重佈線路結構130，可以將封裝結構100中對應的線路依照設計上的需求配置在對應的線路板（如：第一線路板110及第二線路板120）及/或重佈線路結構130。如此一來，可以使線路具有適當地配置。除此之外，相較於將線路集中於單一個線路板的配置方式，可能會造成前述的單一個線路板需具有較大的尺寸或較多的導電層數。因此，前述的單一個線路板的成本可能較高且/或良率可能較低。因此，藉由多個線路板（如：第一線路板110及第二線路板120）的配置方式，對於封裝結構100的製造方法可以較為簡單且/或成本也可以較為低廉。
圖2是依照本發明的第二實施例的一種封裝結構的部分剖視示意圖。第二實施例的封裝結構200的製造方法與第一實施例的封裝結構100的製造方法相似，其類似的構件以相同的標號表示，且具有類似的功能、材質或形成方式，並省略描述。
在本實施例中，封裝結構200可以包括重佈線路結構130、第一線路板110、第二線路板120、第一絕緣體140、多個導電端子163、164、封裝件150以及加強支撐件（stiffening support member）275。加強支撐件275可以位於重佈線路結構130於第一連接面130a上。第一絕緣體140可以包覆加強支撐件275。
在一實施例中，加強支撐件275可以包括支撐用晶粒（supporting die）。舉例而言，可以將不合格晶粒（ugly die）、失效晶粒（failed die）或其他類似的廢晶粒（dummy die）作為支撐用晶粒。如此一來，可以降低製作上的成本。
在一實施例中，加強支撐件275可以包括硬質支撐環。舉例而言，加強支撐件275可以包括環型的金屬條。在一實施例中，加強支撐件275可以被稱為加強環（stiffener ring）。
在一實施例中，加強支撐件275可以降低結構的翹曲（warpage）。
圖3是依照本發明的第三實施例的一種封裝結構的部分剖視示意圖。第三實施例的封裝結構300的製造方法與第一實施例的封裝結構100的製造方法相似，其類似的構件以相同的標號表示，且具有類似的功能、材質或形成方式，並省略描述。
在本實施例中，封裝結構300可以包括重佈線路結構130、第一線路板110、第二線路板120、第一絕緣體140、多個導電端子163、164、封裝件150以及第二絕緣體380。第二絕緣體380可以位於重佈線路結構130於第二連接面130b上。第二絕緣體380可以包覆封裝件150。
第二絕緣體380的材質或形成方式可以相同或相似於第一絕緣體140，故於此不加以贅述。
圖4A至圖4C是依照本發明的第四實施例的一種封裝結構的部分製造方法的部分剖視示意圖。第四實施例的封裝結構400的製造方法與第一實施例的封裝結構100的製造方法相似，其類似的構件以相同的標號表示，且具有類似的功能、材質或形成方式，並省略描述。
接續圖1B，請參照圖4A，在本實施例中，可以於重佈線路結構130的第一連接面130a上形成光敏介電材449（photoimageable dielectric material；PID material）。光敏介電材449可以覆蓋第一線路板110的第一頂面110a、第一底面110b以及第一側面110c。光敏介電材449可以覆蓋第二線路板120的第二頂面120a、第二底面120b以及第二側面120c。在一實施例中，光敏介電材449可以藉由塗佈法或其他適宜的製程形成，但本發明不限於此。在一實施例中，光敏介電材449可以直接接觸第一線路板110的第一頂面110a、第一底面110b以及第一側面110c。在一實施例中，光敏介電材449可以直接接觸第二頂面120a、第二底面120b以及第二側面120c。
請參照圖4A至圖4B，可以固化部分的光敏介電材449。並且，於固化部分的光敏介電材449之後，移除未被固化的其餘光敏介電材449。
舉例而言，光敏介電材449（標示於圖4A）可以具有第一絕緣部分449a（標示於圖4A）以及第二絕緣部分449b（標示於圖4A）。可以藉由光聚合（photopolymerization）及/或烘烤（baking）的方式將第一絕緣部分449a固化。然後，可以藉由濕清洗（wet clean）或其他適宜的方式移除未被固化的第二絕緣部分449b，以使固化後的第一絕緣部分449a圖案化，而形成具有多個第一絕緣開口441（標示於圖4B）及多個第二絕緣開口442（標示於圖4B）的第一絕緣體440（標示於圖4B）。第一絕緣體440可以覆蓋第一線路板110的第一底面110b、第一側面110c及部分的第一頂面110a。第一絕緣體440可以覆蓋第二線路板120的第二底面120b、第二側面120c及部分的第二頂面120a。第一絕緣開口441至少可以暴露位於第一頂面110a上的部分導電層。第二絕緣開口442至少可以暴露位於第二頂面120a上的部分導電層。
請參照圖4B至圖4C，藉由相同或相似於圖1D至圖1F所繪示的步驟，以形成本實施例的封裝結構400。
舉例而言，可以配置第一導電端子163於第一線路板110上。第一導電端子163可以嵌入第一絕緣體440的第一絕緣開口441，且使第一導電端子163電性連接於第一線路板110中對應的線路。
舉例而言，可以配置第二導電端子164於第二線路板120上。第二導電端子164可以嵌入第一絕緣體440的第二絕緣開口442，且使第二導電端子164電性連接於第二線路板120中對應的線路。
經過上述步驟後即可大致上完成本實施例的封裝結構400的製作。
請參照圖4C，封裝結構400包括重佈線路結構130、第一線路板110、第二線路板120、第一絕緣體440、多個導電端子163、164以及封裝件150。第一絕緣體440位於重佈線路結構130的第一連接面130a上且包覆第一線路板110及第二線路板120。
在本實施例中，部分的第一絕緣體440可以覆蓋第一線路板110的第一頂面110a。
在本實施例中，部分的第一絕緣體440可以覆蓋第二線路板120的第二頂面120a。
綜上所述，在本發明具有包含多晶片（如：第一晶片及第二晶片）的封裝件的封裝結構中，多個晶片之間（如：第一晶片及第二晶片之間）需藉由對應的線路進行電源或訊號的傳輸，且各個晶片需藉由對應的線路與外界（如：第一晶片及第二晶片藉由對應的線路板與連接於導電端子的外部電子元件）進行電源或訊號的傳輸。因此，藉由多個線路板（如：第一線路板及第二線路板）配置於重佈線路結構上的方式，對於封裝結構的製造方法可以較為簡單且/或成本也可以較為低廉。並且，對於封裝結構的整體線路佈局中可以降低重佈線路結構及/或封裝件的線路層的負載（如：可以降低重佈線路結構及/或線路層的導電層層數、容易最佳化重佈線路結構及/或線路層的導電層線寬、線距及/或線路佈局）。如此一來，可以提升封裝結構的品質。
100、200、300、400:封裝結構
110:第一線路板
110a:第一頂面
110b:第一底面
110c:第一側面
111:線路層
111a:表面
112:導電微孔
112c:側壁
113:絕緣材
120:第二線路板
120a:第二頂面
120b:第二底面
120c:第二側面
121:線路層
121a:表面
122:導電微孔
122c:側壁
123:絕緣材
130:重佈線路結構
130a:第一連接面
130b:第二連接面
140、440:第一絕緣體
441:第一絕緣開口
442:第二絕緣開口
449:光敏介電材
449a:第一絕緣部分
449b:第二絕緣部分
150:封裝件
151:第一晶片
152:第二晶片
153:線路層
154:模封體
155:電子元件
156:導電封裝端子
159:填充層
161:第一導電連接件
162:第二導電連接件
163:第一導電端子
164:第二導電端子
171:殼體
171a:容置空間
171b:空氣間隙
275:加強支撐件
380:第二絕緣體
91:載板
92:離型層
D1:投影方向
圖1A至圖1F是依照本發明的第一實施例的一種封裝結構的部分製造方法的部分剖視示意圖。 圖1G是依照本發明的第一實施例的一種封裝結構的部分上視示意圖。 圖2是依照本發明的第二實施例的一種封裝結構的部分剖視示意圖。 圖3是依照本發明的第三實施例的一種封裝結構的部分剖視示意圖。 圖4A至圖4C是依照本發明的第四實施例的一種封裝結構的部分製造方法的部分剖視示意圖。
100:封裝結構
110:第一線路板
111:線路層
112:導電微孔
113:絕緣材
120:第二線路板
121:線路層
122:導電微孔
123:絕緣材
130:重佈線路結構
130a:第一連接面
130b:第二連接面
140:第一絕緣體
150:封裝件
151:第一晶片
152:第二晶片
153:線路層
154:模封體
155:電子元件
156:導電封裝端子
159:填充層
161:第一導電連接件
162:第二導電連接件
163:第一導電端子
164:第二導電端子
171:殼體
171a:容置空間
171b:空氣間隙
D1:投影方向

Claims (6)

  1. 一種封裝結構，包括：重佈線路結構，具有第一連接面及相對於所述第一連接面的第二連接面；第一線路板，配置在所述第一連接面上且電性連接於所述重佈線路結構；第二線路板，配置在所述第一連接面上且電性連接於所述重佈線路結構；第一絕緣體，位於所述第一連接面上且包覆所述第一線路板及所述第二線路板；多個導電端子，配置在所述第一線路板或所述第二線路板上，且電性連接於所述第一線路板或所述第二線路板；以及封裝件，配置在所述第二連接面上且電性連接於所述重佈線路結構，且所述封裝件包括：多個晶片；模封體，包覆所述多個晶片；線路層，位於所述模封體上且電性連接於所述多個晶片；以及多個導電封裝端子，位於所述線路層上且電性連接於所述重佈線路結構，其中：所述第一線路板及所述第二線路板為無矽基底線路板；且 在垂直於所述第一連接面或所述第二連接面的投影方向上，所述第一線路板及所述第二線路板不重疊，所述第一線路板及所述第二線路板完全重疊於所述重佈線路結構，且所述封裝件重疊於所述第一線路板及所述第二線路板。
  2. 如請求項1所述的封裝結構，更包括：多個導電連接件，配置在所述第一線路板或所述第二線路板上，且所述第一線路板或所述第二線路板藉由對應的所述多個導電連接件電性連接於所述重佈線路結構。
  3. 如請求項2所述的封裝結構，其中部分的所述第一絕緣體位於所述第一線路板與所述重佈線路結構之間或位於所述第二線路板與所述重佈線路結構之間。
  4. 如請求項1所述的封裝結構，其中部分的所述第一絕緣體位於所述第一線路板及所述第二線路板之間。
  5. 一種封裝結構的製造方法，包括：形成重佈線路結構，其具有第一連接面及相對於所述第一連接面的第二連接面；配置第一線路板於所述第一連接面上，且使所述第一線路板電性連接於所述重佈線路結構；配置第二線路板於所述第一連接面上，且使所述第二線路板電性連接於所述重佈線路結構；形成第一絕緣體於所述第一連接面上，且所述第一絕緣體包覆所述第一線路板及所述第二線路板； 形成多個導電端子於所述第一線路板或所述第二線路板上，且所述多個導電端子電性連接於所述第一線路板或所述第二線路板；配置封裝件於所述第二連接面上，所述封裝件電性連接於所述重佈線路結構，且所述封裝件包括：至少一晶片；模封體，包覆所述至少一晶片；線路層，位於所述模封體上且電性連接於所述至少一晶片；以及多個導電封裝端子，位於所述線路層上且電性連接於所述線路層；以及在配置所述第一線路板的步驟及配置所述第二線路板的步驟之前，對所述重佈線路結構進行檢查或測試步驟；或在形成所述第一絕緣體之前，對所述第一線路板或所述第二線路板進行檢查或測試步驟。
  6. 如請求項5所述的封裝結構的製造方法，其中配置所述封裝件的步驟在配置所述第一線路板的步驟及配置所述第二線路板的步驟之後。
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