TWI710073B - 具有天線的半導體封裝及其製造方法 - Google Patents
具有天線的半導體封裝及其製造方法 Download PDFInfo
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Abstract
一種形成半導體封裝結構的方法包括:提供第一晶片級封裝結構。第一晶片級封裝結構包括:第一封裝層,形成在第一封裝層上的第一重分佈層結構,形成在第一重分佈層結構中並且對應於管芯區域的第一天線元件,以及位於第一封裝層中並且對應於管芯區域的半導體管芯。使用第一粘合層將第二晶片級封裝結構接合到第一重分佈層結構上。第二晶片級封裝結構包括:附著到第一粘合層的第二封裝層,以及形成在第二封裝層上的第二天線元件。在接合第二晶片級封裝結構之後,第二天線元件和第一天線元件形成貼片天線。
Description
本發明涉及一種半導體封裝結構,尤其涉及一種包括天線的扇出半導體封裝及其形成方法。
為了確保電子產品和通信設備的持續小型化和多功能性,半導體封裝必須尺寸小,支持多引腳連接,高速操作並具有高功能性。另外,在諸如射頻(RF)系統級封裝(system-in-package,SiP)元件的高頻應用中,天線通常用於實現無線通訊。
當構造具有天線的無線通訊封裝時,封裝設計需要提供良好的天線特性(例如高效率,寬頻寬等),同時提供可靠且低成本的封裝解決方案。近年來,已經開發出用於實現集成到半導體封裝中的天線(或複數個天線)的天線封裝(antenna-in-package,AiP)技術,以減小器件尺寸。
然而,AiP技術仍面臨許多挑戰,因此需要一種製造具有天線的半導體封裝的改進方法。
提供了半導體封裝結構及其形成方法。形成半導體封裝結構的方法的示例性實施例包括提供具有劃線區域和被劃線區域圍繞的管芯(die)區域的第一晶片級封裝結構。第一晶片級封裝結構包括第一封裝層,第一重分佈層(RDL)結構,第一天線元件和半導體管芯,其中,第一封裝層具有第一表面和與第一表面相對的第二表面,第一重分佈層結構形成在第一封裝層的第二表面上,第一天線元件形成在第一RDL結構中並且對應於管芯區域,半導體管芯位於第一封裝層中並且對應於管芯區域。使用第一粘合層(adhesive layer)將第二晶片級封裝結構接合到第一RDL結構上。第二晶片級封裝結構包括第二封裝層和第二天線元件,其中,第二封裝層具有附著到第一粘合層的第三表面和與第三表面相對的第四表面,第二天線元件形成在第二封裝層的第四表面上。在接合第二晶片級封裝結構之後,第二天線元件和第一天線元件形成貼片天線。
形成半導體封裝結構的方法的另一示例性實施例包括提供晶片級封裝結構,其具有複數個管芯區域和將複數個管芯區域彼此分離的劃線區域。晶片級封裝結構包括第一封裝層,第一RDL結構,複數個半導體管芯和複數個第一天線元件,其中第一封裝層具有第一表面和與第一表面相對的第二表面,第一RDL結構形成在第一封裝層的第二表面上,複數個半導體管芯位於第一封裝層中並且分別對應複數個管芯區域中的相應管芯區域,複數個第一天線元件形式在所述第一RDL結構中並分別對應於複數個管芯區域中的相應管芯區域。使用第一粘合層將至少一個封裝單元接合到第一RDL結構上。封裝單元位於複數個管芯區域中一個內,並包括第二封裝層和第二天線元件,其中,第二封裝層具有附著到第一粘合層的第三表面和與第三表面相對的第四表面,第二天線元件形成在第二封裝層的第四表面上。在接合所述封裝單元之後,第二天線元件和第一天線元件形成貼片天線。
半導體封裝結構的示例性實施例包括第一模塑複合材料層,該第一模塑複合材料層具有第一表面和與第一表面相對的第二表面。半導體封裝結構還包括在第一模塑複合材料層中的半導體管芯,和形成在第一模塑複合材料層的第二表面上並覆蓋半導體管芯的第一RDL結構。半導體封裝結構還包括第二模塑複合材料層,該第二模塑複合材料層形成在第一模塑複合材料層之上並具有第三表面和與第三表面相對的第四表面。半導體封裝結構還包括附著到第一RDL結構和第二模塑膠複合材料層的第三表面的第一粘合層,以及電耦接到半導體管芯的貼片天線。該貼片天線包括形成在第一RDL結構中的第一天線元件,以及形成在第二模塑複合材料層的第四表面上的第二天線元件。
本發明實施例提供的形成半導體封裝結構的方法和半導體封裝結構中,第二封裝層/第二模塑複合材料層通過使用粘合層的接合工藝形成在第一封裝層/第一模塑複合材料層之上,可以減少或消除在半導體封裝結構的製造中使用的熱處理。因此,可以減輕半導體封裝結構的翹曲。
具體實施方式參考附圖在以下實施例中給出詳細描述。
以下描述是實現本發明的最佳方案。 進行該描述是為了說明本發明的一般原理,而不應被視為具有限制意義。 可以通過參考所附請求項確定本發明的範圍。
將參照特定實施例並參考某些附圖來描述本發明,但是本發明不限於此,並且本發明僅受請求項的限制。所描述的附圖僅是示意性的而非限制性的。 在附圖中,為了說明的目的,一些元件的尺寸可能被放大而不是按比例繪製。尺寸和相對尺寸不對應於本發明實踐中的實際尺寸。
第1A至1D圖是根據一些實施例的形成半導體封裝結構的示例性方法的截面圖。如第1A圖所示,提供晶片級封裝結構10。晶片級封裝結構10具有管芯區域(也稱為晶片區域)和圍繞這些管芯區域的劃線區域,以便將相鄰的管芯區域彼此分開。為了簡化該圖,這裡僅描繪了3個完整的管芯區域D和分隔這些管芯區域D的劃線區域S。在一些實施例中,晶片級封裝結構10是倒裝晶片半導體封裝結構。
在一些實施例中,晶片級封裝結構10包括封裝層108,封裝層108具有底表面108a和與底表面108a相對的頂表面108b。在一些實施例中,封裝層108可以由模塑複合材料製成,例如環氧樹脂(epoxy),樹脂(resin),可模塑的聚合物等。在那些例子中,封裝層108可以在基本上為液體的時候施加,然後可以通過化學反應固化。在一些其他實施例中,封裝層108是紫外(UV)或熱固化的聚合物,其作為凝膠(gel)或可延展的固體(malleable solid)施加,能夠設置在半導體管芯周圍,然後通過UV或熱固化工藝固化。用模具(未示出)固化封裝層108。
在一些實施例中,晶片級封裝結構10還包括設置在封裝層108中的半導體管芯100,例如片上系統(system-on-chip,SOC)管芯,使得半導體管芯100的側壁被封裝層108包圍。複數個半導體管芯100可以分別對應於複數個管芯區域D。例如,每個管芯區域D包括至少一個半導體管芯100。例如,SOC管芯可以包括微控制器(microcontroller,MCU),微處理器(MPU),電源管理積體電路(power management integrated circuit,PMIC),全球定位系統(global positioning system,GPS)設備,射頻(radio frequency,RF)設備或其任何組合。
在一些實施例中,每個半導體管芯100具有第一側和與第一側相對的第二側。 更具體地,半導體管芯100的第一側具有主動(active)表面100a(也稱為前表面),並且半導體管芯100的第二側具有非主動表面100b(其也被稱為後表面)並且主動表面100a(也稱為前表面)與非主動表面100b相對。在一些實施例中,半導體管芯100的主動表面100a對應並鄰近封裝層108的底表面108a。半導體管芯100的非主動表面100b對應並鄰近封裝層108的頂表面108b。半導體管芯100的接墊101設置在主動表面100a上並電連接到半導體管芯100的電路(未示出)。
在一些實施例中,晶片級封裝結構10還包括重分佈層(redistribution layer,RDL)結構106,其形成在封裝層108的第一表面108a上並覆蓋每個半導體管芯100的主動表面100a。RDL結構106也稱為扇出結構。 RDL結構106通過接墊101電連接到每個半導體管芯100。
在一些實施例中,RDL結構106包括設置在金屬間電介質(inter-metal dielectric,IMD)層102中的一個或複數個導電跡線。更具體地,在一些實施例中,導電跡線103設置在IMD102的第一層級處,並且至少一個導電跡線103電耦接到半導體管芯100。此外,導電跡線105設置在不同於IMD層102的第一層級的第二層級。
在一些實施例中,IMD層102包括從每個半導體管芯100的主動表面100a連續堆疊的第一子介電層(sub-dielectric layer)102a和第二子介電層102b,從而導電跡線103形成在第一子介電層102a中,以及導電跡線105形成在第二子介電層102b中。應該注意的是,第1A圖中所示的RDL結構106的導電跡線的數量和子介質層的數量僅是示例,並非是對本發明的限制。
在一些實施例中,IMD層102由包括聚合物基底材料的有機材料,或者包括氮化矽(SiNX
),氧化矽(SiOX
),石墨烯的非有機材料等製成。 例如,第一子介質層102a和第二子介質層102b由聚合物基底材料製成。在一些其他實施例中,IMD層102是高k介電層(k是介電層的介電常數)。在一些其他實施例中,IMD層102可以由光敏材料製成,其包括幹膜光致抗蝕劑(dry film photoresist)或膠帶膜(taping film)。
在一些實施例中,晶片級封裝結構10包括形成在RDL結構106上並且電耦接到RDL結構106的導電結構150,使得導電結構150通過RDL結構106與封裝層108和半導體管芯100分離。因此,導電結構150不與封裝層108和半導體管芯100接觸。在一些實施例中,RDL結構106中的至少一個導電跡線105電耦接到一個或複數個導電結構150,使得導電結構150經由RDL結構106電耦接到半導體管芯100。每個導電結構150可以包括導電凸塊結構,例如銅凸塊或焊料凸塊結構。或者,每個導電結構150包括導電柱結構,導電線結構或導電膏結構(conductive paste structure)。
在一些實施例中,晶片級封裝結構10還包括形成在封裝層108中並穿過封裝層108的通孔結構110(有時稱為貫穿絕緣體通孔(through insulator via,TIV))。複數個通孔結構110可以分別對應於管芯區域D。例如,每個管芯區域D包括至少一個通孔結構110。通孔結構110電耦接到RDL結構106的導電跡線103並且可以由銅製成。
在一些實施例中,晶片級封裝結構10還包括天線112並且天線112電耦接到半導體管芯100。更具體地,在一些實施例中,天線112形成在封裝層108中。複數個天線112可以分別對應於管芯區域D。 例如,每個管芯區域D包括至少一個天線112。在一些實施例中,天線112經由RDL結構106的至少一個導電跡線103電耦接到半導體管芯100。在一些實施例中,天線112是偶極天線。在一些實施例中,形成天線112的方法和材料與形成通孔結構110的方法和材料相同或相似。
在一些實施例中,晶片級封裝結構10還包括形成在封裝層108的頂表面108b上並覆蓋每個半導體管芯100的非主動表面100b的RDL結構120。RDL結構 120可以具有與RDL結構106類似的結構,並且也稱為扇出結構。在一些實施例中,每個半導體管芯100的非主動表面100b經由粘合層114(其有時被稱為管芯附著膜)附著到RDL結構120,使得半導體管芯100和封裝層108被插入在RDL結構106和RDL結構120之間。
在一些實施例中,RDL結構120包括IMD層121和IMD層121中的導電跡線(未示出)。IMD層121可以是單層或多層結構。形成IMD層121的方法和材料可以與形成IMD層102的方法和材料相同或相似。類似地,形成RDL結構120的導電跡線的方法和材料可以與形成RDL結構106的導電跡線103和105的方法和材料相同或相似。換言之,形成RDL結構106的工藝可用於形成RDL結構120。
在一些實施例中,晶片級封裝結構10還包括形成在RDL結構120中的第一天線元件130a。複數個第一天線元件130a可以分別對應於管芯區域D。例如,每個管芯區域D包括至少一個第一天線元件130a。在一些實施例中,對應於管芯區域D的第一天線元件130a用作貼片天線(patch antenna)的一部分,該貼片天線隨後形成在相應的半導體管芯100上。
在一些實施例中,第一天線元件130a嵌入在RDL結構120的IMD層121中。在一些實施例中,形成在封裝層108中的通孔結構110電耦接在第一天線元件130a和 RDL結構106的至少一個導電跡線103之間,使得半導體管芯100電耦接到第一天線元件130a。
在一些實施例中,第一天線元件130a由RDL結構120中的至少一個導電跡線製成。在一些例子中,形成第一天線元件130a的方法和材料可以與形成RDL結構106的IMD層102中導電跡線103和105的方法和材料相同或者相似。
如第1B圖所示,在一些實施例中,提供晶片級封裝結構20。晶片級封裝結構20包括封裝層124,封裝層124具有底表面124a和與底表面124a相對的頂表面124b。
在一些實施例中,封裝層124由與封裝層108的材料相同或相似的材料製成。例如,封裝層124可以由模塑複合材料製成,例如,環氧樹脂,樹脂,可模塑的聚合物等。封裝層124可以在基本上為液體的時候施加,然後可以通過化學反應固化。在一些其他實施例中,封裝層124是紫外(UV)或熱固化聚合物,其作為凝膠或可延展固體施加,能夠設置在半導體管芯周圍,然後通過UV或熱固化工藝固化。可以用模具(未示出)固化封裝層124。
在一些實施例中,晶片級封裝結構20還包括形成在封裝層124的頂表面124b上的第二天線元件130b。在一些實施例中,第二天線元件130b形成在封裝層124上並與封裝層124直接接觸。在一些實施例中,第二天線元件130b可以由與第一天線元件130a的材料相同或相似的材料製成。
如第1C圖所示,使用粘合層122將晶片級封裝結構20接合到晶片級封裝結構10的RDL結構120上。類似於第一天線元件130a,在將晶片級封裝結構20接合到晶片級封裝結構10之後,複數個第二天線元件130b可以分別對應於管芯區域D。例如,在接合晶片級封裝結構20之後,每個管芯區域D包括至少一個第二天線元件130b並且第二天線元件130b對應於第一天線元件130a。在這些例子中,第二天線元件130b,相應的第一天線元件130a,和第一天線元件130a與第二天線元件130b之間的封裝層124在相應的管芯區域D中形成天線結構。天線結構電耦接到相應的管芯區域D中的半導體管芯100。在天線結構中,第一天線元件130a和相應的第二天線元件130b形成天線130,例如貼片天線。第一天線元件130a和第二天線元件130b之間的封裝層124用作天線130(例如,貼片天線)的諧振器(resonator)。
在一些實施例中,在將晶片級封裝結構20接合到晶片級封裝結構10上之前,在RDL結構106上形成支撐層160(例如,膠層或膠帶),該支撐層160覆蓋導電結構150,如圖1C所示。在一些實施例中,支撐層160用作載體,以在晶片級封裝結構10與晶片級封裝結構20的接合期間支撐晶片級封裝結構10。此外,支撐層160也用作保護層,以在晶片級封裝結構10和晶片級封裝結構20的接合期間保護導電結構150。
在一些實施例中,在將晶片級封裝結構20接合到晶片級封裝結構10上之前,在晶片級封裝結構10的RDL結構120上形成粘合層122。之後,封裝層124的底部表面124a附著到粘合層122,以將晶片級封裝結構20接合到晶片級封裝結構10上。
或者,在將晶片級封裝結構20接合到晶片級封裝結構10上之前,在封裝層124的底表面124a上形成粘合層122。之後,封裝層124的底部表面124a上的粘合層122被附著到晶片級封裝結構10的RDL結構120,以將晶片級封裝結構20接合到晶片級封裝結構10上。在晶片級封裝結構20接合到晶片級封裝結構10上之後,從RDL結構106中移除支撐層160。
然後,對第1C圖所示的結構執行分割工藝(也稱為切割工藝),以形成單獨的半導體封裝結構。更具體地,沿著劃線區域S切割晶片級封裝結構10和20以及它們之間的粘合層122,從而分離出每個管芯區域D。例如,可以使用切割鋸(dicing saw)或鐳射來執行切割過程。在執行分割工藝之後,形成單獨的半導體封裝結構30,並且為了簡化圖示描繪了一個半導體封裝結構30,如第1D圖所示。在一些其他實施例中,在執行分割工藝之後,從RDL結構106移除支撐層160。
如第1D圖所示,半導體封裝結構30包括封裝層108(例如,模塑複合材料層),其具有至少一個半導體管芯100,至少一個通孔結構110,以及至少一個偶極天線112。RDL結構106和120分別形成在封裝層108的底表面108a和頂表面108b上並覆蓋半導體管芯100。粘合層114將半導體管芯100的非主動表面100b附著到RDL結構120。此外,導電結構150形成在RDL結構106上並且電耦接到RDL結構106。
半導體封裝結構30還包括經由粘合層122在封裝層108上形成的封裝層124(例如,模塑複合材料層)。粘合層122附著到RDL結構120和封裝層124的底表面124a。半導體封裝結構30還包括電耦接到半導體管芯100的至少一個貼片天線130。貼片天線130包括形成在RDL結構120中的第一天線元件130a和形成在封裝層124的頂表面124b上的第二天線元件130b。
在一些實施例中,封裝層108的側壁基本上與封裝層124的側壁和粘合層122的側壁對齊。
半導體封裝結構30可以安裝在基底(base)(未示出)上。例如,半導體封裝結構30可以是片上系統(system-on-chip,SOC)封裝結構。 此外,基底可以包括印刷電路板(PCB)並且可以由聚丙烯(polypropylene,PP)製成。或者,基底是封裝基板,半導體封裝結構30通過接合工藝(bonding process)安裝在基底上。 在一些實施例中,半導體封裝結構30的導電結構150通過接合工藝安裝在基底上並且電耦接到基底。
第2A圖至第2C圖是根據一些實施例的形成半導體封裝結構的示例性方法的截面圖。實施例的一些元件的描述與前面參考第1A圖到第1D圖描述的那些實施例的相應元件的描述相同或相似,為簡潔起見,在下文中可省略。 如第2A圖所示,提供封裝單元20a。在一些實施例中,封裝單元20a通過切割第1B圖中所示的晶片級封裝結構20而形成。每個封裝單元20a包括通過切割第1B圖中所示的封裝層124而形成的封裝層124'。此外,每個封裝單元20a具有底表面124a和與底表面124a相對的頂表面124b,以及形成在封裝層124'的頂表面上的至少一個第二天線元件130b。
如第2B圖所示,根據一些實施例,提供封裝單元20a並使用粘合層122'將封裝單元20a接合到第1A圖所示的晶片級封裝結構10上。在一些實施例中,封裝單元20a的數量等於晶片級封裝結構10的管芯區域D的數量。在一些例子中,在封裝單元20a被接合到晶片級封裝結構10之後,複數個第二天線元件130b可以分別對應於複數個管芯區域D。例如,在接合封裝單元20a之後,每個管芯區域D包括至少一個第二天線元件130b,並且第二天線元件130b對應於第一天線元件130a。在那些例子中,第一天線元件130a和對應的第二天線元件130b形成天線130,例如貼片天線。
在一些其他實施例中,封裝單元20a的數量小於晶片級封裝結構10的管芯區域D的數量。在那些例子下,複數個封裝單元20a分別接合到具有已知良好的半導體管芯的複數個管芯區域D。
在一些實施例中,類似於第1A圖中所示的晶片級封裝結構10,在封裝單元20a接合到晶片級封裝結構10上之前,在RDL結構106上形成支撐層160(未示出)並且該支撐層160覆蓋導電結構150。
在一些實施例中,在封裝單元20a接合到晶片級封裝結構10上之前,粘合層122'形成在封裝層124'的底表面124a上,如第2A圖所示。然後,將封裝層124'的底表面124a上的粘合層122'附著到晶片級封裝結構10的RDL結構120,以便將封裝單元20a接合到晶片級封裝結構10上。在將封裝單元20a接合到晶片級封裝結構10上之後,從RDL結構106移除支撐層160。
然後,在第2B圖所示的結構上執行分割工藝,以形成單獨的半導體封裝結構。更具體地,沿著劃線區域S切割晶片級封裝結構10,從而分離出每個管芯區域D。在執行分割工藝之後,形成單獨的半導體封裝結構30a,並且為了簡化圖示描繪了一個半導體封裝結構30a,如第2C圖所示。在一些其他實施例中,在執行分割工藝之後,從RDL結構106移除支撐層160。
如第2C圖所示,半導體封裝結構30a類似於第1D圖中所示的半導體封裝結構30,除了粘合層122'的側壁基本上與封裝層124'的側壁對齊,並且封裝層108的側壁從封裝層124'的側壁橫向突出之外。在一些實施例中,封裝層124'的側壁與封裝層108的側壁之間的橫向距離d1在約1μm至約100μm的範圍內。
在一些實施例中,在封裝單元20a接合到晶片級封裝結構10上之前,粘合層122'形成在晶片級封裝結構10的RDL結構120的整個表面上並且覆蓋晶片級封裝結構10的RDL結構120的整個表面。 然後,將封裝層124'的底表面124a附著到粘合層122',以便將封裝單元20a接合到晶片級封裝結構10上。在封裝單元20a接合之後,沿著劃線區域S切割粘合層122' 和晶片級封裝結構10,從而分離出每個管芯區域D。在執行分割工藝之後,形成各個半導體封裝結構30b,並且為了簡化圖示描繪了一個半導體封裝結構30b,如第3圖所示。
如第3圖所示,半導體封裝結構30b類似於第2C圖中所示的半導體封裝結構30a。 除了粘合層122'的側壁基本上與封裝層108的側壁對齊並且從封裝層124'的側壁橫向突出之外。在一些實施例中,封裝層124'的側壁與封裝層108的側壁之間的橫向距離d1在約1μm至約100μm的範圍內。
根據前述實施例,半導體封裝結構被設計為製造具有接合兩個封裝層的粘合層的半導體封裝結構。用作貼片天線的諧振器的上封裝層通過使用粘合層的接合工藝形成在下封裝層之上,該下封裝層具有一個或複數個半導體管芯。與在下封裝層上沉積上封裝層相比,可以減少或消除在半導體封裝結構的製造中使用的熱處理。因此,可以減輕晶片級封裝結構的翹曲(warpage),並且可以增加RDL結構中的導電跡線的數量和子介電層的數量。由於RDL結構中導電跡線的增加,可以增加半導體封裝結構的設計靈活性。
此外,由於上封裝層通過接合工藝形成在下封裝層之上,因此在下封裝層之上形成上封裝層期間,可以使用諸如膠層或膠帶的支撐層來代替昂貴的載體基板(carrier substrate)。因此,可以降低製造成本和時間。
此外,由於複數個封裝單元分別接合到具有已知良好的半導體管芯的複數個管芯區域,所以封裝單元的數量可以小於晶片級封裝結構的管芯區域的數量。因此,可以進一步降低製造成本。
儘管已經通過示例並且根據優選實施例描述了本發明,但是應該理解,本發明不限於所公開的實施例。相反,旨在涵蓋各種修改和類似的佈置(對於本領域技術人員來說是顯而易見的)。因此,所附請求項的範圍應當被賦予最廣泛的解釋,以包含所有這些修改和類似的安排。
10‧‧‧晶片級封裝結構;D‧‧‧管芯區域;S‧‧‧劃線區域;10‧‧‧晶片級封裝結構;108‧‧‧封裝層;108a‧‧‧封裝層的底表面;108b‧‧‧封裝層的頂表面;100‧‧‧半導體管芯;100a‧‧‧半導體管芯的主動表面;100b‧‧‧半導體管芯的非主動表面;101‧‧‧接墊;106‧‧‧重分佈層結構;102‧‧‧金屬間電介質層;103‧‧‧導電跡線;105‧‧‧導電跡線;102a‧‧‧第一子介電層;102b‧‧‧第二子介電層;150‧‧‧導電結構;110‧‧‧通孔結構;112‧‧‧天線;114‧‧‧粘合層;120‧‧‧RDL結構;121‧‧‧IMD層;130a‧‧‧第一天線元件;20‧‧‧晶片級封裝結構;124‧‧‧封裝層;124a‧‧‧封裝層的底表面;124b‧‧‧封裝層的頂表面;130b‧‧‧第二天線元件;122‧‧‧粘合層;160‧‧‧支撐層;30‧‧‧半導體封裝結構;20a‧‧‧封裝單元;124'‧‧‧封裝層;122'‧‧‧粘合層;d1‧‧‧橫向距離;30a‧‧‧半導體封裝結構;30b‧‧‧半導體封裝結構。
通過參考附圖閱讀隨後的詳細描述和實施例,可以更全面地理解本發明,其中: 第1A至1D圖是根據一些實施例的形成半導體封裝結構的示例性方法的截面圖; 第2A至2C圖是根據一些實施例的形成半導體封裝結構的示例性方法的截面圖; 第3圖是根據一些實施例的示例性半導體封裝結構的截面圖。
10‧‧‧晶片級封裝結構
D‧‧‧管芯區域
S‧‧‧劃線區域
10‧‧‧晶片級封裝結構
108‧‧‧封裝層
108a‧‧‧封裝層的底表面
108b‧‧‧封裝層的頂表面
100‧‧‧半導體管芯
100a‧‧‧半導體管芯的主動表面
100b‧‧‧半導體管芯的非主動表面
101‧‧‧接墊
106‧‧‧重分佈層結構
102‧‧‧金屬間電介質層
103‧‧‧導電跡線
105‧‧‧導電跡線
102a‧‧‧第一子介電層
102b‧‧‧第二子介電層
150‧‧‧導電結構
110‧‧‧通孔結構
112‧‧‧天線
114‧‧‧粘合層
120‧‧‧RDL結構
121‧‧‧IMD層
130a‧‧‧第一天線元件
20‧‧‧晶片級封裝結構
124‧‧‧封裝層
124a‧‧‧封裝層的底表面
124b‧‧‧封裝層的頂表面
130b‧‧‧第二天線元件
122‧‧‧粘合層
160‧‧‧支撐層
Claims (25)
- 一種形成半導體封裝結構的方法,包括:提供具有劃線區域和被所述劃線區域圍繞的管芯區域的第一晶片級封裝結構,其中,所述第一晶片級封裝結構包括:第一封裝層,具有第一表面和與第一表面相對的第二表面;第一重分佈層結構,形成在所述第一封裝層的第二表面上;第一天線元件,形成在所述第一重分佈層結構中並且對應於所述管芯區域;半導體管芯,位於所述第一封裝層中並且對應於所述管芯區域;使用第一粘合層將第二晶片級封裝結構接合到第一重分佈層結構上,其中所述第二晶片級封裝結構包括:第二封裝層,具有附著到所述第一粘合層的第三表面和與所述第三表面相對的第四表面;以及第二天線元件,形成在所述第二封裝層的第四表面上,其中,在接合所述第二晶片級封裝結構之後,所述第二天線元件和所述第一天線元件形成貼片天線。
- 根據申請專利範圍第1項所述之方法,進一步包括:沿著所述劃線區域,切割所述第一晶片級封裝結構,所述第二晶片級封裝結構,和在所述第一晶片級封裝結構和所述第二晶片級封裝結構之間的所述第一粘合層。
- 根據申請專利範圍第1項所述之方法,其中,所述第一晶片級封裝結構進一步包括:第二重分佈層結構,形成在所述第一封裝層的所述第一表面上;複數個導電結構,形成在所述第二重分佈層上並電耦接到所述第二重分佈層結構。
- 根據申請專利範圍第3項所述之方法,其中,在接合所述第二晶片級封裝結構之前,在所述第二重分佈層上形成支撐層,並且所述支撐層覆蓋 所述複數個導電結構。
- 根據申請專利範圍第1項所述之方法,其中,所述第一晶片級封裝結構還包括形成在所述第一封裝層中並對應於所述管芯區域的通孔結構和偶極天線。
- 根據申請專利範圍第1項所述之方法,其中,所述第二封裝層由模塑複合材料製成。
- 根據申請專利範圍第1項所述之方法,其中,所述半導體管芯具有非主動表面,所述非主動表面被使用第二粘合層附著到所述第一重分佈層結構。
- 根據申請專利範圍第1項所述之方法,其中,在接合所述第二晶片級封裝結構之前,所述第二封裝層的所述第三表面被附著到所述第一粘合層。
- 根據申請專利範圍第1項所述之方法,其中,在接合所述第二晶片級封裝結構之前,所述第一重分佈層結構被附著到所述第一粘合層。
- 一種形成半導體封裝結構的方法,包括:提供具有劃線區域和複數個管芯區域的晶片級封裝結構,其中,所述劃線區域將所述複數個管芯區域彼此分離,其中所述晶片級封裝結構包括:第一封裝層,具有第一表面和與第一表面相對的第二表面;第一重分佈層結構,形成在所述第一封裝層的第二表面上;複數個半導體管芯,位於所述第一封裝層中並且分別的對應於所述複數個管芯區域中的相應管芯區域;以及複數個第一天線元件,形成在所述第一重分佈層結構中並且分別的對應於所述複數個管芯區域中的相應管芯區域;使用第一粘合層將至少一個封裝單元接合到所述第一重分佈層結構上,其中所述封裝單元在所述複數個管芯區域中的一個內並且包括: 第二封裝層,具有附著到所述第一粘合層的第三表面和與所述第三表面相對的第四表面;以及第二天線元件,形成在所述第二封裝層的第四表面上,其中,在接合所述封裝單元之後,所述第二天線元件和所述第一天線元件形成貼片天線。
- 根據申請專利範圍第10項所述之方法,進一步包括:沿著所述劃線區域,切割所述晶片級封裝結構。
- 根據申請專利範圍第10項所述之方法,其中,所述晶片級封裝結構進一步包括:第二重分佈層結構,形成在所述第一封裝層的所述第一表面上;複數個導電結構,形成在所述第二重分佈層上並電耦接到所述第二重分佈層結構。
- 根據申請專利範圍第12項所述之方法,進一步包括:在接合所述封裝單元之前,在所述第二重分佈層上形成支撐層,並且所述支撐層覆蓋所述複數個導電結構。
- 根據申請專利範圍第10項所述之方法,其中,所述晶片級封裝結構還包括形成在所述第一封裝層中的至少一個通孔結構和至少一個偶極天線。
- 根據申請專利範圍第10項所述之方法,其中,所述第二封裝層由模塑複合材料製成。
- 根據申請專利範圍第10項所述之方法,其中,所述複數個半導體管芯中每一個半導體管芯具有非主動表面,所述非主動表面被使用第二粘合層附著到所述第一重分佈層結構。
- 根據申請專利範圍第10項所述之方法,其中,在接合所述封裝單元之前,所述第二封裝層的所述第三表面被附著到所述第一粘合層。
- 根據申請專利範圍第10項所述之方法,其中,在接合所述封裝 單元之前,所述第一重分佈層結構被附著到所述第一粘合層。
- 一種半導體封裝結構,包括:第一模塑複合材料層,具有第一表面和與所述第一表面相對的第二表面;半導體管芯,位於所述第一模塑複合材料層中;第一重分佈層結構,形成在所述第一模塑複合材料層的所述第二表面上,並且覆蓋所述半導體管芯;第二模塑複合材料層,具有第三表面和與所述第三表面相對的第四表面;第一粘合層,附著在所述第一重分佈層結構和所述第二模塑複合材料層的所述第三表面上,使得所述第二模塑複合材料層被接合到所述第一重分佈層結構之上;以及貼片天線,電耦接到所述半導體管芯上,包括:第一天線元件,形成在所述第一重分佈層結構中;以及第二天線元件,形成在所述第二模塑複合材料層的所述第四表面上。
- 根據申請專利範圍第19項所述之半導體封裝結構,其中,所述第一模塑複合材料層的側壁與所述第二模塑複合材料層的側壁和所述第一粘合層的側壁基本對齊。
- 根據申請專利範圍第19項所述之半導體封裝結構,所述第一粘合層的側壁與所述第一模塑複合材料層的側壁基本對齊,並且從所述第二模塑複合材料層的側壁橫向突出。
- 根據申請專利範圍第19項所述之半導體封裝結構,所述第一粘合層的側壁與所述第二模塑複合材料層的側壁基本對齊,並且所述第一模塑複合材料層的側壁從所述第二模塑複合材料層的側壁橫向突出。
- 根據申請專利範圍第19項所述之半導體封裝結構,進一步包括: 第二重分佈層結構,形成在所述第一封裝層的所述第一表面上;複數個導電結構,形成在所述第二重分佈層結構上並電耦接到所述第二重分佈層結構。
- 根據申請專利範圍第19項所述之半導體封裝結構,進一步包括形成在第一封裝層中的通孔結構和偶極天線。
- 根據申請專利範圍第19項所述之半導體封裝結構,進一步包括:第二粘合層,將所述半導體管芯的非主動表面附著到所述第一重分佈層結構。
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