CN110491843B - 具有天线的半导体封装及其制造方法 - Google Patents
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Abstract
本发明提供一种形成半导体封装结构的方法,包括:提供第一晶片级封装结构,第一晶片级封装结构包括:第一封装层,具有第一表面和与第一表面相对的第二表面;第一重分布层结构,形成在第一封装层的第二表面上;第一天线元件,形成在第一重分布层结构中并且对应于管芯区域;半导体管芯,位于第一封装层中并且对应于管芯区域;使用第一粘合层将第二晶片级封装结构接合到第一重分布层结构上,其中第二晶片级封装结构包括:第二封装层,具有附着到第一粘合层的第三表面和与第三表面相对的第四表面;以及第二天线元件,形成在第二封装层的第四表面上,其中,在接合第二晶片级封装结构之后,第二天线元件和第一天线元件形成贴片天线。
Description
技术领域
本发明涉及一种半导体封装结构,尤其涉及一种包括天线的扇出半导体封装及其形成方法。
背景技术
为了确保电子产品和通信设备的持续小型化和多功能性,半导体封装必须尺寸小,支持多引脚连接,高速操作并具有高功能性。另外,在诸如射频(RF)系统级封装(system-in-package,SiP)组件的高频应用中,天线通常用于实现无线通信。
当构造具有天线的无线通信封装时,封装设计需要提供良好的天线特性(例如高效率,宽带宽等),同时提供可靠且低成本的封装解决方案。近年来,已经开发出用于实现集成到半导体封装中的天线(或多个天线)的天线封装(antenna-in-package,AiP)技术,以减小器件尺寸。
然而,AiP技术仍面临许多挑战,因此需要一种制造具有天线的半导体封装的改进方法。
发明内容
提供了半导体封装结构及其形成方法。形成半导体封装结构的方法的示例性实施例包括提供具有划线区域和被划线区域围绕的管芯(die)区域的第一晶片级封装结构。第一晶片级封装结构包括第一封装层,第一重分布层(RDL)结构,第一天线元件和半导体管芯,其中,第一封装层具有第一表面和与第一表面相对的第二表面,第一重分布层结构形成在第一封装层的第二表面上,第一天线元件形成在第一RDL结构中并且对应于管芯区域,半导体管芯位于第一封装层中并且对应于管芯区域。使用第一粘合层(adhesive layer)将第二晶片级封装结构接合到第一RDL结构上。第二晶片级封装结构包括第二封装层和第二天线元件,其中,第二封装层具有附着到第一粘合层的第三表面和与第三表面相对的第四表面,第二天线元件形成在第二封装层的第四表面上。在接合第二晶片级封装结构之后,第二天线元件和第一天线元件形成贴片天线。
形成半导体封装结构的方法的另一示例性实施例包括提供晶片级封装结构,其具有多个管芯区域和将多个管芯区域彼此分离的划线区域。晶片级封装结构包括第一封装层,第一RDL结构,多个半导体管芯和多个第一天线元件,其中第一封装层具有第一表面和与第一表面相对的第二表面,第一RDL结构形成在第一封装层的第二表面上,多个半导体管芯位于第一封装层中并且分别对应多个管芯区域中的相应管芯区域,多个第一天线元件形式在所述第一RDL结构中并分别对应于多个管芯区域中的相应管芯区域。使用第一粘合层将至少一个封装单元接合到第一RDL结构上。封装单元位于多个管芯区域中一个内,并包括第二封装层和第二天线元件,其中,第二封装层具有附着到第一粘合层的第三表面和与第三表面相对的第四表面,第二天线元件形成在第二封装层的第四表面上。在接合所述封装单元之后,第二天线元件和第一天线元件形成贴片天线。
半导体封装结构的示例性实施例包括第一模塑复合材料层,该第一模塑复合材料层具有第一表面和与第一表面相对的第二表面。半导体封装结构还包括在第一模塑复合材料层中的半导体管芯,和形成在第一模塑复合材料层的第二表面上并覆盖半导体管芯的第一RDL结构。半导体封装结构还包括第二模塑复合材料层,该第二模塑复合材料层形成在第一模塑复合材料层之上并具有第三表面和与第三表面相对的第四表面。半导体封装结构还包括附着到第一RDL结构和第二模塑料复合材料层的第三表面的第一粘合层,以及电耦接到半导体管芯的贴片天线。该贴片天线包括形成在第一RDL结构中的第一天线元件,以及形成在第二模塑复合材料层的第四表面上的第二天线元件。
本发明实施例提供的形成半导体封装结构的方法和半导体封装结构中,第二封装层/第二模塑复合材料层通过使用粘合层的接合工艺形成在第一封装层/第一模塑复合材料层之上,可以减少或消除在半导体封装结构的制造中使用的热处理。因此,可以减轻半导体封装结构的翘曲。
具体实施方式参考附图在以下实施例中给出详细描述。
附图说明
通过参考附图阅读随后的详细描述和实施例,可以更全面地理解本发明,其中:
图1A至1D是根据一些实施例的形成半导体封装结构的示例性方法的截面图;
图2A至2C是根据一些实施例的形成半导体封装结构的示例性方法的截面图;
图3是根据一些实施例的示例性半导体封装结构的截面图。
具体实施方式
以下描述是实现本发明的最佳方案。进行该描述是为了说明本发明的一般原理,而不应被视为具有限制意义。可以通过参考所附权利要求确定本发明的范围。
将参照特定实施例并参考某些附图来描述本发明,但是本发明不限于此,并且本发明仅受权利要求的限制。所描述的附图仅是示意性的而非限制性的。在附图中,为了说明的目的,一些元件的尺寸可能被放大而不是按比例绘制。尺寸和相对尺寸不对应于本发明实践中的实际尺寸。
图1A至1D是根据一些实施例的形成半导体封装结构的示例性方法的截面图。如图1A所示,提供晶片级封装结构10。晶片级封装结构10具有管芯区域(也称为芯片区域)和围绕这些管芯区域的划线区域,以便将相邻的管芯区域彼此分开。为了简化该图,这里仅描绘了3个完整的管芯区域D和分隔这些管芯区域D的划线区域S。在一些实施例中,晶片级封装结构10是倒装芯片半导体封装结构。
在一些实施例中,晶片级封装结构10包括封装层108,封装层108具有底表面108a和与底表面108a相对的顶表面108b。在一些实施例中,封装层108可以由模塑复合材料制成,例如环氧树脂(epoxy),树脂(resin),可模塑的聚合物等。在那些例子中,封装层108可以在基本上为液体的时候施加,然后可以通过化学反应固化。在一些其他实施例中,封装层108是紫外(UV)或热固化的聚合物,其作为凝胶(gel)或可延展的固体(malleable solid)施加,能够设置在半导体管芯周围,然后通过UV或热固化工艺固化。用模具(未示出)固化封装层108。
在一些实施例中,晶片级封装结构10还包括设置在封装层108中的半导体管芯100,例如片上系统(system-on-chip,SOC)管芯,使得半导体管芯100的侧壁被封装层108包围。多个半导体管芯100可以分别对应于多个管芯区域D。例如,每个管芯区域D包括至少一个半导体管芯100。例如,SOC管芯可以包括微控制器(microcontroller,MCU),微处理器(MPU),电源管理集成电路(power management integrated circuit,PMIC),全球定位系统(global positioning system,GPS)设备,射频(radio frequency,RF)设备或其任何组合。
在一些实施例中,每个半导体管芯100具有第一侧和与第一侧相对的第二侧。更具体地,半导体管芯100的第一侧具有主动(active)表面100a(也称为前表面),并且半导体管芯100的第二侧具有非主动表面100b(其也被称为后表面)并且主动表面100a(也称为前表面)与非主动表面100b相对。在一些实施例中,半导体管芯100的主动表面100a对应并邻近封装层108的底表面108a。半导体管芯100的非主动表面100b对应并邻近封装层108的顶表面108b。半导体管芯100的接垫101设置在主动表面100a上并电连接到半导体管芯100的电路(未示出)。
在一些实施例中,晶片级封装结构10还包括重分布层(redistribution layer,RDL)结构106,其形成在封装层108的第一表面108a上并覆盖每个半导体管芯100的主动表面100a。RDL结构106也称为扇出结构。RDL结构106通过接垫101电连接到每个半导体管芯100。
在一些实施例中,RDL结构106包括设置在金属间电介质(inter-metaldielectric,IMD)层102中的一个或多个导电迹线。更具体地,在一些实施例中,导电迹线103设置在IMD102的第一层级处,并且至少一个导电迹线103电耦接到半导体管芯100。此外,导电迹线105设置在不同于IMD层102的第一层级的第二层级。
在一些实施例中,IMD层102包括从每个半导体管芯100的主动表面100a连续堆叠的第一子介电层(sub-dielectric layer)102a和第二子介电层102b,从而导电迹线103形成在第一子介电层102a中,以及导电迹线105形成在第二子介电层102b中。应该注意的是,图1A中所示的RDL结构106的导电迹线的数量和子介质层的数量仅是示例,并非是对本发明的限制。
在一些实施例中,IMD层102由包括聚合物基底材料的有机材料,或者包括氮化硅(SiNX),氧化硅(SiOX),石墨烯的非有机材料等制成。例如,第一子介质层102a和第二子介质层102b由聚合物基底材料制成。在一些其他实施例中,IMD层102是高k介电层(k是介电层的介电常数)。在一些其他实施例中,IMD层102可以由光敏材料制成,其包括干膜光致抗蚀剂(dry film photoresist)或胶带膜(taping film)。
在一些实施例中,晶片级封装结构10包括形成在RDL结构106上并且电耦接到RDL结构106的导电结构150,使得导电结构150通过RDL结构106与封装层108和半导体管芯100分离。因此,导电结构150不与封装层108和半导体管芯100接触。在一些实施例中,RDL结构106中的至少一个导电迹线105电耦接到一个或多个导电结构150,使得导电结构150经由RDL结构106电耦接到半导体管芯100。每个导电结构150可以包括导电凸块结构,例如铜凸块或焊料凸块结构。或者,每个导电结构150包括导电柱结构,导电线结构或导电膏结构(conductive paste structure)。
在一些实施例中,晶片级封装结构10还包括形成在封装层108中并穿过封装层108的通孔结构110(有时称为贯穿绝缘体通孔(through insulator via,TIV))。多个通孔结构110可以分别对应于管芯区域D。例如,每个管芯区域D包括至少一个通孔结构110。通孔结构110电耦接到RDL结构106的导电迹线103并且可以由铜制成。
在一些实施例中,晶片级封装结构10还包括天线112并且天线112电耦接到半导体管芯100。更具体地,在一些实施例中,天线112形成在封装层108中。多个天线112可以分别对应于管芯区域D。例如,每个管芯区域D包括至少一个天线112。在一些实施例中,天线112经由RDL结构106的至少一个导电迹线103电耦接到半导体管芯100。在一些实施例中,天线112是偶极天线。在一些实施例中,形成天线112的方法和材料与形成通孔结构110的方法和材料相同或相似。
在一些实施例中,晶片级封装结构10还包括形成在封装层108的顶表面108b上并覆盖每个半导体管芯100的非主动表面100b的RDL结构120。RDL结构120可以具有与RDL结构106类似的结构,并且也称为扇出结构。在一些实施例中,每个半导体管芯100的非主动表面100b经由粘合层114(其有时被称为管芯附着膜)附着到RDL结构120,使得半导体管芯100和封装层108被插入在RDL结构106和RDL结构120之间。
在一些实施例中,RDL结构120包括IMD层121和IMD层121中的导电迹线(未示出)。IMD层121可以是单层或多层结构。形成IMD层121的方法和材料可以与形成IMD层102的方法和材料相同或相似。类似地,形成RDL结构120的导电迹线的方法和材料可以与形成RDL结构106的导电迹线103和105的方法和材料相同或相似。换言之,形成RDL结构106的工艺可用于形成RDL结构120。
在一些实施例中,晶片级封装结构10还包括形成在RDL结构120中的第一天线元件130a。多个第一天线元件130a可以分别对应于管芯区域D。例如,每个管芯区域D包括至少一个第一天线元件130a。在一些实施例中,对应于管芯区域D的第一天线元件130a用作贴片天线(patch antenna)的一部分,该贴片天线随后形成在相应的半导体管芯100上。
在一些实施例中,第一天线元件130a嵌入在RDL结构120的IMD层121中。在一些实施例中,形成在封装层108中的通孔结构110电耦接在第一天线元件130a和RDL结构106的至少一个导电迹线103之间,使得半导体管芯100电耦接到第一天线元件130a。
在一些实施例中,第一天线元件130a由RDL结构120中的至少一个导电迹线制成。在一些例子中,形成第一天线元件130a的方法和材料可以与形成RDL结构106的IMD层102中导电迹线103和105的方法和材料相同或者相似。
如图1B所示,在一些实施例中,提供晶片级封装结构20。晶片级封装结构20包括封装层124,封装层124具有底表面124a和与底表面124a相对的顶表面124b。
在一些实施例中,封装层124由与封装层108的材料相同或相似的材料制成。例如,封装层124可以由模塑复合材料制成,例如,环氧树脂,树脂,可模塑的聚合物等。封装层124可以在基本上为液体的时候施加,然后可以通过化学反应固化。在一些其他实施例中,封装层124是紫外(UV)或热固化聚合物,其作为凝胶或可延展固体施加,能够设置在半导体管芯周围,然后通过UV或热固化工艺固化。可以用模具(未示出)固化封装层124。
在一些实施例中,晶片级封装结构20还包括形成在封装层124的顶表面124b上的第二天线元件130b。在一些实施例中,第二天线元件130b形成在封装层124上并与封装层124直接接触。在一些实施例中,第二天线元件130b可以由与第一天线元件130a的材料相同或相似的材料制成。
如图1C所示,使用粘合层122将晶片级封装结构20接合到晶片级封装结构10的RDL结构120上。类似于第一天线元件130a,在将晶片级封装结构20接合到晶片级封装结构10之后,多个第二天线元件130b可以分别对应于管芯区域D。例如,在接合晶片级封装结构20之后,每个管芯区域D包括至少一个第二天线元件130b并且第二天线元件130b对应于第一天线元件130a。在这些例子中,第二天线元件130b,相应的第一天线元件130a,和第一天线元件130a与第二天线元件130b之间的封装层124在相应的管芯区域D中形成天线结构。天线结构电耦接到相应的管芯区域D中的半导体管芯100。在天线结构中,第一天线元件130a和相应的第二天线元件130b形成天线130,例如贴片天线。第一天线元件130a和第二天线元件130b之间的封装层124用作天线130(例如,贴片天线)的谐振器(resonator)。
在一些实施例中,在将晶片级封装结构20接合到晶片级封装结构10上之前,在RDL结构106上形成支撑层160(例如,胶层或胶带),该支撑层160覆盖导电结构150,如图1C所示。在一些实施例中,支撑层160用作载体,以在晶片级封装结构10与晶片级封装结构20的接合期间支撑晶片级封装结构10。此外,支撑层160也用作保护层,以在晶片级封装结构10和晶片级封装结构20的接合期间保护导电结构150。
在一些实施例中,在将晶片级封装结构20接合到晶片级封装结构10上之前,在晶片级封装结构10的RDL结构120上形成粘合层122。之后,封装层124的底部表面124a附着到粘合层122,以将晶片级封装结构20接合到晶片级封装结构10上。
或者,在将晶片级封装结构20接合到晶片级封装结构10上之前,在封装层124的底表面124a上形成粘合层122。之后,封装层124的底部表面124a上的粘合层122被附着到晶片级封装结构10的RDL结构120,以将晶片级封装结构20接合到晶片级封装结构10上。在晶片级封装结构20接合到晶片级封装结构10上之后,从RDL结构106中移除支撑层160。
然后,对图1C所示的结构执行分割工艺(也称为切割工艺),以形成单独的半导体封装结构。更具体地,沿着划线区域S切割晶片级封装结构10和20以及它们之间的粘合层122,从而分离出每个管芯区域D。例如,可以使用切割锯(dicing saw)或激光来执行切割过程。在执行分割工艺之后,形成单独的半导体封装结构30,并且为了简化图示描绘了一个半导体封装结构30,如图1D所示。在一些其他实施例中,在执行分割工艺之后,从RDL结构106移除支撑层160。
如图1D所示,半导体封装结构30包括封装层108(例如,模塑复合材料层),其具有至少一个半导体管芯100,至少一个通孔结构110,以及至少一个偶极天线112。RDL结构106和120分别形成在封装层108的底表面108a和顶表面108b上并覆盖半导体管芯100。粘合层114将半导体管芯100的非主动表面100b附着到RDL结构120。此外,导电结构150形成在RDL结构106上并且电耦接到RDL结构106。
半导体封装结构30还包括经由粘合层122在封装层108上形成的封装层124(例如,模塑复合材料层)。粘合层122附着到RDL结构120和封装层124的底表面124a。半导体封装结构30还包括电耦接到半导体管芯100的至少一个贴片天线130。贴片天线130包括形成在RDL结构120中的第一天线元件130a和形成在封装层124的顶表面124b上的第二天线元件130b。
在一些实施例中,封装层108的侧壁基本上与封装层124的侧壁和粘合层122的侧壁对齐。
半导体封装结构30可以安装在基底(base)(未示出)上。例如,半导体封装结构30可以是片上系统(system-on-chip,SOC)封装结构。此外,基底可以包括印刷电路板(PCB)并且可以由聚丙烯(polypropylene,PP)制成。或者,基底是封装基板,半导体封装结构30通过接合工艺(bonding process)安装在基底上。在一些实施例中,半导体封装结构30的导电结构150通过接合工艺安装在基底上并且电耦接到基底。
图2A至2C是根据一些实施例的形成半导体封装结构的示例性方法的截面图。实施例的一些元件的描述与前面参考图1和图2描述的那些实施例的相应元件的描述相同或相似,为简洁起见,在下文中可省略。如图2A所示,提供封装单元20a。在一些实施例中,封装单元20a通过切割图1B中所示的晶片级封装结构20而形成。每个封装单元20a包括通过切割图1B中所示的封装层124而形成的封装层124'。此外,每个封装单元20a具有底表面124a和与底表面124a相对的顶表面124b,以及形成在封装层124'的顶表面上的至少一个第二天线元件130b。
如图2B所示,根据一些实施例,提供封装单元20a并使用粘合层122'将封装单元20a接合到图1A所示的晶片级封装结构10上。在一些实施例中,封装单元20a的数量等于晶片级封装结构10的管芯区域D的数量。在一些例子中,在封装单元20a被接合到晶片级封装结构10之后,多个第二天线元件130b可以分别对应于1个或者多个管芯区域D。例如,在接合封装单元20a之后,每个管芯区域D包括至少一个第二天线元件130b,并且第二天线元件130b对应于第一天线元件130a。在那些例子中,第一天线元件130a和对应的第二天线元件130b中形成天线130,例如贴片天线。
在一些其他实施例中,封装单元20a的数量小于晶片级封装结构10的管芯区域D的数量。在那些例子下,多个封装单元20a分别接合到具有已知良好的半导体管芯的多个管芯区域D。
在一些实施例中,类似于图1A中所示的晶片级封装结构10,在封装单元20a接合到晶片级封装结构10上之前,在RDL结构106上形成支撑层160(未示出)并且该支撑层160覆盖导电结构150。
在一些实施例中,在封装单元20a接合到晶片级封装结构10上之前,粘合层122'形成在封装层124'的底表面124a上,如图2A所示。然后,将封装层124'的底表面124a上的粘合层122'附着到晶片级封装结构10的RDL结构120,以便将封装单元20a接合到晶片级封装结构10上。在将封装单元20a接合到晶片级封装结构10上之后,从RDL结构106移除支撑层160。
然后,在图2B所示的结构上执行分割工艺,以形成单独的半导体封装结构。更具体地,沿着划线区域S切割晶片级封装结构10,从而分离出每个管芯区域D。在执行分割工艺之后,形成单独的半导体封装结构30a,并且为了简化图示描绘了一个半导体封装结构30a,如图2C所示。在一些其他实施例中,在执行分割工艺之后,从RDL结构106移除支撑层160。
如图2C所示,半导体封装结构30a类似于图1D中所示的半导体封装结构30,除了粘合层122'的侧壁基本上与封装层124'的侧壁对齐,並且封装层108的侧壁从封装层124'的侧壁横向突出之外。在一些实施例中,封装层124'的侧壁与封装层108的侧壁之间的横向距离d1在约1μm至约100μm的范围内。
在一些实施例中,在封装单元20a接合到晶片级封装结构10上之前,粘合层122'形成在晶片级封装结构10的RDL结构120的整个表面上并且覆盖晶片级封装结构10的RDL结构120的整个表面。然后,将封装层124'的底表面124a附着到粘合层122',以便将封装单元20a接合到晶片级封装结构10上。在封装单元20a接合之后,沿着划线区域S切割粘合层122'和晶片级封装结构10,从而分离出每个管芯区域D。在执行分割工艺之后,形成各个半导体封装结构30b,并且为了简化图示描绘了一个半导体封装结构30b,如图3所示。
如图3所示,半导体封装结构30b类似于图2C中所示的半导体封装结构30a,除了粘合层122'的侧壁基本上与封装层108的侧壁对齐并且从封装层124'的侧壁横向突出之外。在一些实施例中,封装层124'的侧壁与封装层108的侧壁之间的横向距离d1在约1μm至约100μm的范围内。
根据前述实施例,半导体封装结构被设计为制造具有接合两个封装层的粘合层的半导体封装结构。用作贴片天线的谐振器的上封装层通过使用粘合层的接合工艺形成在下封装层之上,该下封装层具有一个或多个半导体管芯。与在下封装层上沉积上封装层相比,可以减少或消除在半导体封装结构的制造中使用的热处理。因此,可以减轻晶片级封装结构的翘曲(warpage),并且可以增加RDL结构中的导电迹线的数量和子介电层的数量。由于RDL结构中导电迹线的增加,可以增加半导体封装结构的设计灵活性。
此外,由于上封装层通过接合工艺形成在下封装层之上,因此在下封装层之上形成上封装层期间,可以使用诸如胶层或胶带的支撑层来代替昂贵的载体基板(carriersubstrate)。因此,可以降低制造成本和时间。
此外,由于多个封装单元分别接合到具有已知良好的半导体管芯的多个管芯区域,所以封装单元的数量可以小于晶片级封装结构的管芯区域的数量。因此,可以进一步降低制造成本。
尽管已经通过示例并且根据优选实施例描述了本发明,但是应该理解,本发明不限于所公开的实施例。相反,旨在涵盖各种修改和类似的布置(对于本领域技术人员来说是显而易见的)。因此,所附权利要求的范围应当被赋予最广泛的解释,以包含所有这些修改和类似的安排。
Claims (25)
1.一种形成半导体封装结构的方法,其特征在于:
提供具有划线区域和被所述划线区域围绕的管芯区域的第一晶片级封装结构,其中,所述第一晶片级封装结构包括:
第一封装层,具有第一表面和与第一表面相对的第二表面;
第一重分布层结构,形成在所述第一封装层的第二表面上;
第一天线元件,形成在所述第一重分布层结构中并且对应于所述管芯区域;
半导体管芯,位于所述第一封装层中并且对应于所述管芯区域;
使用第一粘合层将第二晶片级封装结构接合到第一重分布层结构上,其中所述第二晶片级封装结构包括:
第二封装层,具有附着到所述第一粘合层的第三表面和与所述第三表面相对的第四表面;以及
第二天线元件,形成在所述第二封装层的第四表面上,其中,在接合所述第二晶片级封装结构之后,所述第二天线元件和所述第一天线元件形成贴片天线。
2.根据权利要求1所述的方法,其特征在于:进一步包括:沿着所述划线区域,切割所述第一晶片级封装结构,所述第二晶片级封装结构,和在所述第一晶片级封装结构和所述第二晶片级封装结构之间的所述第一粘合层。
3.根据权利要求1所述的方法,其特征在于:所述第一晶片级封装结构进一步包括:
第二重分布层结构,形成在所述第一封装层的所述第一表面上;
多个导电结构,形成在所述第二重分布层上并电耦接到所述第二重分布层结构。
4.根据权利要求3所述的方法,其特征在于:在接合所述第二晶片级封装结构之前,在所述第二重分布层上形成支撑层,并且所述支撑层覆盖所述多个导电结构。
5.根据权利要求1所述的方法,其特征在于:所述第一晶片级封装结构还包括形成在所述第一封装层中并对应于所述管芯区域的通孔结构和偶极天线。
6.根据权利要求1所述的方法,其特征在于:所述第二封装层由模塑复合材料制成。
7.根据权利要求1所述的方法,其特征在于:所述半导体管芯具有非主动表面,所述非主动表面被使用第二粘合层附着到所述第一重分布层结构。
8.根据权利要求1所述的方法,其特征在于:在接合所述第二晶片级封装结构之前,所述第二封装层的所述第三表面被附着到所述第一粘合层。
9.根据权利要求1所述的方法,其特征在于:在接合所述第二晶片级封装结构之前,所述第一重分布层结构被附着到所述第一粘合层。
10.一种形成半导体封装结构的方法,其特征在于:
提供具有划线区域和多个管芯区域的晶片级封装结构,其中,所述划线区域将所述多个管芯区域彼此分离,其中所述晶片级封装结构包括:
第一封装层,具有第一表面和与第一表面相对的第二表面;
第一重分布层结构,形成在所述第一封装层的第二表面上;
多个半导体管芯,位于所述第一封装层中并且分别的对应于所述多个管芯区域中的相应管芯区域;以及
多个第一天线元件,形成在所述第一重分布层结构中并且分别的对应于所述多个管芯区域中的相应管芯区域;
使用第一粘合层将至少一个封装单元接合到所述第一重分布层结构上,其中所述封装单元在所述多个管芯区域中的一个内并且包括:
第二封装层,具有附着到所述第一粘合层的第三表面和与所述第三表面相对的第四表面;以及
第二天线元件,形成在所述第二封装层的第四表面上,其中,在接合所述封装单元之后,所述第二天线元件和所述第一天线元件形成贴片天线。
11.根据权利要求10所述的方法,其特征在于:进一步包括:沿着所述划线区域,切割所述晶片级封装结构。
12.根据权利要求10所述的方法,其特征在于:所述晶片级封装结构进一步包括:
第二重分布层结构,形成在所述第一封装层的所述第一表面上;
多个导电结构,形成在所述第二重分布层上并电耦接到所述第二重分布层结构。
13.根据权利要求12所述的方法,其特征在于:进一步包括:在接合所述封装单元之前,在所述第二重分布层上形成支撑层,并且所述支撑层覆盖所述多个导电结构。
14.根据权利要求10所述的方法,其特征在于:所述晶片级封装结构还包括形成在所述第一封装层中的至少一个通孔结构和至少一个偶极天线。
15.根据权利要求10所述的方法,其特征在于:所述第二封装层由模塑复合材料制成。
16.根据权利要求10所述的方法,其特征在于:所述多个半导体管芯中每一个半导体管芯具有非主动表面,所述非主动表面被使用第二粘合层附着到所述第一重分布层结构。
17.根据权利要求10所述的方法,其特征在于:在接合所述封装单元之前,所述第二封装层的所述第三表面被附着到所述第一粘合层。
18.根据权利要求10所述的方法,其特征在于:在接合所述封装单元之前,所述第一重分布层结构被附着到所述第一粘合层。
19.一种半导体封装结构,其特征在于,包括:
第一模塑复合材料层,具有第一表面和与所述第一表面相对的第二表面;
半导体管芯,位于所述第一模塑复合材料层中;
第一重分布层结构,形成在所述第一模塑复合材料层的所述第二表面上,并且覆盖所述半导体管芯;
第二模塑复合材料层,具有第三表面和与所述第三表面相对的第四表面;
第一粘合层,附着在所述第一重分布层结构和所述第二模塑复合材料层的所述第三表面上,使得所述第二模塑复合材料层被接合到所述第一重分布层结构之上;以及
贴片天线,电耦接到所述半导体管芯上,包括:
第一天线元件,形成在所述第一重分布层结构中;以及
第二天线元件,形成在所述第二模塑复合材料层的所述第四表面上。
20.根据权利要求19所述的半导体封装结构,其特征在于:所述第一模塑复合材料层的侧壁与所述第二模塑复合材料层的侧壁和所述第一粘合层的侧壁基本对齐。
21.根据权利要求19所述的半导体封装结构,其特征在于:所述第一粘合层的侧壁与所述第一模塑复合材料层的侧壁基本对齐,并且从所述第二模塑复合材料层的侧壁横向突出。
22.根据权利要求19所述的半导体封装结构,其特征在于:所述第一粘合层的侧壁与所述第二模塑复合材料层的侧壁基本对齐,并且所述第一模塑复合材料层的侧壁从所述第二模塑复合材料层的侧壁横向突出。
23.根据权利要求19所述的半导体封装结构,其特征在于,进一步包括:
第二重分布层结构,形成在所述第一模塑复合材料层的所述第一表面上;
多个导电结构,形成在所述第二重分布层结构上并电耦接到所述第二重分布层结构。
24.根据权利要求19所述的半导体封装结构,其特征在于,进一步包括形成在所述第一模塑复合材料层中的通孔结构和偶极天线。
25.根据权利要求19所述的半导体封装结构,其特征在于,进一步包括:第二粘合层,将所述半导体管芯的非主动表面附着到所述第一重分布层结构。
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