TW201916191A - 具有無矽基底的中介層的封裝及其形成方法 - Google Patents

具有無矽基底的中介層的封裝及其形成方法 Download PDF

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TW201916191A
TW201916191A TW106135773A TW106135773A TW201916191A TW 201916191 A TW201916191 A TW 201916191A TW 106135773 A TW106135773 A TW 106135773A TW 106135773 A TW106135773 A TW 106135773A TW 201916191 A TW201916191 A TW 201916191A
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dielectric layer
device die
dielectric layers
dielectric
forming
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TW106135773A
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TWI664685B (zh
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余振華
陳憲偉
陳明發
葉松峯
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台灣積體電路製造股份有限公司
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Abstract

一種方法包括形成多個介電層，在所述多個介電層中形成多條重佈線，在所述多個介電層中形成堆疊通孔，所述堆疊通孔形成穿透所述多個介電層的連續電性連接，在所述堆疊通孔及所述多個介電層之上形成介電層，在所述介電層中形成多個接墊，以及藉由混合接合將裝置晶粒接合至所述介電層以及所述多個接墊的第一部分。

Description

具有無矽基底的中介層的封裝及其形成方法
隨著更多裝置晶粒被封裝於同一封裝中以達成更多功能，積體電路的封裝正變得日益複雜。舉例而言，封裝可包括接合至同一中介層的多個裝置晶粒（例如，處理器及記憶體立方）。可基於半導體基底來形成中介層，在所述半導體基底中形成矽穿孔以對形成於所述中介層的相對兩側上的各特徵進行內連。裝置晶粒包封於模塑化合物中。包括中介層及裝置晶粒的封裝進一步接合至封裝基底。另外，表面安裝裝置（surface mount device）亦可接合至基底。散熱器（heat spreader）可貼合至裝置晶粒的頂表面以發散在所述裝置晶粒中所產生的熱量。散熱器可具有固定至封裝基底上的外圍部分（skirt portion）。
以下揭露內容提供用於實作本發明的不同特徵的諸多不同的實施例或實例。以下闡述組件及排列的具體實例以簡化本揭露內容。當然，該些僅為實例且不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本發明可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的，但自身並不表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「之下（underlying）」、「下面（below）」、「下部的（lower）」、「上覆（overlying）」、「上部的（upper）」等空間相對性用語來闡述圖中所示的一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括裝置在使用或操作中的不同定向。設備可具有其他定向（旋轉90度或處於其他定向）且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
根據各種示例性實施例提供一種基於無矽基底（無矽）的中介層而形成的封裝及其形成方法。根據一些實施例說明形成所述封裝的各中間階段。對一些實施例的一些變型進行論述。在各個圖中及說明性實施例通篇中，相同的參考編號用於表示相同的元件。
圖1至圖27A說明根據本發明一些實施例的封裝的形成過程中的各中間階段的剖視圖。圖1至圖27A中所示步驟亦示意性地反映於圖39中所示製程流程300中。
圖1說明載體20及形成於載體20上的釋放層22。載體20可為玻璃載體、矽晶圓、有機載體等。載體20可具有圓的俯視圖形狀，且可具有常用矽晶圓的大小。舉例而言，載體20可具有8英吋的直徑、12英吋的直徑等。釋放層22可由光熱轉換（Light To Heat Conversion，LTHC）材料形成，其可與載體20一起自將在後續步驟中形成的上覆結構被移除。根據本發明的一些實施例，釋放層22是由環氧系熱釋放材料形成。可將釋放層22塗佈至載體20上。將釋放層22的頂表面整平且所述頂表面具有高的共面程度（degree of co-planarity）。根據替代性實施例，使用被標記為23的矽晶圓而不使用載體20及釋放層22。在釋放層22上形成介電層24。根據本發明的一些實施例，介電層24是由非聚合物（無機材料）形成，所述非聚合物可為氧化矽、氮化矽、氮氧化矽等。當使用矽晶圓時，可直接在矽晶圓23上形成層24。
在介電層24之上形成重佈線（Redistribution Line，RDL）26。重佈線26的形成可包括：在介電層24之上形成晶種層（圖中未示出），在所述晶種層之上形成例如光阻等圖案化罩幕（圖中未示出），且接著對暴露出的晶種層執行金屬鍍覆。接著移除圖案化罩幕及晶種層的被所述圖案化罩幕所覆蓋的部分，進而留下如圖1中的重佈線26。根據本發明的一些實施例，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沈積（Physical Vapor Deposition，PVD）等來形成所述晶種層。可使用例如無電鍍覆（electro-less plating）等來執行鍍覆。
進一步參照圖1，在重佈線26上形成介電層28。介電層28的底表面可接觸重佈線26及介電層24的頂表面。根據本發明的一些實施例，介電層28是由非聚合物（無機材料）形成，所述非聚合物可為氧化矽、氮化矽等。根據本發明的一些實施例，介電層28是由聚合物形成，所述聚合物可為聚醯亞胺、聚苯並噁唑（Polybenzoxazole，PBO）等聚合物形成。接著將介電層28圖案化以在其中形成開口30。因此，重佈線26的一些部分經由介電層28中的開口30暴露出。
接下來，參照圖2，形成連接至重佈線26的重佈線32。重佈線32包括位於介電層28之上的金屬跡線（金屬線）。重佈線32亦包括延伸至介電層28中的開口中的通孔。亦在鍍覆製程中形成重佈線32，其中重佈線32中的每一者包括晶種層（圖中未示出）及位於所述晶種層之上的鍍覆金屬材料。晶種層及鍍覆材料可由相同材料或不同材料形成。重佈線32可包含金屬或金屬合金（包括鋁、銅、鎢或其合金）。形成介電層28及34以及重佈線32及36的步驟被表示為如圖39中所示製程流程300中的步驟302。
參照圖3，在重佈線32及介電層28之上形成介電層34。介電層34可由無機材料形成，所述無機材料可選自氧化矽、氮化矽、碳氮化矽（silicon carbo-nitride）、氮氧化矽等。
圖3進一步說明重佈線36的形成，重佈線36電性連接至重佈線32。重佈線36的形成可採用與形成重佈線32的方法及材料相似的方法及材料。應知，儘管在說明性示例性實施例中論述兩個介電層28及34以及形成於其中的相應重佈線32及36，然而可依據佈線要求及使用聚合物以緩衝應力的要求而採用更少或更多介電層。舉例而言，可存在單一介電層或者三個、四個或更多個介電層。
圖4說明保護層38及42以及重佈線40及44的形成。相應步驟被示為如圖39中所示製程流程300中的步驟304。根據本發明的一些實施例，保護層38及42是由例如氧化矽、氮化矽、碳氮化矽、氮氧化矽、氧碳氮化矽（silicon oxy-carbo-nitride）、未經摻雜的矽酸鹽玻璃（Un-doped Silicate Glass，USG）或其多層等無機材料形成。保護層38及42中的每一者可為單層或複合層，且可由非多孔性材料形成。根據本發明的一些實施例，保護層38及42中的一者或二者為複合層，所述複合層包括氧化矽層（圖中未單獨示出）及位於所述氧化矽層之上的氮化矽層（圖中未單獨示出）。如後續段落中所將論述，保護層38及42具有阻止水分及有害化學物質進入封裝中的導電特徵（例如，精細節距重佈線（fine-pitch RDL））的功能。
重佈線40及44可由鋁、銅、鋁銅、鎳或其合金形成。根據本發明的一些實施例，如圖11中所示，將重佈線44的一些部分形成為金屬接墊，所述金屬接墊大到足以安置後續形成的介電層穿孔（Through-Dielectric Via，TDV）。根據一些實施例，相應地將該些金屬接墊稱作金屬接墊44或鋁接墊44。此外，保護層的數目可為任何整數，例如一個、兩個（如所示）、三個或更多個。
圖5說明一或多個介電層的形成。舉例而言，如所示，可形成介電層46以在其中嵌置頂部重佈線44。介電層48形成於介電層46之上，且可充當蝕刻終止層。根據本發明的一些實施例，亦可使用單一介電層來取代介電層46及48。介電層46及48的可用材料包括氧化矽、氮化矽、碳化矽、氮氧化矽等。
圖6、圖7及圖8說明根據本發明一些實施例的介電層及精細節距重佈線的形成。相應步驟被示為如圖39中所示製程流程300中的步驟306。形成方法可採用所述基於矽基底來形成裝置晶粒的內連結構的方法。舉例而言，內連結構的形成方法可包括單一鑲嵌製程（single damascene process）及/或雙重鑲嵌製程（dual damascene process）。因此，所得重佈線亦稱作金屬線及通孔，對應介電層亦稱作金屬間介電質（Inter-Metal-Dielectric，IMD）層。
參照圖6，形成通孔55、介電層50A及54A以及蝕刻終止層52A。介電層50A及54A可由氧化矽、氮氧化矽、氮化矽、或類似材料或介電常數（k）值低於約3.0的低介電常數介電材料形成。低介電常數介電材料可包括黑金剛石（Black Diamond）（應用材料公司的註冊商標）、含碳低介電常數介電材料、氫矽倍半氧烷（Hydrogen SilsesQuioxane，HSQ）、甲基矽倍半氧烷（MethylSilsesQuioxane，MSQ）等。蝕刻終止層52A是由相對於介電層50A及54A具有高蝕刻選擇性的材料形成，且可由碳化矽、碳氮化矽等形成。根據替代性實施例，不形成蝕刻終止層52A。
在介電層52A及54A中形成用於佈線的精細節距重佈線56A。儘管在一些示例性實施例中將通孔55及精細節距重佈線56A示為具有單一鑲嵌結構，通孔55與精細節距重佈線56A組合起來可具有雙重鑲嵌結構。應知，所示單個精細節距重佈線56A代表多條精細節距重佈線。由於根據本發明一些實施例的精細節距重佈線是使用鑲嵌製程而形成，因此所述精細節距重佈線可被形成為非常薄的且具有小於例如0.8微米（µm）的節距（自所述結構的頂部觀察）。此外，由於介電層34、38、42、46及48皆可由無機材料形成，因此精細節距重佈線的節距及寬度可為小的。若介電層28亦由無機材料形成，則精細節距重佈線的節距及寬度可進一步減小，以使得在雙重鑲嵌結構之下不存在聚合物層。此會顯著提高精細節距重佈線的密度及佈線能力。根據本發明的其中通孔55及精細節距重佈線56A是使用雙重鑲嵌製程而形成的一些實施例，形成製程包括：蝕刻介電層48及50A以形成通孔開口且蝕刻介電層50A及52A以形成溝渠，使用導電材料來填充所述通孔開口及溝渠，以及執行例如化學機械拋光（Chemical Mechanical Polish，CMP）或機械研磨（mechanical grinding）等平面化以移除所述導電材料的位於介電層之上的部分。
根據本發明的一些實施例，用於形成通孔55及精細節距重佈線56A的導電材料為同質材料。根據本發明的其他實施例，導電材料為包含障壁層及位於所述障壁層之上的含銅材料（其可為銅或銅合金）的複合材料，所述障壁層是由鈦、氮化鈦、鉭、氮化鉭等形成。
圖7說明介電層50B及54B以及蝕刻終止層52B的形成。可自用於形成介電層50A及54A的相同候選材料中選擇介電層50B及54B的材料，且可自用於形成蝕刻終止層52A的相同候選材料中選擇蝕刻終止層52B的材料。
亦在介電層50B、52B及54B中形成精細節距重佈線56B。精細節距重佈線56B包括形成於介電層54B及52B中的金屬線以及位於介電層50B中的通孔。所述形成可包括雙重鑲嵌製程，所述雙重鑲嵌製程包括：在介電層54B及52B中形成溝渠以及在介電層50B中形成通孔開口，填充導電材料，以及接著執行例如機械研磨或化學機械拋光（CMP）等平面化。相似地，精細節距重佈線56B可由同質材料形成，或可由包含障壁層及位於所述障壁層之上的含銅材料的複合材料形成。
圖8說明介電層50C及54C、蝕刻終止層52C以及精細節距重佈線56C的形成。所述形成方法及材料可與下伏的相應層相似，且因此本文中將不再對其予以贅述。此外，根據本發明的一些實施例，可省略蝕刻終止層52A、52B及52C，且可使用時間模式（time-mode）執行用於形成溝渠的對應蝕刻以控制所述溝渠的深度。應知，可形成更多介電層及更多層精細節距重佈線。另外，即便可能跳過蝕刻終止層52A、52B及52C中的一些或所有者，由於其中具有精細節距重佈線的介電層是在不同製程中形成，因此用於形成精細節距重佈線56A、56B及56C的介電層之間亦可存在可分辨的介面而無論該些介電層是由相同的介電材料形成還是由不同的介電材料形成。在後續段落中，為使辨識簡明起見，將介電層50A、52A、54A、50B、52B、54B、50C、52C及54C統稱作及各別地稱作介電層58。亦將精細節距重佈線56A、56B及56C統稱作及各別地稱作精細節距重佈線56。
根據本發明的一些實施例，當形成精細節距重佈線56時，同時形成被動裝置61。因此被動裝置61嵌置於介電層58中。被動裝置61可為電容器、電感器、射頻（Radio-Frequency，RF）傳輸線、變壓器或該些裝置的組合。將被動裝置61電性耦合至後續接合的裝置晶粒。
此外，在形成精細節距重佈線56的同時亦形成堆疊通孔67，堆疊通孔67中的每一者包括多個雙重鑲嵌結構（且可包括或可不包括單一鑲嵌結構），所述多個雙重鑲嵌結構進行堆疊以形成穿透介電層58的連接結構。各堆疊通孔67組合起來具有與如圖10中所示介電層穿孔（TDV）62的功能相似的功能。形成堆疊通孔是有益的，乃因其是使用雙重鑲嵌製程而形成，且因此可具有與雙重鑲嵌結構中的金屬線一樣小的寬度。
亦可使用堆疊通孔67來進行佈線。舉例而言，示意性地說明重佈線56中的部分56D以示出出於佈線目的金屬線可與堆疊通孔67同時形成。堆疊通孔67可因此在一旁電性連接至其他電性組件。可在精細節距重佈線56的金屬層中的任一者中形成佈線金屬線。
參照圖9，蝕刻介電層48及58以形成介電層穿孔（TDV）開口60。相應步驟被示為如圖39中所示製程流程300中的步驟308。將金屬接墊44暴露至介電層穿孔開口60。通孔開口60的俯視圖形狀可為矩形、圓形、六邊形等。
接下來，使用導電材料填充介電層穿孔開口60以形成介電層穿孔62，且所得結構示出於圖10中。相應步驟被示為如圖39中所示製程流程300中的步驟310。根據本發明的一些實施例，介電層穿孔62是由同質導電材料形成，所述同質導電材料可為金屬或金屬合金（包括銅、鋁、鎢等）。根據本發明的替代性實施例，介電層穿孔62具有包含導電障壁層及位於所述障壁層之上的含金屬材料的複合結構，所述導電障壁層是由鈦、氮化鈦、鉭、氮化鉭等形成。根據本發明的一些實施例，形成介電隔離層以包圍介電層穿孔62中的每一者。根據替代性實施例，不形成包圍介電層穿孔62的介電隔離層，且介電層穿孔62實體接觸介電層58。形成介電層穿孔62亦包括將導電材料沈積至介電層穿孔開口60（圖9）中，並執行平面化以移除所沈積材料的位於介電層58之上的過量部分。由於難以形成穿透具有不同蝕刻性質的所述多個介電層58及48的深開口60（圖9），因此介電層穿孔62可能具有較堆疊通孔67大的寬度。介電層穿孔62的電阻是低的。因此，可使用介電層穿孔62來傳導電力，同時由於介電層穿孔62的數目小，因此由介電層穿孔62所佔用的面積微不足道。將堆疊通孔67與介電層穿孔62組合起來使得可增大訊號連接的數目（使用堆疊通孔67），同時可仍使用寬的介電層穿孔62來提供低損耗電力傳輸。根據一些實施例，不形成介電層穿孔62。
圖11說明接墊66及介電層64的形成，且接墊66位於介電層64中。相應步驟被示為如圖39中所示製程流程300中的步驟312。接墊66可由易於形成混合接合的金屬形成。根據本發明的一些實施例，接墊66是由銅或銅合金形成。介電層64可由例如氧化矽形成。接墊66的頂表面與介電層64的頂表面共面。可例如藉由平面化步驟（例如，化學機械拋光或機械研磨步驟）來達成平面性。
根據本發明的一些實施例，不形成接墊66及介電層64。因此，將裝置晶粒68A及68B直接接合至頂部重佈線56（示出為圖8中的56C）且可能將裝置晶粒68A及68B直接接合至介電層54C（圖8）。
在本說明通篇中，將位於層22（或矽晶圓23）之上的各組件組合起來稱作中介層100。與基於矽基底而形成的傳統中介層不同，中介層100是基於介電層58而形成。中介層100中不存在矽基底，且因此將中介層100稱作無矽基底的中介層或無矽中介層。在介電層58中形成堆疊通孔67及介電層穿孔62以取代傳統矽穿孔。由於矽基底是半導電的，因此所述矽基底可能負面地影響形成於其中及形成於其上的電路及連接的效能。舉例而言，矽基底可能造成訊號劣化，而由於介電層中形成有介電層穿孔62及堆疊通孔67，因此在本發明的實施例中可避免此種劣化。
接下來，如圖12中所示，將第一層裝置晶粒68A及68B接合至中介層100。相應步驟被示為如圖39中所示製程流程300中的步驟314。根據本發明的一些實施例，裝置晶粒68A及68B包括邏輯晶粒，所述邏輯晶粒可為中央處理單元（Central Processing Unit，CPU）晶粒、微控制單元（Micro Control Unit，MCU）晶粒、輸入-輸出（input-output，IO）晶粒、基頻（BaseBand，BB）晶粒或應用處理器（Application processor，AP）晶粒。裝置晶粒68A及68B亦可包括記憶體晶粒。裝置晶粒68A及68B分別包括半導體基底70A及70B，半導體基底70A及70B可為矽基底。形成分別穿透半導體基底70A及70B的矽穿孔（Through-Silicon Via，TSV）71A及71B（有時稱作半導體穿孔或穿孔），且使用矽穿孔71A及71B將形成於半導體基底70A及70B的前側（所示底側）上的裝置及金屬線連接至後側。此外，裝置晶粒68A及68B分別包括連接至裝置晶粒68A及68B中的主動裝置及被動裝置的內連結構72A及72B。內連結構72A及72B包括金屬線及通孔（圖中未示出）。
裝置晶粒68A包括位於裝置晶粒68A的所示底表面處的接墊74A及介電層76A。接墊74A的所示底表面與介電層76A的所示底表面共面。裝置晶粒68B包括位於所示底表面處的接墊74B及介電層76B。接墊74B的所示底表面與介電層76B的所示底表面共面。
可藉由混合接合來達成所述接合。舉例而言，藉由金屬-金屬直接接合（metal-to-metal direct bonding）將接墊74A及74B接合至接墊66。根據本發明的一些實施例，金屬-金屬直接接合為銅-銅直接結合（copper-to-copper bonding）。此外，舉例而言，藉由所產生的Si-O-Si鍵將介電層76A及76B接合至介電層64。混合接合可包括預接合（pre-bonding）及退火（anneal），以使得接墊74A（及74B）中的金屬與相應下伏接墊66中的金屬相互擴散。
精細節距重佈線56將接墊74A與接墊74B電性內連且被用來達成裝置晶粒68A與68B之間的訊號通訊。精細節距重佈線56具有小的節距及小的寬度。因此，精細節距重佈線56的密度是高的，且因此可形成足夠的通訊通道來達成裝置晶粒68A與68B之間的直接通訊。另一方面，介電層穿孔62及堆疊通孔67提供自裝置晶粒68A及68B至將接合至中介層100的組件（其可為封裝基底、印刷電路板（Printed Circuit Board，PCB）等）的直接連接。此外，藉由接墊而非藉由焊料接頭來達成接墊74A/74B與66之間的接合，焊料接頭通常較接墊大得多。因此，接合件的水平大小是小的，且可實作更多接合件以提供足夠的通訊通道。
進一步參照圖12，執行後側研磨（backside grinding）以將裝置晶粒68A及68B薄化至例如介於約15微米與約30微米之間的厚度。相應步驟被示為如圖39中所示製程流程300中的步驟316。藉由薄化，鄰近的裝置晶粒68A與68B之間的間隙78的長寬比減小以執行間隙填充。否則，開口78原本的高長寬比會使得間隙填充難以進行。在後側研磨之後，可顯露出矽穿孔71A及71B。作為另一選擇，不在此時顯露出矽穿孔71A及71B。作為替代，可在圖17中所示步驟中顯露出矽穿孔71A及71B。
接下來，如圖13中所示，藉由間隙填充材料80來填充間隙78。相應步驟被示為如圖39中所示製程流程300中的步驟318。根據本發明的一些實施例，間隙填充材料80包括例如氧化矽等氧化物，所述氧化物可使用正矽酸四乙酯（tetraethyl orthosilicate，TEOS）形成。形成方法可包括化學氣相沈積（Chemical Vapor Deposition，CVD）、高密度電漿化學氣相沈積（High-Density Plasma Chemical Vapor Deposition，HDPCVD）等。根據替代性實施例，間隙填充材料80是由例如聚苯並噁唑、聚醯亞胺等聚合物形成。接著執行平面化步驟以移除間隙填充材料80的過量部分，以顯露出裝置晶粒68A及68B的基底70A及70B。所得結構示出於圖14中。
圖15說明介電層穿孔162的形成，介電層穿孔162是藉由在非等向性蝕刻步驟中蝕刻穿過間隙填充材料80以形成通孔開口並使用導電材料填充相應開口而形成。相應步驟被示為如圖39中所示製程流程300中的步驟320。將一些接墊66暴露至通孔開口，其中可使用接墊66作為蝕刻終止層來執行所述蝕刻。介電層穿孔162可具有與介電層穿孔62的結構相似的結構，且可包括障壁層及位於所述障壁層之上的金屬材料。亦可自用於形成介電層穿孔62的相似候選材料中選擇介電層穿孔162的材料。
參照圖16，使基底70A及70B凹陷以形成凹陷部73，且矽穿孔71A及71B的頂端分別略微突出於基底70A及70B的頂表面上方。相應步驟被示為如圖39中所示製程流程300中的步驟322。接著藉由例如氧化矽等介電材料填充凹陷部73以形成介電層75A及75B，且所得結構示出於圖17中。相應步驟被示為如圖39中所示製程流程300中的步驟324。形成製程包括用以沈積毯覆介電層（blanket dielectric layer）的沈積製程，以及執行平面化以移除所述毯覆介電層的高於矽穿孔71A及71B的頂端的部分。
接下來，如圖18中所示，將第二層裝置晶粒168A及168B接合至裝置晶粒68A及68B。相應步驟被示為如圖39中所示製程流程300中的步驟326。根據本發明的一些實施例，裝置晶粒168A及168B包括邏輯晶粒、記憶體晶粒或其組合。裝置晶粒168A及168B分別包括半導體基底170A及170B，半導體基底170A及170B可為例如矽基底等半導體基底。若在裝置晶粒168A及168B之上接合有第三層裝置晶粒，則可在半導體基底170A及170B中形成矽穿孔（圖中未示出）。作為另一選擇，在半導體基底170A及170B中不形成矽穿孔。此外，裝置晶粒168A及168B分別包括連接至裝置晶粒168A及168B中的主動裝置及被動裝置的內連結構172A及172B。內連結構172A及172B包括金屬線及通孔（圖中未示出）。
裝置晶粒168A包括位於裝置晶粒168A的所示底表面處的接墊174A及介電層176A。接墊174A的所示底表面與介電層176A的所示底表面共面。裝置晶粒168B包括位於所示底表面處的接墊174B及介電層176B。接墊174B的所示底表面與介電層176B的所示底表面共面。
所述接合可藉由混合接合來達成。舉例而言，藉由金屬-金屬直接接合將接墊174A及174B直接接合至矽穿孔71A及71B。根據本發明的一些實施例，金屬-金屬直接接合是銅-銅直接接合。此外，舉例而言，藉由所產生的Si-O-Si鍵將介電層176A及176B接合至介電層75A及75B。依據間隙填充材料80的材料，可將介電層176A及176B接合至間隙填充材料80，或可使介電層176A及176B接觸但不接合至（不形成接合件）間隙填充材料80。
接下來，與將裝置晶粒68A及68B薄化相似，可將裝置晶粒168A及168B薄化。如圖19中所示，接著藉由間隙填充材料180來填充鄰近的裝置晶粒168A與168B之間的間隙。相應步驟被示為如圖39中所示製程流程300中的步驟328。根據本發明的一些實施例，使用選自用於形成間隙填充材料80的相同候選方法中的方法來形成間隙填充材料180。間隙填充材料180可包括例如氧化矽等氧化物、氮化矽、聚苯並噁唑、聚醯亞胺等。接著執行平面化步驟以移除間隙填充材料180的過量部分，以使得顯露出裝置晶粒168A及168B的基底170A及170B。
接著例如使用化學氣相沈積、電漿增強型化學氣相沈積（plasma-enhanced CVD，PECVD）、原子層沈積（atomic layer deposition，ALD）等沈積介電層182來作為毯覆層。所得結構亦示出於圖19中。相應步驟被示為如圖39中所示製程流程300中的步驟330。根據本發明的一些實施例，介電層182是由例如氧化矽等氧化物、氮氧化矽等形成。
接下來，參照圖20，藉由蝕刻介電層182以及基底170A及170B來形成溝渠184，以使得溝渠184延伸至介電層182以及基底170A及170B中。依據基底170A及170B的厚度T1，溝渠184的位於基底170A及170B內部的部分的深度D1可大於約1微米，且可介於約2微米與約5微米之間。舉例而言，深度D1可介於厚度T1的約20%與約60%之間。應知，本說明通篇中所陳述的值是實例，且可改變成不同的值。
可以各種圖案來分佈溝渠184。舉例而言，可將溝渠184形成為分立的開口，所述分立的開口可被分配成具有陣列圖案、蜂巢圖案或其他重複圖案。溝渠184的俯視圖形狀可為矩形、圓形、六邊形等。根據替代性實施例，當在圖20中所示結構的俯視圖中觀察時，溝渠184可為在單一方向上具有縱向方向的平行溝渠。亦可將各溝渠184內連以形成柵格。所述柵格可包括彼此平行且均勻地或不均勻地間隔開的第一多個溝渠，彼此平行且均勻地或不均勻地間隔開的第二多個溝渠。第一多個溝渠與第二多個溝渠彼此攔截進而形成柵格，且在俯視圖中所述第一多個溝渠與所述第二多個溝渠可彼此垂直或可不彼此垂直。
如圖21中所示，接著填充溝渠184以形成接墊187。相應步驟亦被示為如圖39中所示製程流程300中的步驟332。應知，儘管將特徵187稱作接墊，然而特徵187可為分立的接墊、經內連的金屬線或金屬柵格。根據本發明的一些實施例，接墊187是由銅或其他適合於混合接合的金屬（因為擴散相對容易）形成。在填充之後，執行平面化以將接墊187的頂表面與介電層182的頂表面平面化。平面化可包括化學機械拋光或機械研磨。
接下來，如圖22中所示，將空白晶粒88接合至裝置晶粒168A及168B。相應步驟被示為如圖39中所示製程流程300中的步驟332。空白晶粒88包括塊狀基底194，塊狀基底194可為矽基底或金屬基底。當由金屬形成時，基底194可由銅、鋁、不銹鋼等形成。當基底194是由矽形成時，在空白晶粒88中不形成主動裝置及被動裝置。空白晶粒88包括兩種功能。首先，空白晶粒88對下伏結構提供機械支撐，乃因裝置晶粒68A、68B、168A及168B已被薄化以使之能夠達成更佳的間隙填充。此外，矽或金屬（基底194的）具有高的導熱係數（thermal conductivity），且因此空白晶粒88可充當散熱器。由於圖22中的結構的形成是晶圓級的，因此亦將與所示空白晶粒88相同的多個空白晶粒接合至與裝置晶粒168A及168B相同的相應下伏裝置晶粒。
在基底194的表面處形成介電層190。例如介電層190可由氧化矽或氮氧化矽形成。此外，在介電層190中形成接墊192，且接墊192的所示底表面與介電層190的所示底表面共面。接墊192的圖案及水平大小可與相應接墊187的圖案及水平大小相同或相似，以使得接墊192與接墊187可以一一對應的方式彼此接合。
可藉由混合接合來達成將空白晶粒88接合至裝置晶粒168A及168B上。舉例而言，使介電層182與190彼此接合且介電層182與190可形成Si-O-Si鍵。藉由金屬-金屬直接接合將接墊192接合至相應接墊187。
有利地，藉由接觸基底170A及170B（且甚至插入至基底170A及170B中），接墊187會提供良好的散熱路徑，以使得在裝置晶粒68A、68B、168A及168B中所產生的熱量可輕易地發散至塊狀基底194中，且因此使用塊狀基底194作為散熱器。
參照圖23，塗覆光阻183並將光阻183圖案化。接著使用圖案化光阻183作為蝕刻罩幕蝕刻介電層182及間隙填充材料180以顯露出中介層100的一些部分。相應步驟被示為如圖39中所示製程流程300中的步驟334。根據本發明的一些實施例，顯露出例如裝置晶粒68B等一些裝置晶粒。亦可暴露出矽穿孔71B及介電層穿孔162中的一些。
圖24說明將晶粒堆疊212接合至第一層結構上。相應步驟被示為如圖39中所示製程流程300中的步驟336。可將晶粒堆疊212接合至介電層穿孔162、裝置晶粒（例如，晶粒68B），或接合至介電層穿孔162與所述裝置晶粒二者。晶粒堆疊212可為包括多個堆疊晶粒214的記憶體堆疊，其中可在晶粒214中形成矽穿孔（圖中未示出）以執行內連。晶粒堆疊212亦可為高頻寬記憶體（High Bandwidth Memory，HBM）立方體。根據本發明的一些實施例，藉由混合接合將晶粒堆疊212接合至下伏結構，其中藉由金屬-金屬直接接合將晶粒堆疊212中的電性連接件216（在一些實施例中為接墊）接合至介電層穿孔162及矽穿孔71B，且藉由氧化物-氧化物接合（oxide-to-oxide bonding）（或熔融接合（fusion bonding））將晶粒堆疊212的介電層218接合至間隙填充材料80（例如，氧化物）及介電層75B。根據替代性實施例，電性連接件216為焊料區，且所述接合為焊料接合。根據又一些替代性實施例，電性連接件216為突出超過晶粒堆疊212的表面介電層218的微凸塊。可藉由金屬-金屬直接接合或焊料接合將微凸塊216接合至介電層穿孔162及矽穿孔71B，且在晶粒堆疊212與間隙填充材料80及介電層75B之間不進行氧化物-氧化物接合。
接下來，將間隙填充材料220（圖25）填充至空白晶粒88與晶粒堆疊212之間的間隙中。間隙填充材料220可由例如氧化矽等氧化物或者例如聚苯並噁唑或聚醯亞胺等聚合物形成。根據其中使用載體20（而非矽晶圓23）的一些實施例，例如藉由在釋放層22上投射例如紫外光或雷射等光來分解釋放層22以自載體20剝離形成於載體20上的結構。所得結構示出於圖26中。自被稱作複合晶圓102（圖26）的上覆結構移除載體20及釋放層22。相應步驟被示為如圖39中所示製程流程300中的步驟338。根據本發明的其中使用矽晶圓23（而非載體晶圓20（圖24））的一些實施例，可藉由機械研磨、化學機械拋光或乾蝕刻（dry etching）來移除矽晶圓23。若需要，則可在移除載體20（或矽晶圓23）之前執行載體交換（carrier swap）以將另一載體222貼合於所示結構之上，且在後續步驟中形成電性連接件期間使用新的載體222來提供機械支撐。
圖26亦說明電性連接件110的形成，電性連接件110可穿透介電層24且連接至重佈線26。根據一些實施例，在介電層24上形成聚合物層（圖中未示出），且亦可使電性連接件110延伸至所述聚合物層中。電性連接件110可為金屬凸塊、焊料凸塊、金屬柱、導線接合件或其他適用的連接件。對複合晶圓102執行晶粒鋸切步驟以將複合晶圓102分隔成多個封裝104。相應步驟亦被示為如圖39中所示製程流程300中的步驟340。各封裝104彼此相同，且封裝104中的每一者可包括兩層裝置晶粒及晶粒堆疊212。所得封裝104示出於圖27A中。
圖27B、圖27C、圖27D及圖27E以及圖28至圖35說明根據本發明一些實施例的封裝及所述封裝的形成過程中的各中間階段的剖視圖。除非另外指明，否則該些實施例中的組件的材料及形成方法與由圖1至圖27A中所示實施例中的相同參考編號所表示的相同組件本質上相同。因此可在對圖1至圖27A中所示實施例的論述中找到有關圖27B、圖27C、圖27D及圖27E以及圖28至圖35中所示組件的形成製程及材料的細節。
圖27B說明根據本發明一些實施例而形成的封裝。除不形成接墊187及192以及介電層190（如圖27A中）以外，該些實施例相似於圖27A中所示實施例。藉由熔融接合將塊狀基底194接合至介電層82，塊狀基底194可為空白矽晶粒。
根據本發明的替代性實施例，塊狀基底194為空白金屬基底。因此，圖27B中的層182可由熱介面材料（Thermal Interface Material，TIM）形成，所述熱介面材料為具有高導熱係數（例如，高於約1瓦/開*米（W/k*m）或高於約5瓦/開*米）的黏合劑。
圖27C說明根據本發明一些實施例而形成的封裝104。除可將具有不同厚度的裝置晶粒放置於相同水平高度（level）處以外，該些實施例相似於圖27A中所示實施例。舉例而言，裝置晶粒68B厚於裝置晶粒68A。因此，裝置晶粒68B包括延伸至與裝置晶粒68A及168A相同的水平高度的部分。應知，儘管將空白基底194示為藉由熔融接合或藉由氧化物/熱介面材料182而接合至裝置晶粒168A及68B，然而可使用圖27A中所示包括接墊187及接墊192的相同接合結構。根據一些實施例，晶粒堆疊212具有與空白晶粒88的一部分齊平的一部分。
圖27D說明根據本發明一些實施例而形成的封裝104。除不使用空白晶粒88（如圖27C中所示）以外，該些實施例相似於圖27C中所示實施例。晶粒堆疊212延伸至間隙填充材料80中而非放置於間隙填充材料80之上。
圖27E說明根據本發明一些實施例而形成的封裝104。除晶粒堆疊212位於包封材料180之上而非延伸至包封材料180中以外，該些實施例相似於圖27A中所示實施例。在包封材料180中形成電性耦合至下伏穿孔162及堆疊通孔67的穿孔262。
圖28至圖32說明根據本發明一些實施例的封裝的形成過程中的各中間階段的剖視圖。相應封裝包括單層裝置晶粒。初始步驟相似於圖1至圖17中所示步驟。所得結構亦示出於圖17中。接下來，參照圖28，可形成或可不形成介電層182及接墊187，且接墊187被示為虛線。
接下來，如圖29中所示，藉由混合接合、熔融接合或藉由熱介面材料進行的黏合來接合空白晶粒88。圖30說明晶粒堆疊212的接合。在圖31中，將空白晶粒88及晶粒堆疊212包封於間隙填充材料220中。可執行平面化以暴露出空白晶粒88。在後續步驟中，自載體20剝離中介層100及上覆結構。圖32說明電性連接件110的形成。接著執行晶粒鋸切以形成封裝104。
圖33至圖35說明根據本發明一些實施例的封裝的形成過程中的各中間階段的剖視圖。除不形成介電層穿孔162及其連接導電特徵（包括堆疊通孔67、介電層穿孔62及重佈線32、36及44中的一些）以外，圖33中所示結構的相應封裝及形成製程相似於圖28至圖32中所示封裝及形成製程。藉由熔融接合來將晶粒堆疊212接合至例如間隙填充材料80等下伏結構。因此，堆疊晶粒212的接墊216接觸間隙填充材料80或形成於其上的介電層。
圖33包括連接至重佈線44A的一些金屬接墊44B。金屬接墊44B及重佈線44A是重佈線44的一部份。金屬接墊44B可形成中空環。圖38說明一些示例性金屬接墊44B及連接重佈線44A。將金屬接墊44B形成為環，藉由介電層46（圖33）來填充所述環內部的開口45。應知，儘管將金屬接墊44B示為重佈線44的部份，然而可在中介層100中的層中的任一者中形成相似的金屬接墊。因此將金屬接墊44B電性連接至中介層100中的其他導電特徵。
接下來，參照圖34，由中介層100的底側形成深介電層穿孔162。形成製程包括蝕刻介電層以形成開口，且接著使用導電材料填充所述開口。形成製程及材料相似於介電層穿孔62的形成。在開口的形成中，使用金屬接墊44B作為蝕刻終止層，以使得藉由開口45（圖38）的大小及形狀來界定所述開口的上部部分。進一步藉由晶粒堆疊212中的金屬接墊216來終止所述開口。因此介電層穿孔162的形成藉由金屬接墊44B而達成自對準。金屬接墊44B與重佈線44A組合起來會藉由介電層穿孔162將裝置晶粒68A及68B電性連接至晶粒堆疊212。如圖35中所示，接著形成電性連接件110，且在晶粒鋸切之後得到封裝104。
圖36說明其中嵌置有封裝104（參照圖27A、圖27B、圖27C、圖27D、圖27E、圖32及圖35）的封裝112。所述封裝包括記憶體立方114，記憶體立方114包括多個堆疊記憶體晶粒（圖中未單獨示出）。將封裝104及記憶體立方114包封於包封材料118中，包封材料118可為模塑化合物。介電層及重佈線（籠統示作116）位於封裝104及記憶體立方114之下且連接至封裝104及記憶體立方114。根據本發明的一些實施例，使用與圖1至圖11中所示材料相似的材料來形成介電層及重佈線116且介電層及重佈線116具有與圖1至圖11中所示結構相似的結構。
圖37說明疊層封裝（Package-on-Package，PoP）結構132，疊層封裝結構132具有接合有頂部封裝140的積體扇出（Integrated Fan-Out，InFO）型封裝138。積體扇出型封裝138亦包括嵌置於其中的封裝104。將封裝104及穿孔134包封於包封材料130中，包封材料130可為模塑化合物。將封裝104接合至介電層及重佈線（其被籠統地稱作146）。亦可使用與圖1至圖11中所示材料相似的材料來形成介電層及重佈線146且介電層及重佈線146具有與圖1至圖11中所示結構相似的結構。
本發明的實施例具有一些有利特徵。藉由使用通常對矽晶圓使用的製程（例如，鑲嵌製程）在中介層中形成精細節距重佈線，可將所述精細節距重佈線形成為薄到足以提供使二或更多個裝置晶粒全部藉由所述精細節距重佈線來進行通訊的能力。形成堆疊通孔以取代介電層穿孔中的一些，以使得晶片面積佔用減少。形成連接至晶粒堆疊的自對準介電層穿孔，其中用於將介電層穿孔對準的金屬接墊亦用於將自對準介電層穿孔連接至封裝中的其他特徵及裝置晶粒。此外，當形成精細節距重佈線時，亦可形成被動裝置。
根據一些實施例，一種方法包括：形成多個介電層；在所述多個介電層中形成多條重佈線；當形成所述多條重佈線時，同時在所述多個介電層中形成堆疊通孔，其中所述堆疊通孔形成穿透所述多個介電層的連續電性連接；在堆疊通孔及所述多個介電層之上形成介電層；在介電層中形成多個接墊；以及藉由混合接合將第一裝置晶粒接合至介電層以及所述多個接墊的第一部分。在實施例中，所述方法包括藉由混合接合將第二裝置晶粒接合至介電層以及所述多個接墊的第二部分，其中所述多條重佈線將第一裝置晶粒連接至所述第二裝置晶粒。在實施例中，所述形成所述多條重佈線包括鑲嵌製程。在實施例中，所述方法包括：蝕刻所述多個介電層以形成開口；以及填充開口，以形成穿透所述多個介電層的介電層穿孔。在實施例中，所述方法包括：將額外裝置晶粒接合至第一裝置晶粒，其中所述額外裝置晶粒被直接接合至所述第一裝置晶粒中的矽穿孔；在額外裝置晶粒的半導體基底之上形成與所述額外裝置晶粒的所述半導體基底接觸的氧化物層；形成延伸至氧化物層中的接墊；以及藉由混合接合將空白晶粒接合至氧化物層以及接墊。在實施例中，所述多個介電層形成於玻璃載體之上；且所述方法更包括：剝離玻璃載體；以及在剝離玻璃載體之後，形成穿透所述多個介電層的自對準介電層穿孔，其中所述自對準介電層穿孔終止於晶粒堆疊的接墊上。在實施例中，所述多個介電層形成於矽晶圓之上，且所述方法更包括自所述多個介電層研磨、拋光或蝕刻所述矽晶圓。
根據一些實施例，一種方法包括：形成多個介電層；在所述多個介電層中的每一者中形成多條重佈線；在所述多個介電層中形成被動裝置；形成穿透所述多個介電層的第一介電層穿孔及第二介電層穿孔；在所述多個介電層之上形成介電層；在介電層中形成多個接墊，所述多個接墊電性耦合至第一介電層穿孔、第二介電層穿孔及所述多條重佈線；以及藉由混合接合將第一裝置晶粒及第二裝置晶粒接合至介電層及所述多個接墊，其中所述第一裝置晶粒及所述第二裝置晶粒藉由所述多條重佈線進行電性內連，且所述第一裝置晶粒及所述第二裝置晶粒分別連接至第一介電層穿孔及第二介電層穿孔。在實施例中，所述多條重佈線是使用鑲嵌製程形成。在實施例中，所述方法包括：在第一裝置晶粒及第二裝置晶粒的相對側上填充間隙填充材料；形成穿透間隙填充材料的第三介電層穿孔；以及將晶粒堆疊接合至第三介電層穿孔。在實施例中，所述多個介電層形成於矽晶圓之上，且所述方法更包括自所述多個介電層移除矽晶圓。在實施例中，所述形成第一介電層穿孔及第二介電層穿孔包括：蝕刻所述多個介電層，以形成第一開口及第二開口；以及使用導電材料填充第一開口及第二開口。在實施例中，所述方法包括：當形成所述多條重佈線時，同時在所述多個介電層中形成堆疊通孔，其中所述堆疊通孔形成穿透所述多個介電層的連續電性連接。在實施例中，所述方法包括：將第三裝置晶粒接合於第一裝置晶粒之上；在第三裝置晶粒之上形成介電層；以及將空白晶粒接合至介電層。
根據一些實施例，一種封裝包括：多個介電層；多條重佈線，位於所述多個介電層中的每一者中；介電層穿孔，穿透所述多個介電層，其中所述介電層穿孔具有穿透所述多個介電層的實質上直的邊緣；堆疊通孔，位於所述多個介電層中，其中所述堆疊通孔彼此電性連接以形成穿透所述多個介電層的連續電性連接；多個接墊，位於介電層穿孔及所述多條重佈線之上且連接至所述介電層穿孔及所述多條重佈線；第一介電層，所述多個接墊位於所述第一介電層中；以及第一裝置晶粒，藉由混合接合而接合至第一介電層以及所述多個接墊的第一部分。在實施例中，所述封裝更包括第二裝置晶粒，所述第二裝置晶粒藉由混合接合而接合至第一介電層以及所述多個接墊的第二部分，其中第一裝置晶粒與所述第二裝置晶粒藉由所述多條重佈線彼此電性耦合。在實施例中，所述封裝更包括：第二裝置晶粒，位於第一裝置晶粒之上且接合至所述第一裝置晶粒；接墊，接觸第二裝置晶粒的半導體基底，其中所述接墊的至少一部分位於所述第二裝置晶粒的所述半導體基底之上；第二介電層，接墊具有至少一部分位於所述第二介電層中；以及塊狀基底，位於第二介電層及接墊之上且接合至所述第二介電層及所述接墊。在實施例中，塊狀基底是由矽形成，且在所述塊狀基底上不形成主動裝置及被動裝置。在實施例中，接墊進一步延伸至第二裝置晶粒的半導體基底中。在實施例中，接墊形成柵格。
根據一些實施例，一種方法包括：在矽晶圓之上形成多個介電層；在所述多個介電層中形成多條重佈線；當形成所述多條重佈線時，同時在所述多個介電層中形成堆疊通孔，其中所述堆疊通孔形成穿透所述多個介電層的連續電性連接；在堆疊通孔及所述多個介電層之上形成介電層；在介電層中形成多個接墊；藉由混合接合將第一裝置晶粒接合至介電層以及所述多個接墊的第一部分；自所述多個介電層移除矽晶圓；以及形成電性耦合至所述多條重佈線的電性連接。在實施例中，所述移除矽晶圓包括對所述矽晶圓執行機械研磨。在實施例中，所述移除矽晶圓包括對所述矽晶圓執行化學機械拋光。在實施例中，所述移除矽晶圓包括對所述矽晶圓執行乾蝕刻。在實施例中，所述方法包括在所述多個介電層中形成被動裝置。在實施例中，所述方法包括：將第一裝置晶粒包封於間隙填充材料中；以及在移除矽晶圓之後，形成穿透所述多個介電層及間隙填充材料的介電層穿孔。
根據一些實施例，一種封裝包括：多個介電層；堆疊通孔，穿透所述多個介電層，其中所述堆疊通孔具有雙重鑲嵌結構，且各所述堆疊通孔進行內連以形成連續電性連接結構；裝置晶粒，位於所述多個介電層之上，其中所述裝置晶粒藉由混合接合而接合至下伏結構，且所述裝置晶粒電性耦合至堆疊晶粒；以及晶粒堆疊，位於裝置晶粒之上且接合至所述裝置晶粒。在實施例中，晶粒堆疊藉由混合接合而接合至裝置晶粒。
根據一些實施例，一種封裝包括：多個介電層；被動裝置，位於所述多個介電層中；介電層穿孔，穿透所述多個介電層；第一裝置晶粒，位於介電層穿孔之上且電性耦合至所述介電層穿孔，其中所述第一裝置晶粒包括半導體基底；介電層，位於第一裝置晶粒之上；接墊，位於介電層中，其中所述接墊穿透介電層且進一步延伸至第一裝置晶粒的半導體基底中；以及晶粒堆疊，位於第一裝置晶粒之上且接合至所述第一裝置晶粒。在實施例中，所述封裝更包括：第二裝置晶粒，位於第一裝置晶粒與介電層穿孔之間。
以上概述了若干實施例的特徵，以使熟習此項技術者可更佳地理解本發明的各個態樣。熟習此項技術者應知，其可容易地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，該些等效構造並不背離本發明的精神及範圍，而且他們可在不背離本發明的精神及範圍的條件下對其作出各種改變、代替及變更。
20‧‧‧載體/載體晶圓
22‧‧‧層/釋放層
23‧‧‧矽晶圓
24‧‧‧層/介電層
26、32、36、40、44A‧‧‧重佈線
28、34、46、48、50A、50B、50C、54A、54B、54C、58、64、75A、75B、76A、76B、176A、176B、190‧‧‧介電層
30、45‧‧‧開口
38、42‧‧‧保護層/介電層
44‧‧‧重佈線/金屬接墊/鋁接墊
44B‧‧‧金屬接墊
52A、52B、52C‧‧‧蝕刻終止層/介電層
55‧‧‧通孔
56‧‧‧重佈線/精細節距重佈線
56A、56B、56C‧‧‧精細節距重佈線
56D‧‧‧部分
60‧‧‧介電層穿孔開口/通孔開口/開口
61‧‧‧被動裝置
62‧‧‧介電層穿孔
66、74A、74B、174A、174B、192‧‧‧接墊
67‧‧‧堆疊通孔
68A‧‧‧裝置晶粒/第一層裝置晶粒
68B‧‧‧晶粒/裝置晶粒/第一層裝置晶粒
70A、70B、170A、170B‧‧‧基底/半導體基底
71A、71B‧‧‧矽穿孔
72A、72B、172A、172B‧‧‧內連結構
73‧‧‧凹陷部
78‧‧‧間隙/開口
80、180‧‧‧間隙填充材料/包封材料
88‧‧‧空白晶粒
100‧‧‧中介層
102‧‧‧複合晶圓
104、112‧‧‧封裝
110‧‧‧電性連接件
114‧‧‧記憶體立方
116、146‧‧‧介電層及重佈線
118、130‧‧‧包封材料
132‧‧‧疊層封裝結構
134、262‧‧‧穿孔
138‧‧‧積體扇出型封裝
140‧‧‧頂部封裝
162‧‧‧穿孔/介電層穿孔
168A、168B‧‧‧裝置晶粒/第二層裝置晶粒
182‧‧‧層/介電層/氧化物/熱介面材料
183‧‧‧光阻
184‧‧‧溝渠
187‧‧‧接墊/特徵
194‧‧‧基底/塊狀基底/空白基底
212‧‧‧晶粒堆疊/堆疊晶粒
214‧‧‧晶粒/堆疊晶粒
216‧‧‧電性連接件/微凸塊/接墊/金屬接墊
218‧‧‧介電層/表面介電層
220‧‧‧間隙填充材料
222‧‧‧載體
300‧‧‧製程流程
302、304、306、308、310、312、314、316、318、320、322、324、326、328、330、332、334、336、338‧‧‧步驟
D1‧‧‧深度
T1‧‧‧厚度
結合附圖閱讀以下詳細說明，會最佳地理解本發明的各個態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1至圖27A說明根據一些實施例的無矽基底（無矽）的封裝的形成過程中的各中間階段的剖視圖。
圖27B、圖27C、圖27D及圖27E說明根據一些實施例的無矽封裝的剖視圖。
圖28至圖32說明根據一些實施例的無矽封裝的形成過程中的各中間階段的剖視圖。
圖33至圖35說明根據一些實施例的無矽封裝的形成過程中的各中間階段的剖視圖。
圖36及圖37說明嵌置有根據一些實施例的無矽封裝的封裝的剖視圖。
圖38說明用於根據一些實施例的無矽封裝中的自對準金屬接墊（self-align metal pad）的一些俯視圖。
圖39說明形成根據一些實施例的封裝的製程流程。

Claims (20)

  1. 一種方法，包括： 形成多個介電層； 在所述多個介電層中形成多條重佈線； 在所述多個介電層中形成堆疊通孔，其中所述堆疊通孔形成穿透所述多個介電層的連續電性連接； 在所述堆疊通孔及所述多個介電層之上形成介電層； 在所述介電層中形成多個接墊；以及 藉由混合接合將第一裝置晶粒接合至所述介電層以及所述多個接墊的第一部分。
  2. 如申請專利範圍第1項所述的方法，更包括藉由混合接合將第二裝置晶粒接合至所述介電層以及所述多個接墊的第二部分，其中所述多條重佈線將所述第一裝置晶粒連接至所述第二裝置晶粒。
  3. 如申請專利範圍第1項所述的方法，其中所述形成所述多條重佈線包括鑲嵌製程。
  4. 如申請專利範圍第1項所述的方法，更包括： 蝕刻所述多個介電層以形成開口；以及 填充所述開口，以形成穿透所述多個介電層的介電層穿孔。
  5. 如申請專利範圍第1項所述的方法，更包括： 將額外裝置晶粒接合至所述第一裝置晶粒，其中所述額外裝置晶粒被直接接合至所述第一裝置晶粒中的矽穿孔； 在所述額外裝置晶粒的半導體基底之上形成與所述額外裝置晶粒的所述半導體基底接觸的氧化物層； 形成延伸至所述氧化物層中的接墊；以及 藉由混合接合將空白晶粒接合至所述氧化物層以及所述接墊。
  6. 如申請專利範圍第1項所述的方法，其中所述多個介電層形成於玻璃載體之上；且所述方法更包括： 剝離所述玻璃載體；以及 在剝離所述玻璃載體之後，形成穿透所述多個介電層的自對準介電層穿孔，其中所述自對準介電層穿孔終止於晶粒堆疊的接墊上。
  7. 如申請專利範圍第1項所述的方法，其中所述多個介電層形成於矽晶圓之上，且所述方法更包括自所述多個介電層研磨、拋光或蝕刻所述矽晶圓。
  8. 一種方法，包括： 形成多個介電層； 在所述多個介電層中的每一者中形成多條重佈線； 在所述多個介電層中形成被動裝置； 形成穿透所述多個介電層的第一介電層穿孔及第二介電層穿孔； 在所述多個介電層之上形成介電層； 在所述介電層中形成多個接墊，所述多個接墊電性耦合至所述第一介電層穿孔、所述第二介電層穿孔及所述多條重佈線；以及 藉由混合接合將第一裝置晶粒及第二裝置晶粒接合至所述介電層及所述多個接墊，其中所述第一裝置晶粒及所述第二裝置晶粒藉由所述多條重佈線進行電性內連，且所述第一裝置晶粒及所述第二裝置晶粒分別連接至所述第一介電層穿孔及所述第二介電層穿孔。
  9. 如申請專利範圍第8項所述的方法，其中所述多條重佈線是使用鑲嵌製程形成。
  10. 如申請專利範圍第8項所述的方法，更包括： 在所述第一裝置晶粒及所述第二裝置晶粒的相對側上填充間隙填充材料； 形成穿透所述間隙填充材料的第三介電層穿孔；以及 將晶粒堆疊接合至所述第三介電層穿孔。
  11. 如申請專利範圍第8項所述的方法，其中所述多個介電層形成於矽晶圓之上，且所述方法更包括自所述多個介電層移除所述矽晶圓。
  12. 如申請專利範圍第8項所述的方法，其中所述形成所述第一介電層穿孔及所述第二介電層穿孔包括： 蝕刻所述多個介電層，以形成第一開口及第二開口；以及 使用導電材料填充所述第一開口及所述第二開口。
  13. 如申請專利範圍第8項所述的方法，更包括： 當形成所述多條重佈線時，同時在所述多個介電層中形成堆疊通孔，其中所述堆疊通孔形成穿透所述多個介電層的連續電性連接。
  14. 如申請專利範圍第8項所述的方法，更包括： 將第三裝置晶粒接合於所述第一裝置晶粒之上； 在所述第三裝置晶粒之上形成介電層；以及 將空白晶粒接合至所述介電層。
  15. 一種封裝，包括： 多個介電層； 多條重佈線，位於所述多個介電層中的每一者中； 介電層穿孔，穿透所述多個介電層，其中所述介電層穿孔具有穿透所述多個介電層的實質上直的邊緣； 堆疊通孔，位於所述多個介電層中，其中所述堆疊通孔彼此電性連接以形成穿透所述多個介電層的連續電性連接； 多個接墊，位於所述介電層穿孔及所述多條重佈線之上且連接至所述介電層穿孔及所述多條重佈線； 第一介電層，所述多個接墊位於所述第一介電層中；以及 第一裝置晶粒，接合至所述第一介電層以及所述多個接墊的第一部分。
  16. 如申請專利範圍第15項所述的封裝，更包括第二裝置晶粒，所述第二裝置晶粒藉由混合接合而接合至所述第一介電層以及所述多個接墊的第二部分，其中所述第一裝置晶粒與所述第二裝置晶粒藉由所述多條重佈線彼此電性耦合。
  17. 如申請專利範圍第15項所述的封裝，更包括： 第二裝置晶粒，位於所述第一裝置晶粒之上且接合至所述第一裝置晶粒； 接墊，接觸所述第二裝置晶粒的半導體基底，其中所述接墊的至少一部分位於所述第二裝置晶粒的所述半導體基底之上； 第二介電層，所述接墊具有至少一部分位於所述第二介電層中；以及 塊狀基底，位於所述第二介電層及所述接墊之上且接合至所述第二介電層及所述接墊。
  18. 如申請專利範圍第17項所述的封裝，其中所述塊狀基底是由矽形成，且在所述塊狀基底上不形成主動裝置及被動裝置。
  19. 如申請專利範圍第17項所述的封裝，其中所述接墊進一步延伸至所述第二裝置晶粒的所述半導體基底中。
  20. 如申請專利範圍第17項所述的封裝，其中所述接墊形成柵格。
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