TWI715370B - 封裝及其形成方法 - Google Patents

封裝及其形成方法 Download PDF

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TWI715370B
TWI715370B TW108147471A TW108147471A TWI715370B TW I715370 B TWI715370 B TW I715370B TW 108147471 A TW108147471 A TW 108147471A TW 108147471 A TW108147471 A TW 108147471A TW I715370 B TWI715370 B TW I715370B
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package
die
ipd
passive component
independent passive
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TW108147471A
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TW202114135A (zh
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賴昱嘉
謝政傑
余振華
劉重希
蔡豪益
郭庭豪
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台灣積體電路製造股份有限公司
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Abstract

一種封裝及其形成方法，所述封裝包括第一封裝及第二 封裝，第二封裝位於第一封裝上方且接合至第一封裝。第一封裝包含第一元件晶粒及第一包封體，第一包封體將第一元件晶粒包封在其中。第二封裝包含獨立被動元件(IPD)晶粒及第二包封體，第二包封體將IPD晶粒包封在其中。所述封裝更包含位於第二封裝上方且接合至第二封裝的電力模組。

Description

封裝及其形成方法
本發明實施例是有關於一種封裝及其形成方法。
随着更多的元件晶粒封裝在同一封裝中以形成具有更多功能的系統，積體電路的封裝已變得愈發複雜。獨立被動元件(Independent Passive Device；IPD)(其為離散元件)常常用於封裝中。IPD常常接合至積體扇出型(Integrated Fan-Out；InFO)封裝件的前側，且與電力模組形成於同一層級下。因此，IPD佔據原本可以用於形成電力模組的面積，迫使用於接合電力模組的焊料球形成得更小。此亦導致焊料球中的電流密度不利地增大。
本發明實施例提供一種封裝，其包括第一封裝、第二封裝以及電力模組。第一封裝包括第一元件晶粒以及第一包封體。第一包封體將第一元件晶粒包封於其中。第二封裝位於第一封裝上方且接合至第一封裝。第二封裝包括獨立被動元件晶粒以及第二包封體。第二包封體將獨立被動元件晶粒包封於其中。電力模組位於第二封裝上方且接合至第二封裝。
本發明實施例提供一種封裝，其包括獨立被動元件封裝以及電力模組。獨立被動元件封裝包括獨立被動元件模組、第一模製化合物、第一多個重佈線以及第二多個重佈線。獨立被動元件模組包括位於其中的多個獨立被動元件晶粒，其中多個獨立被動元件晶粒中的每一者包括被動元件。第一模製化合物將獨立被動元件模組模製於其中。第一多個重佈線位於第一模製化合物之下，其中第一多個重佈線內連多個獨立被動元件晶粒中的被動元件作為額外被動元件。第二多個重佈線位於第一模製化合物的與第一多個重佈線相對的側上，其中第一多個重佈線及第二多個重佈線電性內連。電力模組位於獨立被動元件封裝上方且接合至獨立被動元件封裝。
本發明實施例提供一種封裝的形成方法，其包括形成第一封裝、將第一封裝接合至第二封裝以及將電力模組接合至第一封裝，其中電力模組及第二封裝位於第一封裝的相對側上。形成第一封裝包括：將獨立被動元件晶粒及金屬支柱包封在模製化合物中；以及在模製化合物的相對側上形成第一重佈線以連接至獨立被動元件晶粒及金屬支柱。
20:獨立被動元件(IPD)晶粒
21:基底
22:被動元件
24、88:內連線結構
26:端子
28、102:保護層
30、76:載體
32、78:離型膜
34:介電緩衝層
36:背側重佈線(RDL)
38、50、60、62、86A、86B:介電層
40、74:開口
42:金屬支柱
44、52A:通孔
46、82:晶粒貼附膜
48、85:包封體
52、64:重佈線
52B:金屬跡線
65、135:重建構晶圓
65':IPD封裝
66、90:電連接件
68、94:載帶
70、96、108:框架
80、80A、80B:元件晶粒
80-1:邏輯運算晶粒
80-2:記憶體晶粒
80-3:IO晶粒
84A、84B:RDL
92:積體扇出型(InFO)封裝
100:IPD晶圓
104:背側研磨帶
106:研磨機
110:切割帶
120、120A、120B、120C:IPD模組
130:貫穿孔
132、139:底填充料
134:電力模組
136:焊料區域
138:螺桿
140:螺栓
142:撐臂
142A:水平條帶
142B:豎直條帶
144:熱界面材料
146:冷板
148:連接件
200:製程流程
202、204、206、208、210、212、214、216、218、220、222、224、226、228、230、232、234、236、238:製程
結合隨附圖式閱讀以下實施方式時會最佳地理解本揭露內容的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。事實上，可出於論述明晰起見而任意地增加或縮減各種特徵的尺寸。
圖1至圖6示出根據一些實施例的在獨立被動元件(IPD) 模組的形成中的中間階段的橫截面視圖。
圖7至圖12示出根據一些實施例的靈活(flexible)IPD設計。
圖13至圖21示出根據一些實施例的在包含IPD的積體扇出型(InFO)封裝件的封裝中的中間階段的橫截面視圖。
圖22示出根據一些實施例的包含IPD元件的InFO封裝的平面視圖。
圖23至圖28示出根據一些實施例的在包括包含IPD的InFO封裝的系統的形成中的中間階段的橫截面視圖。
圖29及圖30示出根據一些實施例的包含IPD的InFO封裝的橫截面視圖。
圖31示出根據一些實施例的包括包含IPD的InFO封裝的重建構晶圓的平面視圖。
圖32示出根據一些實施例的重建構晶圓的實例佈局的平面視圖。
圖33示出根據一些實施例的包括包含IPD的InFO封裝的系統中的一些組件的示意性橫截面視圖。
圖34示出根據一些實施例的用於形成封裝的製程流程。
以下揭露內容提供用以實施本發明的不同特徵的許多不同實施例或實例。以下描述組件及配置的特定實例以簡化本揭露內容。當然，此等組件及配置僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或第二特徵上形成可包含第一特徵與第二特徵直接接觸地形成的實施例，且亦 可包含額外特徵可在第一特徵與第二特徵之間形成，使得第一特徵與第二特徵可不直接接觸的實施例。另外，本揭露內容可在各種實例中重複附圖標號及/或字母。此重複是出於簡單及清楚的目的，且自身並不指示所論述的各種實施例及/或組態之間的關係。
另外，為易於描述，可在本文中使用諸如「在......之下」、「在......下方」、「下部」、「上覆」、「上部」以及類似者的空間相對術語以描述如圖式中所示出的一個部件或特徵與另一部件或特徵的關係。除圖式中所描繪的定向之外，空間相對術語還意欲涵蓋元件在使用或操作中的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
根據一些實施例，提供一種包含獨立被動元件(IPD)的封裝及其形成方法。根據一些實施例示出封裝的形成中的中間階段。論述一些實施例的一些變型。本文中所論述的實施例將提供使得能夠製成或使用本揭露內容的主題的實例，且所屬技術領域中具有通常知識者將易於理解在保持在不同實施例的所設想範圍內的情況下可進行的修改。貫穿各視圖及示出性實施例，相同的附圖標號用以指明相同部件。儘管方法實施例可論述為以特定次序執行，但其他方法實施例可以任何邏輯次序執行。根據本揭露內容的一些實施例，IPD封裝(其為積體扇出型(InFO)封裝件)藉由將IPD包封在其中來形成。隨後，IPD封裝接合至在其中具有元件晶粒的元件封裝，且可接合在電力模組與元件封裝之間。
圖1至圖6示出根據一些實施例的在IPD模組的形成中的中間階段的橫截面視圖。參看圖1，形成IPD晶圓100。將相應 製程示出為圖34中所繪示的製程流程200中的製程202。IPD晶圓100包含位於其中的多個IPD晶粒20(圖5)，其中圖6示意性地示出根據一些實施例的實例IPD晶粒20的橫截面視圖。如圖6中所繪示，IPD晶粒20在其中包含被動元件22。被動元件22可為電容器、電阻器、電感器或類似者。被動元件22可形成於基底21上方，根據一些實施例，所述基底21可為諸如矽基底的半導體基底。內連線結構24形成在基底21上方。一個IPD晶粒20可在其中包含單一類型的被動元件(諸如電容器、電阻器、電感器或類似者)，且可在其中不含主動元件。被動元件22可形成於基底21中或基底21上方，諸如內連線結構24中，所述內連線結構24包含多個介電層。被動元件22連接至端子(terminal)26，所述端子26可為金屬柱、金屬接墊或類似者。根據一些實施例，IPD晶粒20僅具有兩個端子26，每個端子26各自連接至被動元件22的端部。根據一些實施例，IPD晶粒20具有多於兩個的端子。保護層28被形成為覆蓋端子26。根據本揭露內容的一些實施例，保護層28由諸如聚醯亞胺、聚苯并噁唑(polybenzoxazole；PBO)或類似者的聚合物形成。
參看圖2，IPD晶圓100經由保護層102黏附至背側研磨(Backside Grinding；BG)帶104，保護層102用於保護晶圓100的前表面。然後，如圖3中所繪示，執行背側研磨以使IPD晶圓100變薄，其中示意性地示出研磨機106。在後續製程中，如圖4中所繪示，將晶粒貼附膜(Die-attach film；DAF，未繪示，參看圖16中的DAF 46)黏附至IPD晶圓100的背表面，並將切割帶110黏附至DAF。切割帶110及BG帶104位於晶圓100的 相對側上。框架108用於支撐切割帶110。隨後移除BG帶104及保護層102。
參看圖5，將IPD晶圓100鋸切(單體化)成多個IPD模組120(例如，如圖7中所示的IPD模組120)。將相應製程示出為圖34中所繪示的製程流程200中的製程204。多個IPD模組120中的每一者可包含單個IPD晶粒或多個IPD晶粒。當IPD模組120包含未彼此鋸切開的多個IPD晶粒20時，多個IPD晶粒20中的層連續地連接以形成連續層。舉例而言，多個IPD晶粒20的半導體基底21彼此連續地連接以形成連續的半導體基底。多個IPD晶粒20的內連線結構24亦彼此連續地連接以形成連續的內連線結構。
圖7示出IPD晶圓100的一部分，所述IPD晶圓100包含配置為陣列的多個IPD晶粒20。包含不同數目的IPD晶粒20的IPD模組120可鋸切自IPD晶圓100。如一些實例，IPD模組120A包含IPD晶粒20的4×5陣列。IPD模組120B包含晶粒20的2×2陣列。IPD模組120C包含單個IPD晶粒20。IPD模組120中的IPD晶粒的數目取決於各種因素，諸如元件晶粒80的大小(圖28)及IPD模組120的預期電容、電阻或電感值或類似者。舉例而言，若需要更大電容，則IPD模組120可包含更多IPD晶粒20(電容器晶粒)，所述IPD晶粒可並聯連接以達成預期電容。圖8示出根據一些實施例的實例IPD模組120。
當IPD模組120包含多個IPD晶粒20時，本揭露內容的實施例提供連接IPD晶粒20的靈活性。舉例而言，圖9示出用於將8個IPD晶粒20連接成四個IPD元件的實例連接方案，其可進 一步連接成更少的IPD元件，或四個IPD元件中的每一者可在最終結構中單獨地使用。在如圖9中所繪示的實例中，兩個相鄰IPD晶粒20的端子26經由重佈線(或接墊)52連接。因此，當IPD晶粒20為電容器晶粒時，電容藉由使用重佈線52的連接至少加倍。
根據一些實施例，如圖8中所繪示，IPD晶粒20可具有方形的俯視形狀。根據替代實施例，IPD晶粒20可具有細長形狀，如圖12中所繪示。根據一些實施例，IPD晶粒20的長度及寬度處於約50微米至約2,000微米的範圍。
圖13至圖21示出根據本揭露內容的一些實施例的在包含IPD模組120的InFO封裝的形成中的中間階段的橫截面視圖。對應製程亦示意性地反映於圖34中所繪示的製程流程200中。
參看圖13，提供載體30，並將離型膜(release film)32塗佈於載體30上。將相應製程示出為圖34中所繪示的製程流程200中的製程206。載體30由透明材料形成，且可為玻璃載體、陶瓷載體、有機載體或類似者。離型膜32與載體30的頂部表面實體接觸。離型膜32可由光熱轉換(Light-To-Heat-Conversion；LTHC)塗佈材料形成。離型膜32可經由塗佈而塗覆至載體30上。根據本揭露內容的一些實施例，LTHC塗佈材料能夠在光/輻射(諸如，雷射光束)的熱量下分解，且因此可使載體30自形成於其上的結構脫離。
根據一些實施例，在LTHC塗佈材料32上形成介電緩衝層34。介電緩衝層34可由聚合物(諸如聚苯並惡唑(PBO)、聚醯亞胺、苯並環丁烯(benzocyclobutene；BCB))或另一可適用的 聚合物形成。
參看圖14，形成背側重佈線(redistribution layer；RDL)(及金屬接墊)36。將相應製程示出為圖34中所繪示的製程流程200中的製程208。形成製程可包含沈積金屬晶種層(未繪示)、在金屬晶種層上方形成鍍覆罩幕(諸如光阻，未繪示)並對鍍覆罩幕圖案化，以及在金屬晶種層上方鍍覆諸如銅及/或鋁的金屬材料。金屬晶種層可包含鈦層及位於鈦層上方的銅層，且可使用例如物理氣相沈積(Physical Vapor Deposition；PVD)形成。金屬晶種層及經鍍覆金屬材料可由相同材料或不同材料形成。隨後移除經圖案化鍍覆罩幕，接著蝕刻先前被經圖案化鍍覆罩幕所覆蓋的金屬晶種層的部分。金屬晶種層及經鍍覆金屬材料的剩餘部分為RDL 36。隨後在RDL 36上形成介電層38。將相應製程示出為圖34中所繪示的製程流程200中的製程210。介電層38可由PBO、聚醯亞胺或類似者形成。隨後執行圖案化製程以形成開口40，經由所述開口顯露金屬接墊/RDL 36。圖案化製程可包含曝光製程及顯影製程。
圖15示出金屬支柱42的形成。將相應製程示出為圖34中所繪示的製程流程200中的製程212。在本文中，金屬支柱42替代地被稱為穿孔42，這是由於金屬支柱42穿透隨後施配的包封材料。金屬支柱42的形成可類似於RDL 36的形成，不同之處在於金屬支柱42的經鍍覆金屬材料的高度明顯大於RDL 36的高度。當金屬支柱42形成時，通孔44同時形成在開口40中(圖14)。
圖16示出IPD模組120的置放/貼附。將相應製程示出為圖34中所繪示的製程流程200中的製程214。IPD模組120經 由DAF 46貼附至介電層38。可存在置放於介電層38上的多個IPD模組120。IPD模組120可彼此相同，或可彼此不同，例如包含與彼此數目不同的IPD晶粒20。示意性地示出IPD模組120中的被動元件22。IPD模組120可具有相同類型的被動元件或不同類型的元件。舉例而言，IPD模組120中的一者可包含電容器晶粒，而IPD模組120中的另一者可包含電阻器晶粒。
然後，如圖17中所繪示，包封體48經施配以包封IPD模組120及金屬支柱42，且隨後被固化。將相應製程示出為圖34中所繪示的製程流程200中的製程216。包封體48填充相鄰金屬支柱42之間的空隙及金屬支柱42與IPD模組120之間的空隙。包封體48可包含模製化合物、模製底填充料、環氧樹脂及/或樹脂。包封體48經施配至一水平面，使得包封體48的頂部表面高於端子26及介電層28的頂端。當由模製化合物或模製底填充料形成時，包封體48可包含基質材料以及基質材料中的填料顆粒(未繪示)，所述基質材料可為聚合物、樹脂、環氧樹脂或類似者。填料顆粒可為SiO2、Al2O3、矽石(silica)或類似者的介電質顆粒，且可具有球形形狀。另外，球形填料顆粒可具有相同或不同的直徑。
在施配包封體48之後，亦如圖17中所繪示，執行平坦化製程(諸如化學機械研磨(Chemical Mechanical Polish；CMP)製程或機械研磨製程)以將包封體48及介電層28平坦化，直至金屬支柱42及端子26全部暴露。歸因於平坦化製程，金屬支柱42的頂端與端子26的頂部表面實質上齊平(共面)，且與包封體48的頂部表面實質上共面。金屬支柱42在下文中替代地稱作穿孔 42，此是由於金屬支柱42穿透包封體48。
圖18示出前側重佈線結構的形成，所述前側重佈線結構包含多個RDL及相應的介電層。將相應製程示出為圖34中所繪示的製程流程200中的製程218。形成製程簡要地論述如下。參看圖18，首先形成介電層50。根據本揭露內容的一些實施例，介電層50由諸如PBO、聚醯亞胺或類似者的聚合物形成。形成製程包含以可流動的形式塗佈介電層50、固化介電層50以及執行曝光製程及顯影製程以使介電層50圖案化。根據本揭露內容的替代實施例，介電層50由諸如氮化矽、氧化矽或類似者的無機介電材料形成。形成方法可包含化學氣相沈積(Chemical Vapor Deposition；CVD)、原子層沈積(Atomic Layer Deposition；ALD)、電漿增強型化學氣相沈積(Plasma-Enhanced Chemical Vapor Deposition；PECVD)或其他可適用的沈積方法。開口(被RDL 52佔據)隨後例如經由蝕刻製程而形成。穿孔42及端子26經由經圖案化的介電層50中的開口暴露。
然後，形成RDL 52。RDL 52包含形成在介電層50中以連接至端子26及穿孔42的通孔52A，以及位於介電層50上方的金屬跡線(金屬線)52B。根據本揭露內容的一些實施例，RDL 52使用鍍覆製程形成，所述鍍覆製程可與用於形成RDL 36的製程基本上相同。儘管示出一層RDL 52，但可形成更多層RDL。隨後形成介電層60及介電層62以及RDL 64。介電層60及介電層62可由選自與介電層50相同的候選材料群組的材料形成。舉例而言，介電層60及介電層62可使用PBO、聚醯亞胺或BCB形成。RDL 64亦可包含一些凸塊下金屬(Under-Bump Metallurgy；UBM)， 所述凸塊下金屬亦標示為RDL 64。根據本揭露內容的一些實施例，RDL 64由鎳、銅、鈦或其多層形成。根據一些實施例，RDL 64包含鈦層及位於鈦層上方的銅層。儘管示出RDL 52及RDL 64的兩個層，但前側RDL可包含單個RDL層或多於兩個RDL層。
圖18亦示出根據一些實施例的電連接件66的形成。將相應製程示出為圖34中所繪示的製程流程200中的製程220。電連接件66的形成可包含將焊料球置放於RDL 64的經暴露部分上且接著回焊焊料球，且因此電連接件66是焊料區域。根據本揭露的替代實施例，電連接件66的形成包含執行鍍覆步驟以在RDL 64上方形成焊料層且接著回焊焊料層。電連接件66亦可包含非焊料金屬柱，或金屬柱以及非焊料金屬柱上方的焊料蓋，其亦可經由鍍覆形成。在本文中，包含介電層34及上覆結構的結構組合地被稱為複合封裝65或重建構晶圓65。
然後，參看圖19，將重建構晶圓65置放於載帶68上，所述載帶貼附至框架70。根據本揭露內容的一些實施例，電連接件66與載帶68接觸。然後，將光束投射在LTHC塗佈材料32上，且光束穿透透明載體30。根據本揭露內容的一些實施例，光束為雷射光束，所述雷射光束掃描整個LTHC塗佈材料32。
歸因於曝光(諸如雷射掃描)，載體30可自LTHC塗佈材料32移起，且因此將重建構晶圓65自載體30剝離(卸下)。將相應製程示出為圖34中所繪示的製程流程200中的製程222。在曝光期間，LTHC塗佈材料32回應於藉由光束所引入的熱量而分解，從而允許載體30自重建構晶圓65分離。LTHC塗佈材料32的殘餘物隨後例如經由電漿清潔步驟移除。所得重建構晶圓65 在圖20中繪示。
在剝離載體30之後，介電緩衝層34暴露為重建構晶圓65的表面部分。參看圖20，將介電緩衝層34圖案化以形成開口74，RDL 36的金屬接墊被所述開口74顯露出來。將相應製程示出為圖34中所繪示的製程流程200中的製程224。根據本揭露的一些實施例，圖案化經由雷射鑽孔執行。在後續製程中，將載帶68及框架70自重建構晶圓65移除，且所得重建構晶圓65在圖21中示出。重建構晶圓65隨後被單體化為多個相同的IPD封裝65'，所述IPD封裝65'在圖21及圖22中示出。將相應製程示出為圖34中所繪示的製程流程200中的製程226。
圖22示出IPD封裝65'的平面視圖(俯視圖或底視圖)。亦示出多個電連接件66。根據本揭露的一些實施例，IPD封裝65'的邊角被切割。此可為隨後插入的螺桿138(圖28)提供空間。
圖23至圖28示出根據本揭露內容的一些實施例的在其中包含IPD封裝的系統封裝的形成中的中間階段的橫截面視圖。對應製程亦示意性地反映於圖34中所繪示的製程流程200中。
參看圖23，提供載體76及離型膜78。載體76及離型膜78可分別由與載體30及離型膜32(圖14)的材料基本上相同的材料形成。另外，載體76可具有圓形俯視形狀。在離型膜78上方可能有或可能沒有額外緩衝層(未繪示)，且額外緩衝層(當形成時)可由PBO、聚醯亞胺、BCB或類似者形成。
元件晶粒80(包含元件晶粒80A及元件晶粒80B)隨後例如經由DAF 82置放在離型膜78上方。元件晶粒80可在相應半導體基底的前表面(面向上的表面)處包含半導體基底及積體電 路元件(諸如主動元件，其包含例如晶體管(未繪示))。根據本揭露內容的一些實施例，元件晶粒80可包含邏輯晶粒，所述邏輯晶粒可包含中央處理單元(Central Processing Unit；CPU)晶粒、圖形處理單元(Graphic Processing Unit；GPU)晶粒、行動應用程式晶粒、微型控制單元(Micro Control Unit；MCU)晶粒、基頻(BaseBand；BB)晶粒、應用程式處理器(Application processor；AP)晶粒、場可程式化閘陣列(Field-Programmable Gate Array；FPGA)晶粒、特殊應用積體電路(Application-Specific Integrated Circuit；ASIC)晶粒或類似者。元件晶粒80亦可包含記憶體晶粒、輸入-輸出(input-output；IO)晶粒或類似者。記憶體晶粒可包含高頻寬記憶體(High-Bandwidth Memory；HBM)堆疊、混合記憶體立方體(Hybrid Memory Cube；HMC)、動態隨機存取記憶體(Dynamic Random Access Memory；DRAM)晶粒、靜態隨機存取記憶體(Static Random Access Memory；SRAM)晶粒或類似者。
根據一些實施例，元件晶粒80A及元件晶粒80B表示具有不同大小、不同結構及/或不同功能的多個元件晶粒，且可包含前述類型的晶粒中的一些或所有晶粒的任何組合。舉例而言，圖32示出置放於同一載體76上的元件晶粒80的實例佈局。根據本揭露內容的一些實施例，如圖32中所繪示，元件晶粒80可包含邏輯運算晶粒80-1、記憶體晶粒80-2以及輸入-輸出(IO)晶粒80-3。根據一些實施例，所有元件晶粒80用於諸如人工智慧(Artificial Intelligence；AI)系統的同一系統中，且元件晶粒80不分成不同封裝件，且將全部保留在同一最終封裝件中。根據替代實施例，所有所示出的元件晶粒80-1、元件晶粒80-2以及元件 晶粒80-3可表示充當系統的元件晶粒組，且可存在置放於同一載體76上的多個相同系統。根據此等實施例，多個系統將在後續單體化製程中分離。
返回參看圖23，將元件晶粒80包封在包封體85中。將相應製程示出為圖34中所繪示的製程流程200中的製程228。根據一些實施例，包封體85包含模製化合物、模製底填充料、環氧樹脂、樹脂或類似者。當由模製化合物或模製底填充料形成時，包封體85可包含基質材料以及基質材料中的填料顆粒(未繪示)，所述基質材料可為聚合物、樹脂、環氧樹脂或類似者。執行平坦化製程直至元件晶粒80的電連接件(諸如金屬柱或金屬接墊，未繪示)暴露出來。在後續製程中，在包封體85及元件晶粒80上方形成內連線結構88。將相應製程示出為圖34中所繪示的製程流程200中的製程230。根據本揭露內容的一些實施例，內連線結構88包含介電層86A及位於介電層86A上方的介電層86B。介電層86B中的每一者可比介電層86A中的任一者更厚。介電層86A可由諸如PBO、聚醯亞胺或類似者的感光性材料形成。介電層86B可由諸如模製化合物或模製底填充料的非感光性材料形成。
在介電層86A中形成RDL 84A，且在介電層86B中形成RDL 84B。根據一些實施例，RDL 84B比RDL 84A更厚及/或更寬，且可用於遠程電佈線(long-range electrical routing)，而RDL 84A可用於短程電佈線(short-range electrical routing)。在內連線結構88的表面上形成電連接件90。電連接件90以及RDL 84A及RDL 84B電連接至元件晶粒80。在本文中，位於離型膜78上方的結構稱為InFO封裝92，所述InFO封裝亦為重建構晶圓。
在後續製程中，載體76自InFO封裝92剝離。根據本揭露內容的一些實施例，例如使用CMP製程或機械研磨製程移除DAF 82(圖23)。根據替代實施例，DAF 82未移除，且貼附至載帶94。如圖24中所繪示，InFO封裝92隨後貼附至載帶94，所述載帶進一步貼附至框架96。根據一些實施例，形成貫穿孔130以穿透InFO封裝92。將相應製程示出為圖34中所繪示的製程流程200中的製程232。貫穿孔130可經由雷射鑽孔、鑽頭鑽孔或類似者形成。圖31示出貫穿孔130的實例分佈。元件晶粒80(及隨後接合的IPD封裝65'可被分配為陣列，且貫穿孔130可位於元件晶粒80及IPD封裝65'的邊角處。根據其他實施例，未形成貫穿孔。
參看圖25，IPD封裝65'例如經由焊料區域66及(可能經由)形成為電連接件90的部分的一些預焊料接合至InFO封裝92。將相應製程示出為圖34中所繪示的製程流程200中的製程234。隨後將底填充料132施配在IPD封裝65'與InFO封裝92之間以保護焊料區域66，如圖26中所示出。在後續製程中，可執行清潔製程，且可蝕刻RDL 36中的鈦層(若形成)以顯露RDL 36的銅部分。然後，亦如圖26中所繪示，將底填充料132施配至IPD封裝65'與InFO封裝92之間的空隙中。
圖27示出例如經由焊料區域136將電力模組134接合至IPD封裝65'。將相應製程示出為圖34中所繪示的製程流程200中的製程236。隨後將底填充料139施配在電力模組134與IPD封裝65'之間以保護焊料區域136。在本文中，位於載帶94上方的組件統稱為複合封裝135或重建構晶圓135。根據本揭露內容的一 些實施例，電力模組134包含用於調整電力的脈寬調變(Pulse Width Modulation；PWM)電路。電力模組134例如經由穿孔42及內連線結構88將經調整的電力提供至下伏的元件晶粒80。電力模組134亦連接至IPD模組120中的被動元件，用於電力管理及電力儲存。
圖28示出經由熱界面材料(Thermal Interface Material；TIM)144(其為具有良好熱導率的黏著劑)在重建構晶圓135上安設冷板(散熱板)146。將相應製程示出為圖34中所繪示的製程流程200中的製程238。經由螺桿138及螺栓140安設撐臂(brace)142。相應製程亦示出為圖34中所繪示的製程流程200中的製程238。根據一些實施例，撐臂142的底部表面與IPD封裝65'的頂部表面接觸。撐臂142可由諸如銅、不鏽鋼或類似者的金屬材料形成。在如圖31中所繪示的俯視圖中，撐臂142可被形成為包含聯結在一起的多個水平條帶(strip)142A及多個豎直條帶142B的柵(grid)。撐臂142、螺桿138以及螺栓140組合起來用於固定重建構晶圓135及冷板146，且用於減小重建構晶圓135的翹曲。
圖29示出根據替代實施例的重建構晶圓135。此等實施例類似於如圖28中所繪示的實施例，但未安設撐臂、螺桿以及螺栓。圖30示出根據另外替代實施例的重建構晶圓135。此等實施例類似於如圖29中所繪示的實施例，但未安設冷板。
圖10及圖11示出根據一些實施例的IPD模組120及焊料區域136(參看圖27)的示意性俯視圖。觀測到，由於焊料區域136(亦參看圖28、圖29或圖30)位於IPD模組120上方， 而端子26位於IPD模組120的底部側上，對端子26的連接(圖10及圖11)為靈活的，且所述連接(諸如RDL 52)可置放於任何期望的位置中，而不干擾焊料區域136的位置。IPD模組120中的IPD晶粒20可因此經由RDL52以任何組合分組，以經由並連連接、串連連接或其組合具有期望數目的被動元件(諸如電容器)。
圖32示出實例重建構晶圓135的平面視圖。根據本揭露內容的一些實施例，邏輯運算晶粒80-1、IPD封裝65'以及電力模組134可經堆疊以形成多個組，且所述堆疊的多個組被配置為具有多個列及多個行的陣列。記憶體晶粒80-2及IO晶粒80-3可形成於陣列的周邊區域中。連接件148用於將重建構晶圓135連接至外部元件以用於訊號及/或電力連接目的。根據一些實施例，連接件148可為插座。
圖33示意性地示出邏輯運算晶粒80-1、記憶體晶粒80-2、IO晶粒80-3、IPD封裝65'、電力模組134以及連接件148的豎直相對位置。其繪示連接件148形成在內連線結構88上方，所述內連線結構位於元件晶粒80上方。
在以上所示出實施例中，根據本揭露內容的一些實施例論述一些製程及特徵以形成三維(three-dimensional；3D)封裝。亦可包含其他特性及製程。舉例而言，可包含測試結構以輔助對3D封裝或3DIC元件的驗證測試。測試結構可包含例如形成於重佈線層中或基底上的測試接墊，從而允許測試3D封裝或3DIC、使用探針及/或探針卡以及類似者。驗證測試可對中間結構以及最終結構執行。另外，本文中所揭露的結構及方法可結合併有對已 知良好晶粒的中間驗證的測試方法使用，以提高產率及降低成本。
本揭露內容的實施例具有一些有利特徵。習知地，IPD晶粒接合至InFO封裝的前側，且與電力模組在同一層級。因此，IPD晶粒與電連接件(諸如焊料區域)爭奪晶片面積。此可迫使焊料區域的尺寸不期望地減小，且迫使焊料區域中的電流密度不期望地增大。另外，需要電源的側向佈線以側向地內連IPD晶粒及電力模組，且側向佈線路徑長，此造成效能降低。在本揭露內容的實施例中，IPD晶粒包封在IPD封裝中，使得所述IPD晶粒可直接堆疊在電力模組之下，且因此節省面積。另外，由於IPD晶粒與電力模組之間的豎直距離短，故電源的佈線路徑減小。此外，IPD晶粒的連接為靈活的，使得靈活地形成具有期望電容、電阻及/或電感值的被動元件。
根據本揭露內容的一些實施例，一種封裝包括：第一封裝，包括：第一元件晶粒；以及第一包封體，將第一元件晶粒包封在其中；第二封裝，位於第一封裝上方且接合至第一封裝，第二封裝包括：IPD晶粒；以及第二包封體，將IPD晶粒包封在其中；以及電力模組，位於第二封裝上方且接合至第二封裝。在實施例中，IPD晶粒為包括與IPD晶粒相同的多個IPD晶粒的IPD模組的一部分。在實施例中，IPD晶粒及多個IPD晶粒電性內連。在實施例中，IPD晶粒包括被動元件，且IPD晶粒不含主動元件及額外被動元件。在實施例中，第二封裝及電力模組形成封裝堆疊，且封裝更包括多個封裝堆疊，所述多個封裝堆疊與位於第一封裝上方且接合至第一封裝的封裝堆疊相同。在實施例中，封裝堆疊及多個封裝堆疊組合地形成陣列。在實施例中，封裝更包括： 金屬撐臂，位於第二封裝上方且與第二封裝接觸；螺桿，穿透第一封裝；以及螺栓，其中螺栓及螺桿將金屬撐臂固定在第一封裝上。在實施例中，封裝更包括：第一多個焊料區域，將第一封裝接合至第二封裝；以及第二多個焊料區域，將第二封裝接合至電力模組。在實施例中，封裝更包括：第二元件晶粒，包封在第一包封體中，其中第一元件晶粒為包括與第一元件晶粒相同的多個元件晶粒的晶粒陣列的一部分，且第二元件晶粒位於晶粒陣列的周邊區域中。
根據本揭露內容的一些實施例，一種封裝包括：IPD封裝，其包括：IPD晶粒模組，IPD晶粒模組包括位於其中的多個IPD晶粒，其中多個IPD晶粒中的每一者包括被動元件；第一模製化合物，將IPD模組模製於其中；第一多個重佈線，位於第一模製化合物之下，其中第一多個重佈線內連多個IPD晶粒中的被動元件作為額外被動元件；以及第二多個重佈線，位於第一模製化合物的與第一多個重佈線相對的側上，其中第一多個重佈線及第二多個重佈線電性內連；以及電力模組，位於IPD封裝上方且接合至IPD封裝。在實施例中，封裝更包括：額外封裝，位於IPD封裝之下且接合至IPD封裝，其中額外封裝包括：邏輯運算晶粒、記憶體晶粒以及IO晶粒；以及第二模製化合物，將邏輯運算晶粒、記憶體晶粒以及IO晶粒模製於其中。在實施例中，封裝更包括在第一模製化合物中的穿孔，其中穿孔電性內連第一多個重佈線及第二多個重佈線。
根據本揭露內容的一些實施例，一種方法包括：形成第一封裝，包括：將IPD晶粒及金屬支柱包封在模製化合物中；以 及在模製化合物的相對側上形成第一重佈線以連接至IPD晶粒及金屬支柱；將第一封裝接合至第二封裝；以及將電力模組接合至第一封裝，其中電力模組及第二封裝位於第一封裝的相對側上。在實施例中，包封IPD晶粒包括包封包括多個相同IPD晶粒的第一IPD模組，其中多個相同IPD晶粒未彼此鋸切開。在實施例中，第一重佈線內連多個相同IPD晶粒。在實施例中，在包封中，將與第一IPD模組相同的第二IPD模組包封在模製化合物中，且第一IPD模組藉由模製化合物與第二IPD模組分隔開。在實施例中，所述方法更包括將冷板或連接件貼附至第二封裝，其中當貼附冷板或連接件時，第一IPD模組及第二IPD模組兩者位於模製化合物的同一連續區域中。在實施例中，IPD晶粒包括單個電容器，且在其中不含主動元件及其他被動元件。在實施例中，所述方法更包括形成第二封裝，其包括：將第一元件晶粒包封在包封體中；以及形成電連接至第一元件晶粒的第二重佈線。在實施例中，所述方法更包括：將第二元件晶粒及第三元件晶粒包封在包封體中，其中第一元件晶粒包括邏輯運算晶粒，第二元件晶粒包括記憶體晶粒，且第三元件晶粒包括IO晶粒。
前文概述若干實施例的特徵，以使得所屬技術領域中具有通常知識者可更佳地理解本揭露內容的態樣。所屬技術領域中具有通常知識者應理解，其可易於使用本揭露內容作為設計或修改用於實現本文中所引入之實施例的相同目的及/或達成相同優點的其他方法及結構之基礎。所屬技術領域中具有通常知識者亦應認識到，此類等效構造並不脫離本揭露內容的精神及範圍，且所屬技術領域中具有通常知識者可在不脫離本揭露內容的精神及範 圍的情況下在本文中作出各種改變、替代以及更改。
26:端子
28:保護層
42:金屬支柱
48、85:包封體
65':IPD封裝
66:電連接件
80、80A、80B:元件晶粒
86A、86B:介電層
88:內連線結構
92:InFO封裝
120:IPD模組
132、139:底填充料
134:電力模組
135:重建構晶圓
136:焊料區域
144:熱界面材料
146:冷板

Claims (9)

  1. 一種封裝，包括：第一封裝，包括：第一元件晶粒；以及第一包封體，將所述第一元件晶粒包封於其中；第二封裝，位於所述第一封裝上方且接合至所述第一封裝，所述第二封裝包括：獨立被動元件晶粒；以及第二包封體，將所述獨立被動元件晶粒包封於其中；以及電力模組，位於所述第二封裝上方且接合至所述第二封裝，其中所述第二封裝及所述電力模組形成封裝堆疊，且所述封裝更包括多個封裝堆疊，所述多個封裝堆疊與位於所述第一封裝上方且接合至所述第一封裝的所述封裝堆疊相同。
  2. 如申請專利範圍第1項所述的封裝，其中所述獨立被動元件晶粒包括被動元件，且所述獨立被動元件晶粒不包含主動元件及額外被動元件。
  3. 如申請專利範圍第1項所述的封裝，更包括：金屬撐臂，位於所述第二封裝上方且與所述第二封裝接觸；螺桿，穿透所述第一封裝；以及螺栓，其中所述螺栓及所述螺桿將所述金屬撐臂固定在所述第一封裝上。
  4. 一種封裝，包括：獨立被動元件封裝，包括：獨立被動元件模組，包括位於其中的多個獨立被動元件 晶粒，其中所述多個獨立被動元件晶粒中的每一者包括被動元件；第一模製化合物，將所述獨立被動元件模組模製於其中；第一多個重佈線，位於所述第一模製化合物之下，其中所述第一多個重佈線內連所述多個獨立被動元件晶粒中的被動元件作為額外被動元件；以及第二多個重佈線，位於所述第一模製化合物的與所述第一多個重佈線相對的側上，其中所述第一多個重佈線及所述第二多個重佈線電性內連；以及電力模組，位於所述獨立被動元件封裝上方且接合至所述獨立被動元件封裝。
  5. 如申請專利範圍第4項所述的封裝，更包括：額外封裝，位於所述獨立被動元件封裝之下且接合至所述獨立被動元件封裝，其中所述額外封裝包括：邏輯運算晶粒、記憶體晶粒以及輸入-輸出晶粒；以及第二模製化合物，將所述邏輯運算晶粒、所述記憶體晶粒以及所述輸入-輸出晶粒模製於其中。
  6. 如申請專利範圍第4項所述的封裝，更包括位於所述第一模製化合物中的穿孔，其中所述穿孔電性內連所述第一多個重佈線及所述第二多個重佈線。
  7. 一種封裝的形成方法，包括：形成第一封裝，包括：將獨立被動元件晶粒及金屬支柱包封在模製化合物中；以及在所述模製化合物的相對側上形成第一重佈線以連接至 所述獨立被動元件晶粒及所述金屬支柱；將所述第一封裝接合至第二封裝；以及將電力模組接合至所述第一封裝，其中所述電力模組及所述第二封裝位於所述第一封裝的相對側上。
  8. 如申請專利範圍第7項所述的封裝的形成方法，其中包封所述獨立被動元件晶粒包括包封包括多個相同獨立被動元件晶粒的第一獨立被動元件模組，其中所述多個相同獨立被動元件晶粒未彼此鋸切開。
  9. 如申請專利範圍第7項所述的封裝的形成方法，更包括形成所述第二封裝，包括：將第一元件晶粒包封在包封體中；以及形成電連接至所述第一元件晶粒的第二重佈線。
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