CN112466834B - 半导体封装结构及其制造方法 - Google Patents
半导体封装结构及其制造方法 Download PDFInfo
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- CN112466834B CN112466834B CN202010046269.9A CN202010046269A CN112466834B CN 112466834 B CN112466834 B CN 112466834B CN 202010046269 A CN202010046269 A CN 202010046269A CN 112466834 B CN112466834 B CN 112466834B
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- conductive bumps
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Abstract
本发明提供一种半导体封装结构,其包括线路基板、至少一芯片、密封体、多个导电连接件、重布线路层以及多个导电端子。线路基板具有第一表面以及相对于第一表面的第二表面。至少一芯片具有主动面以及相对于主动面的背面。至少一芯片以背面配置于线路基板。密封体包封至少一芯片。多个导电连接件围绕至少一芯片。重布线路层位于密封体上。多个导电端子位于第二表面上。至少一芯片经由重布线路层、多个导电连接件以及线路基板电性连接至多个导电端子。另提供一种半导体封装结构的制造方法。
Description
技术领域
本发明涉及一种封装结构及其制造方法,尤其涉及一种半导体封装结构及其制造方法。
背景技术
为了使电子产品设计实现轻、薄、短且小,半导体封装技术正持续进步,以尝试开发出体积较小、重量较轻、整合度较高且更具市场竞争力的产品。因此,对于本领域技术人员来说,如何在使半导体封装结构具有高输入/输出(Input/output,I/O)连接的数目的同时降低制造成本已成为挑战。
发明内容
本发明提供一种半导体封装结构及其制造方法,其可以在使半导体封装结构具有高输入/输出连接的数目且提升电性能力和/或效能的同时降低制造成本。
本发明的提供一种半导体封装结构,其包括线路基板、至少一芯片、密封体、多个导电连接件、重布线路层以及多个导电端子。线路基板具有第一表面以及相对于第一表面的第二表面。至少一芯片具有主动面以及相对于主动面的背面。至少一芯片以背面配置于线路基板。密封体包封至少一芯片。多个导电连接件围绕至少一芯片。重布线路层位于密封体上。多个导电端子位于第二表面上。至少一芯片经由重布线路层、多个导电连接件以及线路基板电性连接至多个导电端子。
本发明提供一种半导体封装结构的制造方法,其至少包括以下步骤。提供线路基板。线路基板具有第一表面以及相对于第一表面的第二表面。配置至少一芯片于第一表面上。至少一芯片具有主动面以及相对于主动面的背面,且至少一芯片以背面配置于线路基板。形成密封体包封至少一芯片。形成多个导电连接件围绕至少一芯片。形成重布线路层于密封体上。形成多个导电端子于第二表面上。至少一芯片经由重布线路层、多个导电连接件以及线路基板电性连接至多个导电端子。
基于上述,在半导体封装结构中,由于线路基板不为暂时载板,因此,于半导体封装结构的制造过程中可以省去使用暂时载板的成本且不用额外进行移除暂时载板的制程,进而可以降低半导体封装结构的制造成本。此外,由于至少一芯片经由重布线路层、多个导电连接件以及线路基板电性连接至多个导电端子,因此可以通过重布线路层、多个导电连接件以及线路基板使半导体封装结构具有高输入/输出连接的数目,且将至少一芯片信号进行重新配置扩展出去,进而可以提升半导体封装结构的电性能力和/或效能。
附图说明
图1A至图1D是依据本发明一实施例的半导体封装结构的部分制造方法的部分剖面示意图;
图2A至图2E是依据本发明另一实施例的半导体封装结构的部分制造方法的部分剖面示意图;
图3A至图3D是依据本发明又一实施例的半导体封装结构的部分制造方法的部分剖面示意图。
附图标号说明:
100、200、300:半导体封装结构
110、210:线路基板
110a、210a:第一表面
110b、210b:第二表面
112:导电线路
120:第一芯片
120a、130a:主动面
120b、130b:背面
122、1221、1222、132、1321、1322:导电凸块
130:第二芯片
140、240、340:密封体
140a、240a、340a:顶面
150、250、350:重布线路层
151、251、351:底介电层
152、252、352:导电图案
160、260、360:导电连接件
170:导电端子
C:凹穴
CS:底面
P1、P2:间距
具体实施方式
本文所使用的方向用语(例如,上、下、右、左、前、后、顶部、底部)仅作为参看所绘附图使用且不意欲暗示绝对定向。
除非另有明确说明,否则本文所述任何方法绝不意欲被解释为要求按特定顺序执行其步骤。
参照本实施例的附图以更全面地阐述本发明。然而,本发明亦可以各种不同的形式体现,而不应限于本文中所述的实施例。附图中的层或区域的厚度、尺寸或大小会为了清楚起见而放大。相同或相似的参考号码表示相同或相似的元件,以下段落将不再一一赘述。
图1A至图1D是依据本发明一实施例的半导体封装结构的部分制造方法的部分剖面示意图。
请参照图1A,本实施例中,半导体封装结构100的制造过程可以包括以下步骤。首先,提供线路基板110。线路基板110具有第一表面110a以及相对于第一表面110a的第二表面110b,其中线路基板110可以具有导电线路112,以用于后续的电性连接。导电线路112可以是由多层线路层及连接多层线路层之间的通孔(through hole)或者是盲孔(blindhole)所组成,但本发明不限于此。
在一些实施例中,线路基板110可以为印刷电路板(Printed Circuit Board,PCB)、有机基板(organic substrate)或高密度内连线基板。然而,本发明不限制线路基板110的种类,只要线路基板110中具有适宜的导电线路112可以提供后续制程中所需的电性连接,皆属于本发明的保护范围。
值得说明的是,线路基板110为永久基板(Permanent substrate),换句话说,线路基板110非暂时载板,因此,于半导体封装结构100的制造过程中可以省去使用暂时载板的成本且不用额外进行移除暂时载板的制程,进而可以降低半导体封装结构100的制造成本。
请继续参照图1A,于线路基板110的第一表面110a配置至少一芯片,其中在图1A至图1D中示意地示出出二个芯片(第一芯片120与第二芯片130),但本发明不限于此。在本实施例中,第一芯片120与第二芯片130可以具有不同功能。举例而言,第一芯片120可以是系统单芯片(system on chip,SoC),而第二芯片130可以是动态随机存取存储器(DRAM),但本发明不限于此,在其他实施例中,第一芯片120与第二芯片130可以是其他适宜的半导体芯片。
第一芯片120与第二芯片130的尺寸可以不同。举例而言,第一芯片120的尺寸可以是大于第二芯片130的尺寸。第一芯片120于第一表面110a上的正投影面积可以大于第二芯片130于第一表面110a上的正投影面积,但本发明不限于此。
至少一芯片具有主动面以及相对于主动面的背面。举例而言,在本实施例中,第一芯片120具有主动面120a以及相对于主动面120a的背面120b,而第二芯片130具有主动面130a以及相对于主动面130a的背面130b。如图1A所示,第一芯片120与第二芯片130以面朝上的方式配置于线路基板110。换句话说,第一芯片120以背面120b配置于线路基板110;而第二芯片130以背面130b配置于线路基板110。
至少一芯片可以经由黏着层附接在线路基板110上,使得黏着层夹于至少一芯片与线路基板110之间。举例而言,在本实施例中,可以于第一芯片120的背面120b与第二芯片130的背面130b配置黏着层。黏着层可以增强芯片与线路基板110之间的黏着力,以防止芯片位移。黏着层可以包括由树脂构成的晶粒黏着膜(die attach film,DAF)。然而,本发明不限于此。在一些替代实施例中,可以使用其他具有黏着特性的材料来作为黏着层的材料。
请继续参照图1A,至少一芯片中的每一者的主动面上可以具有多个导电凸块。举例而言,在本实施例中,第一芯片120的主动面120a上可以具有多个导电凸块122;而第二芯片130的主动面130a上可以具有多个导电凸块132。
多个导电凸块可以包括多个第一导电凸块与多个第二导电凸块,多个第一导电凸块的间距P1小于多个第二导电凸块的间距P2。举例而言,如图1A所示,在本实施例中,多个导电凸块122可以包括多个第一导电凸块1221与多个第二导电凸块1222;而多个导电凸块132可以包括多个第一导电凸块1321与多个第二导电凸块1322。多个第一导电凸块1221的间距P1小于多个第二导电凸块1222的间距P2;而多个第一导电凸块1321的间距P1小于多个第二导电凸块1322的间距P2。在此,间距P1为两相邻的第一导电凸块(两相邻的第一导电凸块1221或两相邻的第一导电凸块1321)的中心点之间的距离;而间距P2为两相邻的第二导电凸块(两相邻的第二导电凸块1222或两相邻的第二导电凸块1322)的中心点之间的距离。
由于多个第一导电凸块的间距P1小于多个第二导电凸块的间距P2,因此,具有微间距的多个第一导电凸块可以作为信号输入/输出接点,而具有粗间距的多个第二导电凸块可以作为电源/接地接点,但本发明不限于此。
请参照图1B,于线路基板110的第一表面110a上形成密封体140,以包封至少一芯片。举例而言,在本实施例中,密封体140可以包封第一芯片120与第二芯片130。在一实施例中,密封体140可以是通过模塑制程(molding process)所形成的模塑化合物(moldingcompound)。在一实施例中,密封体140例如可以由环氧树脂或其他适宜的树脂等绝缘材料所形成的,但本发明不限于此。
在本实施例中,形成密封体140的步骤可以如下。首先,于线路基板110的第一表面110a上形成密封材料,以完全覆盖第一芯片120与第二芯片130。接着,对密封材料进行平坦化制程,直到露出第一芯片120的主动面120a上的导电凸块122以及第二芯片130的主动面130a上的导电凸块132,使导电凸块122的顶面、导电凸块132的顶面与密封体140的顶面140a实质上共面(coplanar)。平坦化制程可以包括化学机械研磨制程(chemical-mechanical polishing,CMP)、机械研磨制程(mechanical grinding process)、蚀刻制程或其他适宜的制程。
请参照图1C,于密封体140上形成重布线路层150。在本实施例中,重布线路层150可以包括多个介电层以及部分嵌入于介电层中的多个图案化导电层,其中介电层可以包括邻近密封体140的底介电层151,而图案化导电层可以包括邻近密封体140的多个导电图案152。
在本实施例中,形成重布线路层150的步骤可以如下。首先,于密封体140上形成介电材料。接着,于介电材料中形成多个第一开口与多个第二开口,其中多个第一开口暴露出至少一芯片(第一芯片120以及第二芯片130)中的每一者的主动面上的多个导电凸块,而多个第二开口暴露出部分线路基板110的第一表面110a。然后,于多个第一开口与多个第二开口中形成导电材料,且导电材料至少覆盖多个第二开口的侧壁与底面,其中至少覆盖多个第二开口的侧壁与底面导电材料用以形成多个导电连接件160(于图1C与图1D中示意性示出二个)。
多个导电连接件160围绕至少一芯片。举例而言,在本实施例中,多个导电连接件160围绕第一芯片120以及第二芯片130。多个导电连接件160可以贯穿密封体140,且多个导电连接件160可以是由重布线路层150延伸至线路基板110。密封体140可以填充于多个导电连接件160之间。多个导电连接件160可以为模塑通孔(through molding via;TMV)。
至少一芯片通过多个导电凸块与重布线路层150电性连接。举例而言,在本实施例中,第一芯片120可以通过导电凸块122与重布线路层150电性连接,而第二芯片130可以通过导电凸块132与重布线路层150电性连接。
在本实施例中,第一芯片120与第二芯片130上的多个第一导电凸块通过重布线路层150电性连接。第一芯片120与第二芯片130上的多个第二导电凸块通过重布线路层150以及多个导电连接件160与线路基板110电性连接。举例而言,第一芯片120上的多个第一导电凸块1221与第二芯片130上的多个第一导电凸块1321可以通过重布线路层150电性连接。第一芯片120上的多个第二导电凸块1222与第二芯片130上的多个第二导电凸块1322可以通过重布线路层150以及多个导电连接件160与线路基板110电性连接。
由于多个第一导电凸块的间距P1小于多个第二导电凸块的间距P2,且第一芯片120与第二芯片130上的多个第一导电凸块可以通过重布线路层150电性连接,而第一芯片上与第二芯片上的多个第二导电凸块可以通过重布线路层150以及多个导电连接件160与线路基板110电性连接,因此,在本发明的半导体封装结构100中具有不同间距的第一导电凸块与第二导电凸块可以有效地利用线路基板110来达成两芯片之间不同的电性连接需求(信号输入/输出及电源/接地)。举例而言,具有微间距的多个第一导电凸块通过重布线路层150电性连接以传递信号,而具有粗间距的多个第二导电凸块通过重布线路层150以及多个导电连接件160与线路基板110电性连接以连接电源/接地。如此,可以减少重布线路层150所需形成的层数,进而可以降低半导体封装结构100的制造成本。此外,上述配置方式也可以进一步使半导体封装结构100具有更好的信号完整性/电源完整性(signalintegrity/power integrity,SI/PI)性能。
在一实施例中,重布线路层150的细线距(line-and-space,L/S)可以是小于5微米/5微米。在一实施例中,重布线路层150的细线距例如是小于2微米/2微米,因此可以具有较佳的信号传输能力。
应说明的是,附图中的线路布局(layout)仅为示意用,因此,于附图中,线路基板110以及重布线路层150中部分未连接的线路实际上也可以视线路设计需求经由导通孔或其他方向的导电件进行电性连接。
请参照图1D,于线路基板110的第二表面110b上形成多个导电端子170。至少一芯片(第一芯片120以及第二芯片130)经由重布线路层150、多个导电连接件160以及线路基板110电性连接至多个导电端子170,因此可以通过重布线路层150、多个导电连接件160以及线路基板110使半导体封装结构100具有高输入/输出连接的数目,且将至少一芯片(第一芯片120以及第二芯片130)信号进行重新配置扩展出去,进而可以提升半导体封装结构100的电性能力和/或效能。
导电端子170可以通过植球制程(ball placement process)以和/或回焊制程(reflow process)来形成。导电端子170可以是焊球等的导电凸块。然而,本发明不限于此。在一些替代的实施例中,基于设计需求,导电端子170可以具有其他可能的形式以及形状。
经过上述制程后即可大致上完成本实施例的半导体封装结构100的制作。半导体封装结构100包括线路基板110、至少一芯片(第一芯片120以及第二芯片130)、密封体140、多个导电连接件160、重布线路层150以及多个导电端子170。线路基板具有第一表面110a以及相对于第一表面110a的第二表面110b。至少一芯片(第一芯片120以及第二芯片130)具有主动面以及相对于主动面的背面。至少一芯片(第一芯片120以及第二芯片130)以背面配置于线路基板110。密封体140包封至少一芯片(第一芯片120以及第二芯片130)。多个导电连接件160围绕至少一芯片(第一芯片120以及第二芯片130)。重布线路层150位于密封体140上。多个导电端子170位于第二表面110b上。至少一芯片(第一芯片120以及第二芯片130)经由重布线路层150、多个导电连接件160以及线路基板110电性连接至多个导电端子170。
在半导体封装结构100中,由于线路基板110不为暂时载板,因此,于半导体封装结构100的制造过程中可以省去使用暂时载板的成本且不用额外进行移除暂时载板的制程,进而可以降低半导体封装结构100的制造成本。
此外,由于至少一芯片(第一芯片120以及第二芯片130)经由重布线路层150、多个导电连接件160以及线路基板110电性连接至多个导电端子170,因此可以通过重布线路层150、多个导电连接件160以及线路基板110使半导体封装结构100具有高输入/输出连接的数目,且将至少一芯片(第一芯片120以及第二芯片130)信号进行重新配置扩展出去,进而可以提升半导体封装结构100的电性能力和/或效能。
在此必须说明的是,以下实施例沿用上述实施例的元件标号与部分内容,其中采用相同或近似的标号来表示相同或近似的元件,并且省略了相同技术内容的说明,关于省略部分的说明可参考前述实施例,下述实施例不再重复赘述。
图2A至图2E是依据本发明另一实施例的半导体封装结构的部分制造方法的部分剖面示意图。在本实施例中,半导体封装结构200与半导体封装结构100相似,其类似的构件以相同的标号表示,且具有类似的功能、材质或形成方式,并省略描述。
请参照图2A,提供线路基板210,其中线路基板210具有第一表面210a以及相对于第一表面210a的第二表面210b。在本实施例中,线路基板210类似于线路基板110,线路基板210与线路基板110的差异在于:线路基板210中可以包括预先形成的多个导电连接件260。换句话说,多个导电连接件260可以是线路基板210的一部分。线路基板210可以具有凹穴C,以形成后续可配置芯片的空间。在一实施例中,多个导电连接件260的顶面可以是与第一表面210a实质上共面。凹穴C的底面CS可以是位于线路基板210的第一表面210a与第二表面210b之间。
请参照图2B,于线路基板110的凹穴C配置至少一芯片。举例而言,在本实施例中,第一芯片120以背面120b配置于线路基板210的凹穴C;而第二芯片130以背面130b配置于线路基板210的凹穴C。第一芯片120与第二芯片130可以经由黏着层附接在凹穴C的底面CS上,使第一芯片120以及第二芯片130埋设于线路基板110中。在一实施例中,凹穴C的高度可以大于至少一芯片中的每一者的高度。
请参照图2C,于凹穴C中形成密封体240,以包封至少一芯片(第一芯片120以及第二芯片130)。在本实施例中,密封体240类似于密封体140,密封体240与密封体140的差异在于形成密封体240的步骤可以如下。首先,于凹穴C与线路基板210的第一表面210a上形成密封材料,以完全覆盖第一芯片120、第二芯片130以及多个导电连接件260。接着,对密封材料进行平坦化制程,直到露出第一芯片120的主动面120a上的导电凸块122、第二芯片130的主动面130a上的导电凸块132以及多个导电连接件260,使第一芯片120的主动面120a上的导电凸块122的顶面、第二芯片130的主动面130a上的导电凸块132的顶面、多个导电连接件260的顶面、密封体240的顶面240a与线路基板210的第一表面210a实质上共面。
请参照图2D,于密封体240上形成重布线路层250。重布线路层250类似于重布线路层150,重布线路层250与重布线路层150的差异在于:多个导电连接件260不延伸至重布线路层250,部分线路基板210可以与重布线路层250直接接触,其中重布线路层250可以包括邻近密封体240的底介电层251,而图案化导电层可以包括邻近密封体240的多个导电图案252。
在本实施例中,形成重布线路层250的步骤可以如下。首先,于密封体240以及线路基板210的第一表面210a上形成介电材料。接着,于介电材料中形成多个第三开口,以暴露出至少一芯片(第一芯片120以及第二芯片130)中的每一者的主动面上的多个导电凸块以及多个导电连接件260的顶面。然后,于多个第三开口中形成导电材料。重布线路层250可以与至少一芯片(第一芯片120以及第二芯片130)中的每一者的主动面上的多个导电凸块以及多个导电连接件260直接接触。
请参照图2E,于线路基板110的第二表面110b上形成多个导电端子170。至少一芯片(第一芯片120以及第二芯片130)经由重布线路层250、多个导电连接件260以及线路基板210电性连接至多个导电端子170,因此可以通过重布线路层250、多个导电连接件260以及线路基板210使半导体封装结构200具有高输入/输出连接的数目,且将至少一芯片(第一芯片120以及第二芯片130)信号进行重新配置扩展出去,进而可以提升半导体封装结构200的电性能力和/或效能。
经过上述制程后即可大致上完成本实施例的半导体封装结构200的制作。半导体封装结构200包括线路基板210、至少一芯片(第一芯片120以及第二芯片130)、密封体240、多个导电连接件260、重布线路层250以及多个导电端子170。线路基板具有第一表面210a以及相对于第一表面210a的第二表面210b。至少一芯片(第一芯片120以及第二芯片130)具有主动面以及相对于主动面的背面。至少一芯片(第一芯片120以及第二芯片130)以背面配置于线路基板110。密封体240包封至少一芯片(第一芯片120以及第二芯片130)。多个导电连接件260围绕至少一芯片(第一芯片120以及第二芯片130)。重布线路层250位于密封体240上。多个导电端子170位于第二表面110b上。至少一芯片(第一芯片120以及第二芯片130)经由重布线路层250、多个导电连接件260以及线路基板210电性连接至多个导电端子170。
在半导体封装结构200中,由于线路基板210不为暂时载板,因此,于半导体封装结构200的制造过程中可以省去使用暂时载板的成本且不用额外进行移除暂时载板的制程,进而可以降低半导体封装结构200的制造成本。
此外,由于至少一芯片(第一芯片120以及第二芯片130)经由重布线路层250、多个导电连接件260以及线路基板210电性连接至多个导电端子170,因此可以通过重布线路层250、多个导电连接件260以及线路基板210使半导体封装结构200具有高输入/输出连接的数目,且将至少一芯片(第一芯片120以及第二芯片130)信号进行重新配置扩展出去,进而可以提升半导体封装结构200的电性能力和/或效能。
图3A至图3D是依据本发明又一实施例的半导体封装结构的部分制造方法的部分剖面示意图。在本实施例中,半导体封装结构300与半导体封装结构100相似,其类似的构件以相同的标号表示,且具有类似的功能、材质或形成方式,并省略描述。
请参照图3A,提供线路基板110,其中线路基板110具有第一表面110a以及相对于第一表面110a的第二表面110b。接着,将预先形成的多个导电连接件360形成于第一表面110a上。然后,于第一表面110a上配置至少一芯片,其中在图3A至图3D中示意地示出出一个芯片(第一芯片120),但本发明不限于此。
在本实施例中,预先形成的多个导电连接件360可以由铜、铝、镍、上述的组合、或是其他适宜的导电材料所制成。导电连接件360可以通过电镀或其他适宜的制程所形成。
请参照图3B,于线路基板110的第一表面110a上形成密封体340,以包封至少一芯片(第一芯片120)。在本实施例中,密封体340类似于密封体140,密封体340与密封体140的差异在于形成密封体340的步骤可以如下。首先,于线路基板110的第一表面110a上形成密封材料,以完全覆盖第一芯片120与多个导电连接件360。接着,对密封材料进行平坦化制程,直到露出第一芯片120的主动面120a上的导电凸块122与多个导电连接件360的顶面,使第一芯片120的主动面120a上的导电凸块122的顶面、多个导电连接件360的顶面与密封体340的顶面340a实质上共面。
请参照图3C,于密封体340上形成重布线路层350。重布线路层350类似于重布线路层150,重布线路层350与重布线路层150的差异在于:多个导电连接件360不延伸至重布线路层350。重布线路层350可以包括邻近密封体340的底介电层351,而图案化导电层可以包括邻近密封体340的多个导电图案352。
请参照图3D,于线路基板110的第二表面110b上形成多个导电端子170。至少一芯片经由重布线路层350、多个导电连接件360以及线路基板110电性连接至多个导电端子170,因此可以通过重布线路层350、多个导电连接件360以及线路基板110使半导体封装结构300具有高输入/输出连接的数目,且将至少一芯片(第一芯片120)信号进行重新配置扩展出去,进而可以提升半导体封装结构300的电性能力和/或效能。
经过上述制程后即可大致上完成本实施例的半导体封装结构300的制作。半导体封装结构300包括线路基板110、至少一芯片(第一芯片120)、密封体340、多个导电连接件360、重布线路层350以及多个导电端子170。线路基板具有第一表面110a以及相对于第一表面110a的第二表面110b。至少一芯片(第一芯片120)具有主动面以及相对于主动面的背面。至少一芯片(第一芯片120)以背面配置于线路基板110。密封体340包封至少一芯片(第一芯片120)。多个导电连接件360围绕至少一芯片(第一芯片120)。重布线路层350位于密封体340上。多个导电端子170位于第二表面110b上。至少一芯片(第一芯片120)经由重布线路层350、多个导电连接件360以及线路基板110电性连接至多个导电端子170。
在半导体封装结构300中,由于线路基板110不为暂时载板,因此,于半导体封装结构300的制造过程中可以省去使用暂时载板的成本且不用额外进行移除暂时载板的制程,进而可以降低半导体封装结构300的制造成本。
此外,由于至少一芯片(第一芯片120)经由重布线路层350、多个导电连接件360以及线路基板110电性连接至多个导电端子170,因此可以通过重布线路层350、多个导电连接件360以及线路基板110使半导体封装结构300具有高输入/输出连接的数目,且将至少一芯片(第一芯片120)信号进行重新配置扩展出去,进而可以提升半导体封装结构300的电性能力和/或效能。
综上所述,在半导体封装结构中,由于线路基板不为暂时载板,因此,于半导体封装结构的制造过程中可以省去使用暂时载板的成本且不用额外进行移除暂时载板的制程,进而可以降低半导体封装结构的制造成本。再者,由于至少一芯片经由重布线路层、多个导电连接件以及线路基板电性连接至多个导电端子,因此可以通过重布线路层、多个导电连接件以及线路基板使半导体封装结构具有高输入/输出连接的数目,且将至少一芯片信号进行重新配置扩展出去,进而可以提升半导体封装结构的电性能力和/或效能。此外,在至少一芯片为二个以上时,具有不同间距的第一导电凸块与第二导电凸块可以有效地利用线路基板来达成两芯片之间不同的电性连接需求(信号输入/输出及电源/接地),进而可以进一步使半导体封装结构具有更好的信号完整性/电源完整性性能。
Claims (9)
1.一种半导体封装结构,其特征在于,包括:
线路基板,具有第一表面以及相对于所述第一表面的第二表面;
至少一芯片,具有主动面以及相对于所述主动面的背面,其中所述至少一芯片以所述背面配置于所述线路基板,所述至少一芯片中的每一者的所述主动面上具有多个导电凸块,所述多个导电凸块包括多个第一导电凸块与多个第二导电凸块,所述多个第一导电凸块的间距小于所述多个第二导电凸块的间距,所述多个第一导电凸块作为信号输入/输出接点,而所述多个第二导电凸块作为电源/接地接点;
密封体,包封所述至少一芯片;
多个导电连接件,围绕所述至少一芯片;
重布线路层,位于所述密封体上,所述至少一芯片通过所述多个导电凸块与所述重布线路层电性连接;以及
多个导电端子,位于所述第二表面上,其中所述至少一芯片经由所述重布线路层、所述多个导电连接件以及所述线路基板电性连接至所述多个导电端子。
2.根据权利要求1所述的半导体封装结构,其特征在于:
所述至少一芯片包括第一芯片与第二芯片;
所述第一芯片与所述第二芯片的所述多个第一导电凸块通过所述重布线路层电性连接;以及
所述第一芯片与所述第二芯片上的所述多个第二导电凸块通过所述重布线路层以及所述多个导电连接件与所述线路基板电性连接。
3.根据权利要求1所述的半导体封装结构,其特征在于,所述多个导电连接件的顶面与所述密封体的顶面实质上共面。
4.根据权利要求1所述的半导体封装结构,其特征在于,所述多个导电连接件由所述重布线路层延伸至所述线路基板。
5.一种半导体封装结构的制造方法,其特征在于,包括:
提供线路基板,具有第一表面以及相对于所述第一表面的第二表面;
配置至少一芯片于所述第一表面上,其中所述至少一芯片具有主动面以及相对于所述主动面的背面,且所述至少一芯片以所述背面配置于所述线路基板,所述至少一芯片中的每一者的所述主动面上具有多个导电凸块,所述多个导电凸块包括多个第一导电凸块与多个第二导电凸块,所述多个第一导电凸块的间距小于所述多个第二导电凸块的间距,所述多个第一导电凸块作为信号输入/输出接点,而所述多个第二导电凸块作为电源/接地接点;
形成密封体包封所述至少一芯片;
形成多个导电连接件围绕所述至少一芯片;
形成重布线路层于所述密封体上,所述至少一芯片通过所述多个导电凸块与所述重布线路层电性连接;以及
形成多个导电端子于所述第二表面上,其中所述至少一芯片通过所述重布线路层、所述多个导电连接件以及所述线路基板电性连接至所述多个导电端子。
6.根据权利要求5所述的半导体封装结构的制造方法,其特征在于,在形成所述密封体后形成所述多个导电连接件。
7.根据权利要求5所述的半导体封装结构的制造方法,其特征在于,所述多个导电连接件为预先形成的导电柱。
8.根据权利要求7所述的半导体封装结构的制造方法,其特征在于,所述预先形成的导电柱埋设于所述线路基板中。
9.根据权利要求8所述的半导体封装结构的制造方法,其特征在于,所述线路基板具有凹穴,且所述至少一芯片配置于所述凹穴中。
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CN102157394A (zh) * | 2011-03-22 | 2011-08-17 | 南通富士通微电子股份有限公司 | 高密度系统级封装方法 |
CN104011851A (zh) * | 2011-12-22 | 2014-08-27 | 英特尔公司 | 具有窗口插入器的3d集成电路封装 |
US9659911B1 (en) * | 2016-04-20 | 2017-05-23 | Powertech Technology Inc. | Package structure and manufacturing method thereof |
CN109585384A (zh) * | 2017-09-28 | 2019-04-05 | 台湾积体电路制造股份有限公司 | 半导体结构 |
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US11171106B2 (en) | 2021-11-09 |
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