CN109585384A - 半导体结构 - Google Patents
半导体结构 Download PDFInfo
- Publication number
- CN109585384A CN109585384A CN201711288879.4A CN201711288879A CN109585384A CN 109585384 A CN109585384 A CN 109585384A CN 201711288879 A CN201711288879 A CN 201711288879A CN 109585384 A CN109585384 A CN 109585384A
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- China
- Prior art keywords
- semiconductor element
- active surface
- trace
- conductive
- insulating seal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
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Abstract
本发明实施例提供一种包括绝缘密封体、第一半导体管芯、第二半导体管芯及重布线路层的半导体结构。第一半导体管芯与第二半导体管芯嵌置在绝缘密封体中且彼此隔开。第一半导体管芯包括以能够触及的方式暴露出的第一有源表面及分布在所述第一有源表面处的第一导电端子。第二半导体管芯包括以能够触及的方式暴露出的第二有源表面及分布在所述第二有源表面处的第二导电端子。包括导电迹线的重布线路层设置在第一有源表面及第二有源表面上以及绝缘密封体上。导电迹线从第一半导体管芯电连接并蜿蜒地延伸到第二半导体管芯且所述导电迹线的总长度对绝缘密封体的顶部宽度的比率介于约3到约10范围内。
Description
技术领域
本发明的实施例是有关于一种半导体结构。
背景技术
在例如集成扇出型晶片级封装(integrated fan-out wafer level packaging,InFO-WLP)等传统半导体封装技术的一个方面中,可在管芯之上形成与管芯中的有源装置电连接的重布线层(redistribution layer,RDL)。另外,可在管芯周围形成模塑化合物(molding compound)以提供用以支撑扇出型内连线结构的表面区域。举例来说,通常在管芯与模塑化合物二者之上形成包括电路布线层(circuit routing layer)的重布线层。
在此种半导体封装结构中,热量会使管芯与模塑化合物二者在操作期间分别以各自的热膨胀系数(coefficient of thermal expansion,CTE)膨胀。管芯与模塑化合物的CTE不匹配(mismatch)会使拉伸应力集中度(tensile stress concentration)逐渐提高。然而,此种应力可能潜在地损坏电路布线层。举例来说,在热应力下,电路布线层中可能出现开裂(crack)或断裂(break),从而导致电路故障。因此,需要一种提高可靠性且保护电路布线层免受拉伸应力影响的半导体封装结构。
发明内容
根据一些实施例,提供一种包括绝缘密封体、第一半导体管芯、第二半导体管芯及重布线路层的半导体结构。第一半导体管芯嵌置在绝缘密封体中。第一半导体管芯包括第一有源表面及第一导电端子,所述第一有源表面被绝缘密封体以能够触及的方式暴露出,所述第一导电端子分布在所述第一有源表面处。第二半导体管芯嵌置在绝缘密封体中且与第一半导体管芯隔开。第二半导体管芯包括第二有源表面及第二导电端子,所述第二有源表面被绝缘密封体以能够触及的方式暴露出,所述第二导电端子分布在所述第二有源表面处。重布线路层设置在第一半导体管芯的第一有源表面上,第二半导体管芯的第二有源表面上及绝缘密封体上。重布线路层包括导电迹线。导电迹线从第一半导体管芯电连接并蜿蜒地延伸到第二半导体管芯。导电迹线的总长度对绝缘密封体的顶部宽度的比率介于约3到约10范围内。
根据一些替代性实施例,提供一种包括绝缘密封体、第一半导体管芯、第二半导体管芯及导电迹线的半导体结构。第一半导体管芯嵌置在绝缘密封体中。第一半导体管芯包括第一有源表面及第一导电端子,所述第一有源表面被绝缘密封体以能够触及的方式暴露出,所述第一导电端子分布在所述第一有源表面处。第二半导体管芯嵌置在绝缘密封体中且与第一半导体管芯隔开。第二半导体管芯包括第二有源表面及第二导电端子,所述第二有源表面被绝缘密封体以能够触及的方式暴露出,所述第二导电端子分布在所述第二有源表面处。导电迹线从第一导电端子蜿蜒地延伸到第二导电端子以电连接在第一半导体管芯与第二半导体管芯之间。导电迹线的总长度大于第一导电端子与第二导电端子之间的最短距离,且所述导电迹线的所述总长度比绝缘密封体的顶部宽度大至少3倍。
根据一些替代性实施例,提供一种包括多个半导体管芯、绝缘密封体及重布线路层的半导体结构。半导体管芯中的每一者包括有源表面。绝缘密封体在侧向上密封半导体管芯。半导体管芯通过绝缘密封体彼此间隔开。重布线路层设置在半导体管芯的有源表面上及绝缘密封体上。重布线路层包括之字形导电图案,所述之字形导电图案对应于绝缘密封体且电连接在半导体管芯之间。
附图说明
结合附图阅读以下详细说明,会最好地理解本发明的各个方面。应注意,根据本行业中的标准惯例,各种特征并非按比例绘制。事实上,为论述清晰起见,可任意增大或减小各种特征的尺寸。
图1是说明根据本发明一些实施例的集成扇出型封装的示意性剖视图。
图2A是说明根据本发明一些实施例的半导体结构的示意性俯视图。
图2B是沿图2A中的半导体结构的线A-A截取的示意性剖视图。
图3A是说明根据本发明一些实施例的半导体结构的示意性俯视图。
图3B是沿图3A中的半导体结构的线B-B截取的示意性剖视图。
图4是说明根据本发明一些实施例的半导体结构的示意性透视图。
[符号的说明]
2:电路衬底
3:导电凸块
4:外部端子
6、10、20、30:半导体结构
50:集成扇出型封装
100:半导体管芯
110:第一半导体管芯
110a:第一有源表面
112:第一导电端子
120:第二半导体管芯
120a:第二有源表面
122:第二导电端子
210:绝缘密封体
210a:顶表面
310、410、510:重布线路层
312、416、516:导电迹线
312a:转向段
312b:导电接垫
314:介电层
412、512:第一介电层
414、514:第二介电层
416a、516a:第一迹线
416a’、516a’:第一层阶
416a”、516a”:第二层阶
416b、516b:导电通孔
416c、516c:第二迹线
A-A、B-B:线
D:最短距离
D’:距离
G:间隙
L1、L2:切线
P1:平面
W:顶部宽度
X、Y:方向
Z:方向/圆圈
Z1、Z2:圆圈
θ:角度
具体实施方式
以下公开内容提供用于实作所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例以简化本公开内容。当然,这些仅为实例且不旨在进行限制。举例来说,以下说明中将第一特征形成在第二特征之上或第二特征上可包括其中第一特征及第二特征被形成为直接接触的实施例,且也可包括其中第一特征与第二特征之间可形成有附加特征、进而使得所述第一特征与所述第二特征可能不直接接触的实施例。另外,本公开内容可能在各种实例中重复使用参考编号及/或字母。这种重复使用是出于简洁及清晰的目的,而不是自身表示所论述的各种实施例及/或配置之间的关系。
此外,为易于说明,本文中可能使用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所说明的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括装置在使用或操作中的不同取向。设备可具有其他取向(旋转90度或处于其他取向)且本文中所使用的空间相对性描述语可同样相应地进行解释。
也可包括其他特征及工艺。举例来说,可包括测试结构,以帮助对三维(three-dimensional,3D)封装或三维集成电路(3D integrated circuit,3DIC)装置进行验证测试。所述测试结构可例如包括在重布线层中或在衬底上形成的测试接垫,所述测试接垫容许对3D封装或3DIC进行测试、对探针及/或探针卡(probe card)进行使用等。可对中间结构以及最终结构执行验证测试。另外,本文中所公开的结构及方法可结合包括对已知良好管芯(known good die)进行中间验证的测试方法而使用,以提高良率并降低成本。
图1是说明根据本发明一些实施例的半导体封装的示意性剖视图。参照图1,在一些实施例中,集成扇出型封装50可包括电路衬底(circuit substrate)2、外部端子4及半导体结构6,外部端子4安装在电路衬底2的下表面上且电连接到电路衬底2,半导体结构6设置在电路衬底2的上表面上。所述上表面与所述下表面相对。换句话说,外部端子4与半导体结构6设置在电路衬底2的相对两侧。在一些实施例中,电路衬底2可为包括交替堆叠的图案化导电层与图案化介电层的印刷电路板,且安装在电路衬底2的下表面上的外部端子4可为排列成格栅阵列(grid array)的焊球(solder balls)。举例来说,半导体结构6可首先形成并接着安装在电路衬底2上并且通过导电凸块3电连接到电路衬底2。集成扇出型封装50可包括多个半导体管芯且集成扇出型封装50通过导电凸块3(例如受控塌陷芯片连接凸块(controlled collapse chip connection bump),即C4凸块)电连接到电路衬底2。以下将阐述关于半导体结构6的实施例的细节。
图2A是说明根据本发明一些实施例的半导体结构的示意性俯视图且图2B是沿图2A中的半导体结构的线A-A截取的示意性剖视图。参照图2A及图2B,在一些实施例中,半导体结构10包括多个半导体管芯(semiconductor dies)100(例如第一半导体管芯110及第二半导体管芯120)、绝缘密封体210及电连接到半导体管芯100的重布线路层310。在一些实施例中,半导体管芯100中的每一者包括有源表面及分布在所述有源表面处的导电端子。举例来说,第一半导体管芯110包括第一有源表面110a及分布在第一有源表面110a处的至少一个第一导电端子112,且第二半导体管芯120包括第二有源表面120a及分布在第二有源表面120a处的至少一个第二导电端子122。应注意,图中的半导体管芯100的数目仅用作示例性说明且本发明的实施例并非仅限于此。在一些替代性实施例中,可采用更多的半导体管芯100来形成半导体结构10。
在一些实施例中,绝缘密封体210可在侧向上密封半导体管芯100的侧壁,从而使得半导体管芯100可通过所述绝缘密封体210彼此间隔开。举例来说,在第一半导体管芯110与第二半导体管芯120之间可具有间隙G,且绝缘密封体210可位于间隙G中且填充间隙G从而使第一半导体管芯110与第二半导体管芯120在空间上隔开。换句话说,第一半导体管芯110与第二半导体管芯120可单独地(separately)嵌置在绝缘密封体210中。举例来说,绝缘密封体210可包含通过压缩模塑(compressive molding)、转移模塑(transfer molding)或其他适合的形成工艺而形成的绝缘材料或聚合物复合材料。在一些实施例中,第一半导体管芯110的第一有源表面110a与第二半导体管芯120的第二有源表面120a可被绝缘密封体210以能够触及(accessibly)的方式暴露出,从而使得第一导电端子112及第二导电端子122可被绝缘密封体210以能够触及的方式暴露出以进行进一步的电连接。
如图2A中所示,第一半导体管芯110的第一导电端子112及第二半导体管芯120的第二导电端子122可在X方向上具有一对平行的切线L1且在与X方向垂直的Y方向上具有一对平行的切线L2。换句话说,平行的切线L1可实质上垂直于平行的切线L2。在一些实施例中,第一半导体管芯110的第一导电端子112与第二半导体管芯120的第二导电端子122之间的最短距离D可在平行的切线L2之间测得。最短距离D可大于第一半导体管芯110与第二半导体管芯120之间的绝缘密封体210的顶部宽度W且最短距离D可小于绝缘密封体210的顶部宽度W的3倍。在一些情形中,第一半导体管芯110与第二半导体管芯120之间的绝缘密封体210的顶部宽度W大于第一半导体管芯110的面朝第二半导体管芯120的侧壁与第二半导体管芯120的面朝第一半导体管芯110的侧壁之间的距离D’。举例来说,在剖视图中,第一导电端子112与第二导电端子122之间的绝缘密封体210的顶部部分(图中未说明)可具有宽的顶部及窄的底部。
在一些实施例中,第一半导体管芯110的第一有源表面110a及第二半导体管芯120的第二有源表面120a可与绝缘密封体210的顶表面210a实质上共面。重布线路层310可设置在第一有源表面110a上、第二有源表面120a上及绝缘密封体210的顶表面210a上。举例来说,重布线路层310可在侧向上延伸超过导电端子的外部周界(external perimeters)以提供扇出型内连线结构。举例来说,导电端子(例如第一导电端子112及第二导电端子122)可包括铜通孔(cooper vias)。在一些实施例中,重布线路层310可包括至少一个导电迹线(conductive trace)312。导电迹线312可从第一半导体管芯110的第一导电端子112电连接并蜿蜒地延伸到第二半导体管芯120的第二导电端子122。本文中所使用的蜿蜒地延伸到第二导电端子122的导电迹线312可包括比其所连接的各所述导电端子之间的最短距离长的任意电迹线,或者包括具有足以维持导电性的长度的任意电迹线。举例来说,从第一导电端子112蜿蜒地延伸到第二导电端子122的导电迹线312的电路径可被配置成具有连续的曲线、弯曲部分等的迹线。换句话说,导电迹线312可电连接到半导体管芯100并对电信号进行重新路由(reroute)以供进行进一步的电连接。举例来说,导电迹线312的总长度可近似介于50微米(μm)到500μm范围内。在一些实施例中,导电迹线312的总长度可大于最短距离D且比绝缘密封体210的顶部宽度W大至少3倍。举例来说,导电迹线312的总长度对绝缘密封体210的顶部宽度W的比率介于约3到约10范围内。在一些情形中,最短距离D小于绝缘密封体210的顶部宽度W的3倍。如果在此种情形中,连接在第一导电端子112与第二导电端子122之间的导电迹线312的电路径为线性的(linear),则因CTE不匹配而造成的拉伸应力可能负面地影响导电迹线312,例如使得导电迹线312可能易于开裂。由于导电迹线312在半导体管芯100之间蜿蜒地延伸以增大导电迹线312的总长度,因此这会提高导电迹线312对因CTE不匹配而造成的拉伸应力的容忍能力。
在一些实施例中,重布线路层310的导电迹线312可包括与绝缘密封体210对应的至少一个转向段(turning segment)312a。如图2A中所示,举例来说,转向段312a位于绝缘密封体210上方。在一些实施例中,转向段312a可位于第一半导体管芯110及/或第二半导体管芯120上方。在一些其他实施例中,依据设计要求,在俯视图中,转向段312a可位于半导体管芯100与绝缘密封体210之间的界面上方。转向段312a可位于与第一半导体管芯110的第一有源表面110a及第二半导体管芯120的第二有源表面120a实质上平行的平面P1处。举例来说,平面P1可为X-Y平面。
在一些实施例中,导电迹线312可被形成为与绝缘密封体210对应的之字形(zigzag)导电图案。在一些其他实施例中,导电迹线312的转向段312a的电路径可被形成为有角路径(angular path)。举例来说,转向段312a的电路径的角度θ可包括锐角、直角或钝角。多个转向段312a可彼此连接以形成蜿蜒的图案。在一些实施例中,转向段312a的电路径可为弯曲路径(curve path)。举例来说,蜿蜒的图案可以正弦方式分布在第一导电端子112与第二半导体管芯120的第二导电端子122之间。在一些实施例中,之字形导电图案可被形成为规则图案。举例来说,之字形导电图案可以是相对于绝缘密封体210的中心对称。在一些其他实施例中,依据布线设计要求,之字形导电图案可被形成为不规则图案。
在一些其他实施例中,导电迹线312可包括形成在第一导电端子112上及第二导电端子122上的导电接垫312b。在一些实施例中,导电迹线312的布线区域(layout area)可位于第一导电端子112及第二导电端子122的平行的切线L1之间。在一些其他实施例中,依据布线设计要求,导电迹线312的布线区域可位于第一导电端子112及第二导电端子122的平行的切线L1之间及/或位于第一导电端子112及第二导电端子122的平行的切线L1外部。
举例来说,重布线路层310可包括形成在第一有源表面110a之上、第二有源表面120a之上及绝缘密封体210的顶表面210a之上的介电层314。在一些实施例中,介电层可包含例如聚酰亚胺、苯并环丁烯(benzocyclobutene,BCB)、聚苯并恶唑(polybenzoxazole,PBO)、类似材料或其组合等光可图案化绝缘材料(photo-patternable insulatingmaterial),且可通过化学气相沉积(chemical vapor deposition,CVD)、物理气相沉积(physical vapor deposition,PVD)、原子层沉积(atomic layer deposition,ALD)、旋涂介电质工艺(spin-on-dielectric process)、类似工艺或其组合来形成。
在一些实施例中,可使用例如光刻技术(photolithography technique)或其他适合的工艺将介电层314图案化以形成多个开口(图中未说明),所述多个开口暴露出半导体管芯100的导电端子的至少所述表面。在一些其他实施例中,可通过在介电层314之上及在开口中沉积晶种层(seed layer)(图中未说明)来形成导电迹线312。晶种层可包含例如铜、钛、镍、金、类似材料或其组合等导电材料。接下来,可在晶种层之上沉积光刻胶(photoresist)材料(图中未说明)并将所述光刻胶材料图案化以界定例如之字形导电图案等期望图案。可通过电化学镀覆工艺(electro-chemical plating process)、无电镀覆工艺(electroless plating process)、PVD、ALD、类似工艺或其组合在晶种层上形成导电迹线的材料(例如铜、铝、银、金、类似材料或其组合)。随后,可使用适宜的光刻胶移除工艺移除光刻胶材料。在一些实施例中,可在介电层314之前形成导电迹线312。导电迹线312与介电层314的所述形成顺序在本发明的实施例中不构成限制。
在一些实施例中,位于介电层314之上的晶种层的暴露部分可使用例如蚀刻(etching)工艺或其他适合的工艺移除。在一些其他实施例中,可在导电迹线312之上形成保护层(passivation layer)(图中未说明)以保护导电迹线312免受损坏。也可利用导电迹线312的其他可能形状,只要导电迹线312的总长度对绝缘密封体210的顶部宽度W的比率可介于约3到约10范围内即可。这样一来,半导体结构10可承受住因半导体管芯100与绝缘密封体210之间的CTE不匹配而造成的拉伸应力并消除因重布线路层310的开裂而造成的负面影响,从而使半导体结构10的可靠性可提高。
图3A是说明根据本发明一些实施例的半导体结构的示意性透视图且图3B是沿图3A中的半导体结构的线B-B截取的示意性剖视图。参照图3A及图3B,本实施例的半导体结构20相似于图2A中所说明实施例的半导体结构10。在所有图式中,相同或相似的标号指代相同或相似的元件且不再对其予以赘述。半导体结构20与图2A所示的半导体结构10之间的差异在于重布线路层410可包括多于一个导电特征(conductive feature)(例如导电迹线及/或导电通孔)。
在一些实施例中,重布线路层410可包括第一介电层412及第二介电层414。举例来说,可形成第一介电层412并将第一介电层412图案化以在第一半导体管芯110上、第二半导体管芯120上及绝缘密封体210的顶表面210a上形成开口(图中未说明)。第一介电层412的开口可暴露出半导体管芯100的导电端子(例如112及122)的一部份。接下来,可在第一介电层412上且在开口中形成导电迹线416的第一迹线416a的第一层阶(level)416a’。第一介电层412及导电迹线416的形成方法及材料可与介电层314及导电迹线312相似。不再予以赘述。随后,可在第一介电层412上形成第二介电层414并将第二介电层414图案化成具有暴露出第一迹线416a的一部份的开口。接下来,可在第二介电层414的开口中形成多个导电通孔416b且可在导电通孔416b上及在第二介电层414上形成第一迹线416a的第二层阶416a”。换句话说,第一迹线416的第一层阶416a’与第二层阶416a”可通过导电通孔416b电连接。在一些实施例中,可在同一工艺中形成导电通孔416b与第一迹线416a的第二层阶416a”。第二层阶416a”的形成工艺可与第一迹线416a及导电迹线312的形成工艺相似,因而不再予以赘述。在一些实施例中,包括第一层阶416a’及第二层阶416a”的第一迹线416a可位于与第一有源表面110a及第二有源表面120a实质上平行的第一平面(图中未说明)处。
在一些实施例中,导电通孔416b与连接到导电通孔416b的第一迹线416a的第一层阶416a’的一部份及第二层阶416a”的一部份可被称作第二迹线416c。在剖视图中,第二迹线416c可被形成为之字形导电图案(如图3B中的圆圈Z的斜线区域)且被称作导电迹线416的转向段。在一些实施例中,第二迹线416c可形成在绝缘密封体210上方。在一些其他实施例中,第二迹线416c可位于与第一半导体管芯110的第一有源表面110a及第二半导体管芯120的第二有源表面120a实质上垂直的第二平面(如沿图3A中的B-B线截取的剖视平面)处。在一些实施例中,导电迹线416的第一迹线416a的第二层阶416a”的总长度可介于最短距离D与绝缘密封体210的顶部宽度W之间。在一些其他实施例中,导电迹线416的第二迹线416c的总长度可大于第一导电端子112与第二导电端子122之间的最短距离D。
在一些实施例中,导电迹线416的转向段可相对于绝缘密封体210对称地形成在半导体管芯100的有源表面(例如第一有源表面110a及第二有源表面110b)上方。在一些实施例中,导电迹线416的转向段可对应于第一有源表面110a及/或第二有源表面120a及/或绝缘密封体210的顶表面210a。在一些实施例中,在剖视图中,导电迹线416的转向段可位于半导体管芯100与绝缘密封体210之间的界面上方。在一些实施例中,导电通孔416b可具有锥形(tapered)的侧壁。在一些其他实施例中,导电通孔416b可具有垂直的侧壁。通过交替地重复进行以上步骤,完成重布线路层410的形成过程。
在半导体结构20中,导电通孔416b可在第一迹线416a与第二迹线416c之间提供连通路径。导电通孔416b可贡献用于对导电迹线416进行布线的延伸路径。这样一来,半导体结构20可承受住因半导体管芯100与绝缘密封体210之间的CTE不匹配而造成的拉伸应力并消除因重布线路层410的开裂而造成的负面影响,从而使半导体结构20的可靠性可提高。
图4是说明根据本发明一些实施例的半导体结构的示意性透视图。参照图4,本实施例的半导体结构30与图2A及图2B中所说明实施例的半导体结构10与图3A及图3B中所说明实施例的半导体结构20的组合相似。在所有图式中,相同或相似的标号指代相同或相似的元件且不再对其予以赘述。半导体结构30、半导体结构10及半导体结构20之间的差异在于重布线路层510的导电迹线516的布线。
导电迹线516(或称作之字形导电图案)的第一迹线516a包括第一层阶516a’及/或第二层阶516a”,第一迹线516a可被形成为转向段(如图4中的圆圈Z1的斜线区域),转向段对应于绝缘密封体210。第一迹线516a的形成过程可与图2A及图2B中所说明的实施例相似且将简化详细说明。举例来说,可在半导体管芯100及绝缘密封体210上形成第一介电层512并将第一介电层512图案化成具有开口(图中未说明)。随后,可在开口中及在第一介电层512上形成第一迹线516a的第一层阶516a’,从而使得第一迹线516a的第一层阶516a’可在俯视图中包括转向段。在一些其他实施例中,第一迹线516a的第二层阶516a”可在俯视图中包括转向段(或称作之字形导电图案)。举例来说,可在第一介电层512上形成第二介电层514并将第二介电层514图案化成具有暴露出导电通孔516b的一部分的开口(图中未说明)。可在开口中将第一迹线516a的第二层阶516a”形成为电连接到导电通孔516b且在第二介电层514上形成第一迹线516a的第二层阶516a”,从而使得第二层阶516a”可在俯视图中包括转向段。这样一来,导电迹线516的总长度可增大。
在一些实施例中,导电迹线516的转向段(如图4中的圆圈Z2的斜线区域)可包括导电通孔516b,第一迹线516a的第一层阶516a’的一部份及第二层阶516a”的一部份连接到导电通孔516b且转向段也可被称作之字形导电图案。转向段(如图4中的圆圈Z2的斜线区域)的形成过程可与图3B中的圆圈Z的斜线区域相似且不再予以赘述。在一些实施例中,第一迹线516a可位于与半导体管芯100的有源表面(例如110a及110b)实质上平行的第一平面(图中未说明)处,并且包括导电通孔516b的第二迹线516c可位于与半导体管芯100的有源表面(例如110a及110b)实质上垂直的第二平面(图中未说明)处。
由于导电迹线516包括用于增大导电迹线516的总长度的转向段,因此半导体结构30可承受住因半导体管芯100与绝缘密封体210之间的CTE不匹配而造成的拉伸应力并消除因重布线路层510的开裂而造成的负面影响,从而使半导体结构30的可靠性可提高。
根据一些实施例,提供一种包括绝缘密封体、第一半导体管芯、第二半导体管芯及重布线路层的半导体结构。第一半导体管芯嵌置在绝缘密封体中。第一半导体管芯包括第一有源表面及第一导电端子,所述第一有源表面被绝缘密封体以能够触及的方式暴露出,所述第一导电端子分布在所述第一有源表面处。第二半导体管芯嵌置在绝缘密封体中且与第一半导体管芯隔开。第二半导体管芯包括第二有源表面及第二导电端子,所述第二有源表面被绝缘密封体以能够触及的方式暴露出,所述第二导电端子分布在所述第二有源表面处。重布线路层设置在第一半导体管芯的第一有源表面上,第二半导体管芯的第二有源表面上及绝缘密封体上。重布线路层包括导电迹线。导电迹线从第一半导体管芯电连接并蜿蜒地延伸到第二半导体管芯。导电迹线的总长度对绝缘密封体的顶部宽度的比率介于约3到约10范围内。
在一些实施例中,所述第一导电端子与所述第二导电端子之间的最短距离大于所述绝缘密封体的所述顶部宽度。在一些实施例中,所述导电迹线电连接在所述第一半导体管芯的所述第一导电端子与所述第二半导体管芯的所述第二导电端子之间。在一些实施例中,在所述第一半导体管芯与所述第二半导体管芯之间具有间隙,且所述绝缘密封体填充所述间隙。
根据一些替代性实施例,提供一种包括绝缘密封体、第一半导体管芯、第二半导体管芯及导电迹线的半导体结构。第一半导体管芯嵌置在绝缘密封体中。第一半导体管芯包括第一有源表面及第一导电端子,所述第一有源表面被绝缘密封体以能够触及的方式暴露出,所述第一导电端子分布在所述第一有源表面处。第二半导体管芯嵌置在绝缘密封体中且与第一半导体管芯隔开。第二半导体管芯包括第二有源表面及第二导电端子,所述第二有源表面被绝缘密封体以能够触及的方式暴露出,所述第二导电端子分布在所述第二有源表面处。导电迹线从第一导电端子蜿蜒地延伸到第二导电端子以电连接在第一半导体管芯与第二半导体管芯之间。导电迹线的总长度大于第一导电端子与第二导电端子之间的最短距离,且所述导电迹线的所述总长度比绝缘密封体的顶部宽度大至少3倍。
在一些实施例中,所述第一导电端子与所述第二导电端子之间的所述最短距离小于所述绝缘密封体的所述顶部宽度的3倍。在一些实施例中,在所述第一半导体管芯与所述第二半导体管芯之间具有间隙,且所述绝缘密封体填充所述间隙。
根据一些替代性实施例,提供一种包括多个半导体管芯、绝缘密封体及重布线路层的半导体结构。半导体管芯中的每一者包括有源表面。绝缘密封体在侧向上密封半导体管芯。半导体管芯通过绝缘密封体彼此间隔开。重布线路层设置在半导体管芯的有源表面上及绝缘密封体上。重布线路层包括之字形导电图案,所述之字形导电图案对应于绝缘密封体且电连接在半导体管芯之间。
在一些实施例中,所述半导体管芯中彼此相邻的两个半导体管芯之间的最短距离大于填充所述半导体管芯中彼此相邻的所述两个半导体管芯之间的间隙的所述绝缘密封体的顶部宽度。在一些实施例中,所述半导体管芯中的每一者包括分布在各自的所述有源表面处的导电端子,且所述重布线路层的所述之字形导电图案电连接到所述半导体管芯的所述导电端子。
以上概述了若干实施例的特征,以使所属领域中的技术人员可更好地理解本发明的各个方面。所属领域中的技术人员应知,其可容易地使用本发明作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的及/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到,这些等效构造并不背离本发明的精神及范围,而且他们可在不背离本发明的精神及范围的条件下对其作出各种改变、代替、及变更。
Claims (10)
1.一种半导体结构,其特征在于,包括:
绝缘密封体;
第一半导体管芯,嵌置在所述绝缘密封体中,其中所述第一半导体管芯包括第一有源表面及第一导电端子,所述第一有源表面被所述绝缘密封体以能够触及的方式暴露出,所述第一导电端子分布在所述第一有源表面处;
第二半导体管芯,嵌置在所述绝缘密封体中且与所述第一半导体管芯隔开,其中所述第二半导体管芯包括第二有源表面及第二导电端子,所述第二有源表面被所述绝缘密封体以能够触及的方式暴露出,所述第二导电端子分布在所述第二有源表面处;以及
重布线路层,设置在所述第一半导体管芯的所述第一有源表面上、所述第二半导体管芯的所述第二有源表面上及所述绝缘密封体上,所述重布线路层包括导电迹线,其中所述导电迹线从所述第一半导体管芯电连接并蜿蜒地延伸到所述第二半导体管芯,且所述导电迹线的总长度对所述第一半导体管芯与所述第二半导体管芯之间的所述绝缘密封体的顶部宽度的比率介于约3到约10范围内。
2.根据权利要求1所述的半导体结构,其特征在于,所述重布线路层的所述导电迹线包括位于所述绝缘密封体上方的至少一个转向段。
3.根据权利要求2所述的半导体结构,其特征在于,所述导电迹线的所述至少一个转向段位于与所述第一半导体管芯的所述第一有源表面及所述第二半导体管芯的所述第二有源表面实质上平行或实质上垂直的平面处。
4.根据权利要求2所述的半导体结构,其特征在于,所述导电迹线的所述至少一个转向段包括第一迹线及连接到所述第一迹线的第二迹线,所述第一迹线位于与所述第一有源表面及所述第二有源表面实质上平行的第一平面处,且所述第二迹线位于与所述第一半导体管芯的所述第一有源表面及所述第二半导体管芯的所述第二有源表面实质上垂直的第二平面处。
5.一种半导体结构,其特征在于,包括:
绝缘密封体;
第一半导体管芯,嵌置在所述绝缘密封体中,其中所述第一半导体管芯包括第一有源表面及第一导电端子,所述第一有源表面被所述绝缘密封体以能够触及的方式暴露出,所述第一导电端子分布在所述第一有源表面处;
第二半导体管芯,嵌置在所述绝缘密封体中且与所述第一半导体管芯隔开,其中所述第二半导体管芯包括第二有源表面及第二导电端子,所述第二有源表面被所述绝缘密封体以能够触及的方式暴露出,所述第二导电端子分布在所述第二有源表面处;以及
导电迹线,从所述第一导电端子蜿蜒地延伸到所述第二导电端子以电连接在所述第一半导体管芯与所述第二半导体管芯之间,其中所述导电迹线的总长度大于所述第一导电端子与所述第二导电端子之间的最短距离,且所述导电迹线的所述总长度比所述第一半导体管芯与所述第二半导体管芯之间的所述绝缘密封体的顶部宽度大至少3倍。
6.根据权利要求5所述的半导体结构,其特征在于,所述导电迹线包括至少一个转向段,所述至少一个转向段位于与所述第一半导体管芯的所述第一有源表面及所述第二半导体管芯的所述第二有源表面实质上平行或实质上垂直的平面处。
7.根据权利要求5所述的半导体结构,其特征在于,所述导电迹线包括第一迹线及连接到所述第一迹线的第二迹线,所述第一迹线位于与所述第一有源表面及所述第二有源表面实质上平行的第一平面处,且所述第二迹线位于与所述第一半导体管芯的所述第一有源表面及所述第二半导体管芯的所述第二有源表面实质上垂直的第二平面处。
8.一种半导体结构,其特征在于,包括:
多个半导体管芯,其中所述半导体管芯中的每一者包括有源表面;
绝缘密封体,在侧向上密封所述半导体管芯,其中所述半导体管芯通过所述绝缘密封体彼此间隔开;以及
重布线路层,设置在所述半导体管芯的所述有源表面上及所述绝缘密封体上,其中所述重布线路层包括之字形导电图案,所述之字形导电图案对应于所述绝缘密封体且电连接在所述半导体管芯之间。
9.根据权利要求8所述的半导体结构,其特征在于,所述重布线路层的所述之字形导电图案位于与所述半导体管芯的所述有源表面实质上平行或实质上垂直的平面处。
10.根据权利要求8所述的半导体结构,其特征在于,所述之字形导电图案包括第一迹线及连接到所述第一迹线的第二迹线,所述第一迹线位于与所述半导体管芯的所述有源表面实质上平行的第一平面处,且所述第二迹线位于与所述半导体管芯的所述有源表面实质上垂直的第二平面处。
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