CN103824819B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN103824819B
CN103824819B CN201310539882.4A CN201310539882A CN103824819B CN 103824819 B CN103824819 B CN 103824819B CN 201310539882 A CN201310539882 A CN 201310539882A CN 103824819 B CN103824819 B CN 103824819B
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semiconductor element
downside
partition wall
dielectric film
outer electrode
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CN103824819A (zh
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须田亨
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Rely On Technology Japan Co
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J Devices Corp
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Abstract

本发明提供不会阻碍外部电极与键合线的电接触、不对小型化以及量产化造成障碍的CoC连接的半导体装置。具有：矩形形状的下侧半导体元件；沿着所述下侧半导体元件的边而排列并形成在下侧半导体元件上的多个外部电极；经由多个布线图案与多个外部电极分别电连接、且排列并形成在下侧半导体元件上的多个内部电极；形成为包围多个外部电极中的每一个或每多个的隔墙图案；以多个端子分别与多个内部电极电连接的方式搭载在下侧半导体元件上的上侧半导体元件；以及以滴注并流入下侧半导体元件与上侧半导体元件之间的方式而形成的树脂。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置及其制造方法。特别地，涉及在CoC（chip on chip；叠层芯片）结构的半导体装置中，不管上侧半导体元件的大小如何都能够不使底部填充（underfiling）树脂流入下侧半导体元件的外部电极（周边部电极）的、可靠性高的半导体装置及其制造方法。
背景技术
以往，对CoC（叠层芯片）连接结构的半导体装置进行了研究，利用图8对其具体的结构进行说明。即，在表面上形成了电极9的下侧半导体芯片6上，经由凸块8以倒装芯片安装的方式搭载有上侧半导体芯片5。下侧半导体芯片6与上侧半导体芯片5之间以及凸块8被通过滴注（灌封）而流入的底部填充树脂4所覆盖。下侧半导体芯片6借助于粘接剂7搭载在基底基板2上，下侧半导体芯片6的周边部的外部电极9与基底基板2的电极通过键合线10而电连接。在基底基板2上以包围上侧半导体芯片5、下侧半导体芯片6的方式形成有树脂1。在基底基板2的背面形成有在安装于印刷电路基板等上所使用的焊料球3。
在如上述那样的CoC连接结构的半导体装置中，通过滴注而流入的底部填充树脂4会流入到外部电极9表面，结果，存在阻碍外部电极9与键合线10的电接触的可能性。
于是，在日本特开2003-234362号公报（专利文献1）以及日本特开2005-276879号公报（专利文献2）记载的半导体装置中，公开了形成用于防止使通过滴注而流入的底部填充树脂4到达外部电极9的表面的隔墙的例子。利用图9、图10以及图11对将这种隔墙应用于图8的半导体装置的例子进行说明。
图9是形成了用于防止使通过滴注而流入的底部填充树脂4到达外部电极9的表面的隔墙11的例子的剖视图。图10是下侧半导体芯片6的俯视图，图11是刚进行了CoC连接后的上侧半导体芯片5以及下侧半导体芯片6的剖视图。若在该状态下，将底部填充树脂4滴注到隔墙11与上侧半导体芯片5之间的区域，则如图9的剖面图所示，底部填充树脂会扩散，但是即便滴注的底部填充树脂4向外侧方向流动，由于在一定程度上被隔墙11阻拦，因此底部填充树脂4也不会覆盖外部电极9的表面，结果，阻碍外部电极9与键合线10的电接触的可能性被降低。
（现有技术文献）
（专利文献）
专利文献1：日本特开2003-234362号公报
专利文献2：日本特开2005-276879号公报
然而，在以往的CoC连接的半导体装置中，若向外侧方向流动的底部填充树脂4一旦越过了隔墙11，则底部填充树脂4会覆盖大部分的外部电极9的表面，结果，会阻碍外部电极9与键合线10的电接触。为了避免发生这样的问题，必须充分地设置隔墙11与上侧半导体芯片5的距离，并且严格地控制底部填充树脂4的量，从而会对半导体装置的小型化以及量产化造成障碍。另外，在以往的CoC连接的半导体装置中，由于隔墙11以一条线的方式包围内部电极，因此存在在热处理工序中以及因树脂的滴注而脱落的担忧。
发明内容
本发明鉴于上述课题而完成，其目的在于提供不阻碍外部电极与键合线的电接触、不会对小型化以及量产化造成障碍的CoC连接的半导体装置及其制造方法。
为了解决上述课题，本发明的一个实施方式所涉及的半导体装置的特征在于，具有：矩形形状的下侧半导体元件；多个外部电极，所述多个外部电极沿着所述下侧半导体元件的边而排列并形成在下侧半导体元件上；多个内部电极，所述多个内部电极经由多个布线图案与多个外部电极分别电连接，并且排列而形成在下侧半导体元件上；隔墙图案，其形成为包围多个外部电极中的每一个或每多个；上侧半导体元件，其以多个端子分别与多个内部电极电连接的方式搭载在下侧半导体元件上；以及树脂，其输出为滴注并流入下侧半导体元件与上侧半导体元件之间的方式。
优选地，隔墙图案由焊料形成，且与形成在内部电极上的焊料凸块同时地形成。
在下侧半导体元件表面上形成有绝缘膜，多个布线图案形成在绝缘膜上。优选地，在布线图案上还形成有高分子绝缘薄膜，所述高分子绝缘薄膜的、多个内部电极以及多个外部电极的区域是开口了的。
优选地，隔墙图案是在维持从滴注树脂的区域通向下侧半导体元件的外周的空隙的同时形成的。
优选地，隔墙图案形成为将多个外部电极按每多个进行包围的方式，并且隔墙图案也形成在外部电极的各个之间。
为了解决上述课题，本发明的一个实施方式所涉及的半导体装置的制造方法的特征在于，具有：在矩形形状的下侧半导体元件上形成沿着所述下侧半导体元件的边而排列的多个外部电极、排列了的多个内部电极以及将多个外部电极与多个内部电极分别电连接的布线图案的工序；以将多个外部电极中的每一个或每多个进行包围的方式形成隔墙图案的工序；以将上侧半导体元件的多个端子分别与多个内部电极电连接的方式在下侧半导体元件上搭载上侧半导体元件的工序；以及以流入下侧半导体元件与上侧半导体元件之间的方式滴注形成树脂的工序。
优选地，隔墙由焊料形成，并且与形成在内部电极上的焊料凸块同时地形成。
在下侧半导体元件表面上形成绝缘膜，在绝缘膜上形成多个布线图案。优选地，在布线图案上还形成有高分子绝缘薄膜，所述高分子绝缘薄膜的、多个内部电极以及多个外部电极的区域是开口了的。
优选地，一边维持从滴注树脂的区域通向下侧半导体元件的外周的空隙，一边形成隔墙图案。
优选地，以将多个外部电极按每多个进行包围的方式形成隔墙图案，并且在外部电极的各个之间也形成隔墙图案。
（发明的效果）
根据本发明，能够提供不阻碍外部电极与键合线的电接触、不对小型化以及量产化造成障碍的CoC连接的半导体装置及其制造方法。关于其他的效果，会在下文中详述。
附图说明
图1是本发明的一个实施方式的半导体装置的剖视图。
图2是本发明的一个实施方式的下侧半导体芯片的俯视图。
图3是本发明的一个实施方式的下侧半导体芯片以及上侧半导体芯片在CoC连接之前的状态下的剖视图。
图4是本发明的一个实施方式的下侧半导体芯片以及上侧半导体芯片在CoC连接之后的状态下的剖视图。
图5是本发明的第一变形例的下侧半导体芯片的俯视图。
图6是本发明的第二变形例的下侧半导体芯片的俯视图。
图7是本发明的第三变形例的下侧半导体芯片的俯视图。
图8是以往例的半导体装置（没有隔墙）的剖视图。
图9是以往例的半导体装置（有隔墙）的剖视图。
图10是以往例的下侧半导体芯片的俯视图。
图11是以往例的下侧半导体芯片以及上侧半导体芯片在CoC连接之后的状态下的剖视图。
（附图标记的说明）
1树脂；2基底基板；3焊料球；4底部填充树脂；5上侧半导体芯片；6下侧半导体芯片；7粘接剂；8凸块；9外部电极；10键合线；12隔墙。
具体实施方式
以下，参照图1～图7对本发明的实施方式进行说明。其中，在实施方式中，对同一结构要素标注同一附图标记，并省略了实施方式之间的重复说明。
图1是本发明的一个实施方式的半导体装置的剖视图。该半导体装置以搭载在基底基板2上的下侧半导体芯片6和搭载在所述下侧半导体芯片6上的上侧半导体芯片5为主要的构成元件。
图2是本发明的一个实施方式的下侧半导体芯片6的俯视图。下侧半导体芯片6为矩形形状，沿着它的四边在表面上配置有外部电极9。虽然在图中多个外部电极9沿着边配置成一列，但也可以配置成两列或交错地排列。另外，在与上侧半导体芯片5电连接之处配置有矩阵状的内部电极80。
以下，结合制造工序对各部件加以说明。
下侧半导体芯片6用硅基板形成，在其表面上既可以形成集成电路，也可以不形成集成电路。但无论哪种情况，最上层都形成例如氮化硅膜，其上例如利用铜薄膜形成外部电极9、内部电极80、以及连接它们的布线（未图示）。在本实施例中，在铜布线等上形成有厚5μm的聚酰亚胺绝缘膜，在该聚酰亚胺绝缘膜上形成有露出外部电极9、内部电极80、由铜薄膜形成的虚设布线（其上形成隔墙12）的开口。由铜薄膜形成的虚设布线也可以与外部电极9、内部电极80、以及连接它们的布线同时地形成。聚酰亚胺绝缘膜例如用旋涂法进行涂覆，而开口利用蚀刻而形成。通过形成聚酰亚胺绝缘膜，能够防止连接外部电极9与内部电极80的、由铜薄膜等形成的布线等的损伤，能够阻隔引起所谓的软错误（soft error）的α射线。
在下侧半导体芯片6上形成的内部电极80具有例如直径20μm的八边形等任意形状的铝焊盘，它们排列成例如30×30的矩阵状。排列的间距例如为40μm。
下侧半导体芯片6表面的外部电极9按每边进行分组，以包围分组后的每个外部电极9的方式，在从聚酰亚胺绝缘膜的開口部露出的铜薄膜的虚设布线上形成隔墙12。隔墙12不仅包围组的周围，也以梯子状形成在相邻的外部电极9之间。在下侧半导体芯片6的四个角附近有隔墙图案的间断，此处形成使底部填充树脂4流向芯片外周的空隙13。隔墙由焊料形成，其粗细为45～55μm，高度为15μm～25μm。更优选地，隔墙的粗细为50μm，高度为20μm。在内部电极80的表面上，焊料层经也是由例如由镍形成的金属阻挡层而与隔墙同时地例如通过电镀来形成。另外，上述说明是基于下侧半导体芯片6来进行的，但内部电极80表面的焊料层与隔墙是在形成有多个下侧半导体芯片6的晶片状态下形成的，之后对多个下侧半导体芯片6进行单片化，而在对下侧半导体芯片6进行单片化后，进行后述的与上侧半导体芯片5的接合、底部填充树脂的填充工序。
图3是本发明的一个实施方式的下侧半导体芯片以及上侧半导体芯片在CoC连接之前的状态下的剖视图。在下侧半导体芯片6的表面上，均由焊料形成的隔墙12与内部电极80表面的焊料层81突出出来。另一方面，在已经形成了集成电路的上侧半导体芯片5的表面电极上形成有焊料层82。使焊料层81与焊料层82对位并将上侧半导体芯片5与下侧半导体芯片6进行CoC连接。此时的加热温度为比焊料的熔点高的260℃左右，焊料层81与焊料层82熔化而结合，如图4所示，成为鼓状（drum stick）的凸块8。
针对CoC连接后的半导体装置，在将温度维持在100℃左右的状态下向上侧半导体芯片5与隔墙12之间滴注底部填充树脂4。底部填充树脂4采用环氧树脂。结果，下侧半导体芯片6与上侧半导体芯片5之间以及凸块8会因底部填充树脂4的表面张力而被底部填充树脂4覆盖（图1）。此时，即使由于底部填充树脂4的量多、或者隔墙12与上侧半导体芯片5的距离小的原因，底部填充树脂4看上去要从隔墙12的上面溢出，底部填充树脂4也会通过间隙13向下侧半导体芯片6的外周侧逃逸。结果，底部填充树脂4不会流出到外部电极9上。另外，由于隔墙12覆盖外部电极9的周围，因此逃逸到下侧半导体芯片6的外周侧的底部填充树脂4也不会迂回而流到外部电极9上。由于底部填充树脂通常具有热固化性，因此若温度升高到150℃则底部填充树脂4会固化。此处，虽然也存在由于底部填充树脂4的流动，向隔墙12施加变形压力的情况，但是由于隔墙12形成为梯子状，因此铜薄膜的虚设布线与焊料的接触面积增大，紧贴性提高，因此不必担心隔墙12的形状走样。
接下来，下侧半导体芯片6经由粘接剂7而搭载在基底基板2上。下侧半导体芯片6的周边部的外部电极9与基底基板2的电极通过键合线10而电连接。另外，在基底基板2上以包围上侧半导体芯片5、下侧半导体芯片6的方式形成树脂1。树脂1是环氧树脂。最后，在基底基板2的背面形成在向电路印刷基板安装时所使用的焊料球3。
图5是本发明的第一变形例的下侧半导体芯片61的俯视图。与图2的下侧半导体芯片6的区别在于隔墙121的图案。在第一变形例的下侧半导体芯片61上，沿着四个边的各边的外部电极9分别被分组，分组后的外部电极9被隔墙121包围，在各个外部电极9之间未插入隔墙图案。在下侧半导体芯片6的四个角附近有隔墙121的图案的间断，在此形成使底部填充树脂4向芯片外周流动的间隙13。据此也能够实现本发明的目的。
图6是本发明的第二变形例的下侧半导体芯片62的俯视图。与图2的下侧半导体芯片6的区别在于隔墙122的图案。在第二变形例的下侧半导体芯片62上，沿着四个边的各边的外部电极9的图案上有空缺而形成了空隙132。被空隙132分离的外部电极9的组被各自不同的隔墙122的图案包围。由于在该结构中形成了大的空隙132，因此与上述实施方式相比较，能够使大量的底部填充树脂4向下侧半导体芯片62的外周逃逸，能够防止底部填充树脂4流出到外部电极9上。
图7是本发明的第三变形例的下侧半导体芯片63的俯视图。与图2的下侧半导体芯片6的区别在于外部电极9的排列以及隔墙123的图案。在第三变形例中，外部电极9交错状地排列成两列，各个外部电极9被隔墙123的图案单独地包围。由于在该结构中，朝向下侧半导体芯片的外周形成多个空隙133，因此与上述实施方式相比较，能够使大量的底部填充树脂4向下侧半导体芯片63的外周逃逸，能够防止底部填充树脂4流出到外部电极9上。
以上，对本发明的实施方式以及各种变形例进行了说明，但本发明并不局限于上述方式，只要不脱离本发明的宗旨，还可以有更多的变形。例如，隔墙由焊料形成，且与焊料凸块同时地形成，但也可以取代焊料地，用聚酰亚胺、环氧树脂的树脂片材形成。外部电极以及内部电极的图案能够进行各种各样的变形。
在本发明的一个实施方式或者各种变形例中，能够实现以下的任一效果。
（1）根据本发明，能够提供不阻碍外部电极与键合线的电接触、不对小型化以及量产化造成障碍的CoC连接的半导体装置及其制造方法。
（2）在本发明中，在将焊料用作隔墙的情况下，由于能够同时地形成内部电极上的焊料凸块与隔墙，因此能够使制造工序简化。
（3）在本发明中，将焊料用作隔墙，在隔墙的图案上进行创新，据此能够提高其与下层的紧贴性，防止隔墙的脱落。

Claims (7)

1.一种半导体装置，其特征在于，具有：
矩形形状的下侧半导体元件；
第一绝缘膜，形成在所述下侧半导体元件表面上；
多个外部电极，所述多个外部电极沿着所述第一绝缘膜的边而排列并形成在所述所述第一绝缘膜上；
多个内部电极，所述多个内部电极经由多个布线图案与所述多个外部电极分别电连接，并且排列而形成在所述第一绝缘膜上；
第二绝缘膜，为形成在所述布线图案上的薄膜，所述多个内部电极以及所述多个外部电极位置的区域是开口了的；
隔墙图案，所述隔墙图案形成为包围所述多个外部电极中的每一个或每多个；
上侧半导体元件，所述上侧半导体元件以多个端子分别与所述多个内部电极电连接的方式搭载在所述下侧半导体元件上；以及
树脂，所述树脂形成为滴注并流入所述下侧半导体元件与所述上侧半导体元件之间的方式，
其中，所述隔墙图案是在维持从滴注所述树脂的区域通向所述下侧半导体元件的外周的空隙的同时而形成的。
2.根据权利要求1所述的半导体装置，其特征在于，所述隔墙图案由焊料形成，且与形成在所述内部电极上的焊料凸块同时地形成。
3.根据权利要求1所述的半导体装置，其特征在于，所述隔墙图案形成为以将所述多个外部电极按每多个进行包围的方式，并且所述隔墙图案也形成在所述多个外部电极的各个之间。
4.一种半导体装置的制造方法，其特征在于，具有：
在矩形形状的下侧半导体元件表面上形成第一绝缘膜的工序，
在所述第一绝缘膜上形成多个布线图案的工序，
形成沿着所述第一绝缘膜的边而排列的多个外部电极、在所述第一绝缘膜上排列的多个内部电极、在第一绝缘膜上将所述多个外部电极与所述多个内部电极分别电连接的布线图案的工序，
在所述多个布线图案上形成第二绝缘膜的工序，所述第二绝缘膜为薄膜，所述第二绝缘膜的、所述多个内部电极以及所述多个外部电极的区域是开口了的，
以将所述多个外部电极中的每一个或每多个进行包围的方式形成具有空隙的隔墙图案的工序；
以将上侧半导体元件的多个端子分别与所述多个内部电极电连接的方式在所述下侧半导体元件上搭载所述上侧半导体元件的工序；以及
以流入所述下侧半导体元件与所述上侧半导体元件之间的方式滴注而形成树脂的工序，
其中，树脂经由所述空隙滴注到所述下侧半导体元件的外周。
5.根据权利要求4所述的半导体装置的制造方法，其特征在于，所述隔墙图案由焊料形成，并且与形成在所述内部电极上的焊料凸块同时地形成。
6.根据权利要求4所述的半导体装置的制造方法，其特征在于，一边维持从滴注所述树脂的区域通向所述下侧半导体元件的外周的空隙，一边形成所述隔墙图案。
7.根据权利要求4所述的半导体装置的制造方法，其特征在于，以将所述多个外部电极按每多个进行包围的方式形成所述隔墙图案，并且在所述多个外部电极的各个之间也形成所述隔墙图案。
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