US20180226271A1 - Control of under-fill using a film during fabrication for a dual-sided ball grid array package - Google Patents

Control of under-fill using a film during fabrication for a dual-sided ball grid array package Download PDF

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US20180226271A1
US20180226271A1 US15/885,775 US201815885775A US2018226271A1 US 20180226271 A1 US20180226271 A1 US 20180226271A1 US 201815885775 A US201815885775 A US 201815885775A US 2018226271 A1 US2018226271 A1 US 2018226271A1
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under
film
packaging substrate
substrate
fill material
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US15/885,775
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Howard E. Chen
Hoang Mong Nguyen
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Skyworks Solutions Inc
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Skyworks Solutions Inc
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Priority to US15/885,775 priority Critical patent/US20180226271A1/en
Publication of US20180226271A1 publication Critical patent/US20180226271A1/en
Assigned to SKYWORKS SOLUTIONS, INC. reassignment SKYWORKS SOLUTIONS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, HOWARD E., NGUYEN, HOANG MONG
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Definitions

  • the present disclosure generally relates to fabrication of dual-sided packaged electronic modules.
  • the present disclosure relates to fabrication of packaged electronic modules such as radio-frequency (RF) modules.
  • RF circuits and related devices can be implemented in a packaged module.
  • Such a packaged module can then be mounted on a circuit board such as a phone board.
  • the present disclosure relates to a method of fabricating a packaged radio-frequency device.
  • the method includes mounting components to a first side of a packaging substrate.
  • the method also includes applying a film to a second side of a packaging substrate.
  • the method also includes mounting a lower component to the second side of the packaging substrate after application of the film.
  • the method also includes under-filling the lower component mounted on the second side of the packaging substrate with an under-fill agent.
  • the method also includes removing the film on the second side of the packaging substrate.
  • the method also includes mounting solder balls to the second side of the packaging substrate after removal of the film.
  • the film covers contact pads of the solder balls.
  • applying the film includes laser cutting openings in a tape adhesive and mounting strips to the film.
  • the method also includes applying the film includes covering a first area of the second side of the packaging substrate while a second area of the second side of the packaging substrate remains uncovered by the film.
  • the first area includes a plurality of contact pads for the solder balls.
  • the second area includes a die area where the lower-component is mounted.
  • a size of a keep out zone is reduced by application and removal of the film.
  • the under-fill agent at least partially covers the film prior to removal of the film.
  • the film prevents the under-fill agent from coating contact pads of the solder balls.
  • the present disclosure relates to a method for manufacturing packaged radio-frequency devices.
  • the method includes applying a film to an underside of a packaging substrate, the packaging substrate having an upper side with one or more upper components mounted thereto, the underside of the packaging substrate having a die area and a contact pad area having a plurality of contact pads for through-mold connections, application of the film including covering the contact pad area with the film while leaving the die area uncovered by the film.
  • the method also includes after applying the film, mounting one or more lower components within the die area so that there is a gap between the one or more lower components and the packaging substrate.
  • the method also includes after mounting the one or more lower components, depositing an under-fill material on the packaging substrate so that the under-fill material penetrates into the gap.
  • the method also includes after depositing the under-fill material, removing the film from the underside of the packaging substrate.
  • the method further includes mounting through-mold connections to the underside of the packaging substrate after removal of the film.
  • the through-mold connections include solder balls.
  • the method further includes singulating individual units from the packaging substrate to yield a plurality of dual-sided packages.
  • the under-fill material includes a sealing resin or an epoxy. In some embodiments, the method further includes curing the under-fill material. In some embodiments, applying the film includes laser cutting openings in a tape adhesive and mounting strips to the film.
  • the film is configured to control distribution of the under-fill material during deposition of the under-fill material.
  • the under-fill material contacts the film.
  • removing the film includes removing a portion of the under-fill material that covers the film.
  • removing the film further includes leaving the under-fill material deposited in the die area.
  • the present disclosure relates to a method of fabricating a packaged radio-frequency (RF) device.
  • the method includes mounting components to a first side of a packaging substrate.
  • the method also includes mounting a lower component to a second side of the packaging substrate.
  • the method also includes under-filling the lower component mounted on the second side of the packaging substrate with an under-filling agent.
  • the method also includes deflashing a portion of the under-filling agent.
  • the method also includes mounting solder balls to the second side of the packaging substrate after the portion of the under-filling agent has been deflashed.
  • the portion of the under-filling agent that is deflashed includes under-filling agent that coats contact pads of the solder balls.
  • deflashing includes removing a thin layer of the under-filling agent.
  • a size of a keep out zone is reduced by deflashing a portion of the under-filling agent prior to mounting the solder balls.
  • the second side of the packaging substrate includes a plurality of contact pads for mounting the solder balls.
  • the under-filling agent coats a portion of at least one of the plurality of contact pads.
  • deflashing includes removing the portion of the under-filling agent that coats the portion of the at least one of the plurality of contact pads.
  • the present disclosure relates to a method for manufacturing packaged radio-frequency devices.
  • the method includes mounting one or more lower components on an underside of a packaging substrate so that there is a gap between the one or more lower components and the packaging substrate, the packaging substrate having an upper side with one or more upper components mounted thereto, the underside of the packaging substrate having a die area and a contact pad area having a plurality of contact pads for through-mold connections.
  • the method also includes after mounting the one or more lower components, depositing an under-fill material on the packaging substrate so that the under-fill material penetrates into the gap.
  • the method also includes after depositing the under-fill material, deflashing a portion of the under-fill material that covers one or more targeted areas.
  • the method further includes mounting through-mold connections to the underside of the packaging substrate after deflashing the portion of the under-fill material.
  • the through-mold connections include solder balls.
  • the methods further includes singulating individual units from the packaging substrate to yield a plurality of dual-sided packages.
  • the under-fill material includes a sealing resin or an epoxy. In some embodiments, the method further includes curing the under-fill material. In some embodiments, the one or more targeted areas includes a portion of the contact pad area. In some embodiments, deflashing includes removing a thin layer of the under-fill material. In some embodiments, a size of a keep out zone is reduced by deflashing a portion of the under-fill material prior to mounting any through-mold connections to the underside of the packaging substrate.
  • the under-fill material coats a portion of the contact pad area.
  • deflashing includes removing the portion of the under-fill material that coats the portion of the contact pad area.
  • the present disclosure relates to a packaging substrate for a packaged radio-frequency (RF) device.
  • the packaging substrate includes an insulating material forming a first side and a second side, the second side forming contact points for a ball grid array and a lower component, the contact points exposing electrically conducting material on the second side, the second side also forming a dam on the insulating material forming an area to receive under-fill agent during an under-fill process, the dam including a feature configured to block the spread of under-fill material during an under-fill process.
  • the packaging substrate also includes one or more conducting layers formed within the insulating material.
  • the packaging substrate also includes conducting paths electrically coupling contact pads formed on the insulating material to one of the one or more conducting layers.
  • the dam is formed using a solder mask during fabrication of the packaging substrate. In some embodiments, the dam is photolithographically defined in the original substrate manufacturing process. In some embodiments, the dam includes a plurality of outcroppings. In some embodiments, the dam includes continuous elevated structures. In some embodiments, the dam includes a plurality of disconnected elongated raised features. In some embodiments, the dam defines a keep out region that includes contact points for the lower component and excludes contact points for the ball grid array. In some embodiments, the dam is configured to surround the contact points for the ball grid array.
  • the present disclosure relates to a method of fabricating a packaged radio-frequency (RF) device.
  • the method includes mounting components to a first side of a packaging substrate.
  • the method also includes mounting a lower component to a second side of the packaging substrate.
  • the method also includes mounting solder balls to the second side of the packaging substrate.
  • the method also includes forming a dam on a second side of the packaging substrate after mounting the lower component and after mounting the solder balls.
  • the method also includes under-filling the lower component mounted on the second side of the packaging substrate with an under-fill material such that the under-fill material at least partially contacts the dam formed on the packaging substrate.
  • the dam is formed using an application method that includes jetting or needle dispensing. In some embodiments, the dam is configured to limit the distribution of the under-fill material to maintain the under-fill material a targeted distance from the solder balls while providing targeted coverage under and around the lower component. In some embodiments, the method further includes singulating individual units from the packaging substrate to yield a plurality of dual-sided packages. In some embodiments, the under-fill material includes a sealing resin or an epoxy. In some embodiments, the method further includes curing the under-fill material.
  • the present disclosure relates to a method of fabricating a packaged radio-frequency (RF) device.
  • the method includes mounting components to a first side of a packaging substrate.
  • the method also includes forming a dam on a second side of the packaging substrate.
  • the method also includes mounting a lower component to a second side of the packaging substrate after forming the dam.
  • the method also includes mounting solder balls to the second side of the packaging substrate after forming the dam.
  • the method also includes under-filling the lower component mounted on the second side of the packaging substrate with an under-fill material such that the under-fill material at least partially contacts the dam formed on the packaging substrate.
  • the dam is formed using an application method that includes screen printing, jetting, or needle dispensing.
  • the dam is configured to limit the distribution of the under-fill material to maintain the under-fill material a targeted distance from the solder balls while providing targeted coverage under and around the lower component.
  • the method further includes singulating individual units from the packaging substrate to yield a plurality of dual-sided packages.
  • the under-fill material includes a sealing resin or an epoxy. In some embodiments, the method further includes curing the under-fill material.
  • the present disclosure relates to a packaging substrate for a packaged radio-frequency (RF) device.
  • the packaging substrate includes an insulating material forming a first side and a second side, the second side forming contact points for a ball grid array and a lower component, the contact points exposing electrically conducting material on the second side, the second side also forming trenches in the insulating material that include a feature to receive under-fill agent during an under-fill process.
  • the packaging substrate also includes one or more conducting layers formed within the insulating material.
  • the packaging substrate also includes conducting paths electrically coupling contact pads formed on the insulating material to one of the one or more conducting layers.
  • the trenches are formed using a solder mask during fabrication of the packaging substrate. In some embodiments, the trenches do not expose electrically conducting material on the second side. In some embodiments, the trenches form continuous trench structures. In some embodiments, the trenches form a plurality of disconnected elongated trenches. In some embodiments, the trenches form a plurality of voids in the substrate. In some embodiments, the trenches define a keep out region that includes contact points for the lower component and excludes contact points for the ball grid array. In some embodiments, the substrate is configured to be singulated to yield a plurality of dual-sided packages.
  • the present disclosure relates to a method of fabricating a packaged radio-frequency (RF) device.
  • the method includes forming a trench in insulating material of a packaging substrate, the trench formed on an underside of the packaging substrate.
  • the method also includes mounting components to an upper side of the packaging substrate.
  • the method also includes mounting a lower component to the underside of the packaging substrate.
  • the method also includes mounting solder balls to the underside of the packaging substrate.
  • the method also includes under-filling the lower component mounted on the second side of the packaging substrate with an under-fill material such that the under-fill material at least partially fills the trench formed in the insulating material of the packaging substrate.
  • the trench is configured to limit the distribution of the under-fill material to maintain the under-fill material a targeted distance from the solder balls while providing targeted coverage under and around the lower component.
  • the method further includes singulating individual units from the packaging substrate to yield a plurality of dual-sided packages.
  • the under-fill material includes a sealing resin or an epoxy.
  • the method further includes curing the under-fill material.
  • forming the trench includes using a solder mask process.
  • the trench includes continuous trench structures.
  • the trench includes a plurality of disconnected elongated trenches.
  • the trench includes a plurality of voids in the substrate.
  • forming the trench does not penetrate through the insulating material to a conductive layer. In some embodiments, the trench does not include conductive material. In some embodiments, the trench defines a keep out region that includes contact points for the lower component and excludes contact points for the solder balls.
  • the present disclosure relates to a method of fabricating a packaged radio-frequency (RF) device.
  • the method includes mounting components to a first side of a packaging substrate.
  • the method also includes coating solder balls with a fluxing agent.
  • the method also includes attaching the solder balls to a second side of the packaging substrate.
  • the method also includes encapsulating the solder balls with an encapsulant that forms an obtuse angle with the packaging substrate.
  • the method also includes attaching a lower component to the second side of the packaging substrate.
  • the method also includes under-filling the lower component mounted on the second side of the packaging substrate with an under-filling agent such that the under-filling agent contacts the encapsulant.
  • the encapsulant is a polymer. In some embodiments, the encapsulant is not removed in a cleaning process following attachment of the solder balls to the packaging substrate. In some embodiments, the encapsulant forms an obtuse angle to the solder balls. In some embodiments, the under-filling agent contacts the encapsulant and not the solder balls. In some embodiments, the method further includes singulating individual units from the packaging substrate to yield a plurality of dual-sided packages.
  • the present disclosure relates to a method for manufacturing packaged radio-frequency devices.
  • the method includes mounting one or more lower components within a die area on an underside of a packaging substrate so that there is a gap between the one or more lower components and the packaging substrate, the packaging substrate having an upper side with one or more upper components mounted thereto, the underside of the packaging substrate having the die area and a contact pad area having a plurality of contact pads for through-mold connections.
  • the method also includes mounting the solder balls to the underside of the packaging substrate, the solder balls being coated with a fluxing agent that leaves behind a material that encapsulates the base of each solder balls, the material forming an encapsulant.
  • the method also includes after mounting the solder balls, depositing an under-fill material on the packaging substrate so that the under-fill material penetrates into the gap.
  • the encapsulant forms an obtuse angle with a surface of the underside of the packaging substrate and with a surface of the solder balls.
  • the obtuse angle is configured to reduce a surface energy driving force for capillary action of the under-fill material.
  • the method further includes singulating individual units from the packaging substrate to yield a plurality of dual-sided packages.
  • the under-fill material includes a sealing resin or an epoxy. In some embodiments, the method further includes curing the under-fill material.
  • the encapsulant is configured to control distribution of the under-fill material during deposition of the under-fill material. In further embodiments, the under-fill material contacts the encapsulant.
  • the material is configured so that it is not removed during a cleaning process that follows solder ball attach reflow.
  • the material is a polymer.
  • the encapsulant is configured to reduce capillary action causing the under-fill material to wick around the solder balls.
  • the present disclosure relates to a packaging substrate for a packaged radio-frequency (RF) device.
  • the packaging substrate includes an insulating material forming a first side and a second side, the second side forming contact points for a ball grid array and a lower component, the contact points exposing electrically conducting material on the second side, the second side also forming trenches in the insulating material that include a feature to receive under-fill agent during an under-fill process, the second side also forming a dam on the insulating material forming an area to receive under-fill agent during an under-fill process, the dam including a feature configured to block the spread of under-fill material during an under-fill process.
  • the packaging substrate also includes one or more conducting layers formed within the insulating material.
  • the packaging substrate also includes conducting paths electrically coupling contact pads formed on the insulating material to one of the one or more conducting layers.
  • the present disclosure relates to a method of fabricating a packaged radio-frequency (RF) device.
  • the method includes forming a trench in insulating material of a packaging substrate, the trench formed on an underside of the packaging substrate.
  • the method also includes forming a dam on the underside of the packaging substrate.
  • the method also includes mounting components to an upper side of a packaging substrate.
  • the method also includes mounting a lower component to the underside of the packaging substrate.
  • the method also includes mounting solder balls to the underside of the packaging substrate.
  • the method also includes under-filling the lower component mounted on the second side of the packaging substrate with an under-fill material such that the under-fill material at least partially flows into the trench or contacts the dam formed on the packaging substrate.
  • the present disclosure relates to a method of fabricating a packaged radio-frequency (RF) device.
  • the method includes forming a dam on an underside of the packaging substrate.
  • the method also includes mounting components to an upper side of the packaging substrate.
  • the method also includes mounting a lower component to the underside of the packaging substrate.
  • the method also includes under-filling the lower component mounted on the second side of the packaging substrate with an under-fill material such that the under-fill material at least partially flows into the trench or contacts the dam formed on the packaging substrate.
  • the method also includes deflashing a portion of the under-filling agent.
  • the method also includes mounting solder balls to the underside of the packaging substrate.
  • the present disclosure relates to a method of fabricating a packaged radio-frequency (RF) device.
  • the method includes forming a trench in insulating material of a packaging substrate, the trench formed on an underside of the packaging substrate.
  • the method also includes mounting components to an upper side of the packaging substrate.
  • the method also includes mounting a lower component to the underside of the packaging substrate.
  • the method also includes under-filling the lower component mounted on the second side of the packaging substrate with an under-fill material such that the under-fill material at least partially flows into the trench or contacts the dam formed on the packaging substrate.
  • the method also includes deflashing a portion of the under-filling agent.
  • the method also includes mounting solder balls to the underside of the packaging substrate.
  • FIG. 1 illustrates a dual-sided package having a shielded package and a lower component mounted thereto.
  • FIG. 2 illustrates another example of a dual-sided package having one or more lower components that can be mounted under a shielded package, generally within a volume defined on an underside of the shielded package.
  • FIGS. 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, and 3I illustrate a typical process flow for fabricating a dual-sided ball grid array package.
  • FIGS. 4A, 4B, 4C, 4D, 4E, and 4F illustrate a modified fabrication process that uses a film to control distribution of an under-fill material.
  • FIGS. 5A, 5B, 5C, and 5D illustrate a modified fabrication process using under-fill deflash to control the distribution of an under-fill material.
  • FIGS. 6A, 6B, 6C, and 6D illustrate a modified fabrication process that includes using a dam to contain an under-fill material.
  • FIGS. 7A and 7B illustrate a modified fabrication process that uses a substrate with trenches on the underside of the substrate.
  • FIGS. 8A and 8B illustrate a modified fabrication process using encapsulant to control the distribution of an under-fill material.
  • FIGS. 9A and 9B illustrate a panel with a dam or a series of raised features in conjunction with a trench or a series of valleys, holes, or the like in a substrate, wherein the dam and the trench are configured to control the distribution of an under-fill material.
  • Described herein are technologies related to fabrication of dual-sided packaged electronic modules, such as radio-frequency modules, and devices, systems, and methods to control the distribution of an under-fill material between one or more components and a packaging substrate.
  • the disclosed technologies include applying a film to targeted areas on the packaging substrate prior to under-filling one or more components and prior to attaching solder balls.
  • the film can be applied to the packaging substrate prior to under-filling, the region that receives under-fill material can be controlled to a greater degree.
  • the film can be removed to expose clean contact pads for the solder balls.
  • the solder balls are not present during under-fill, there is little capillary action drawing material away from the components being under-filled. This can advantageously reduce the frequency of voids under the components being under-filled. Accordingly, the disclosed systems, devices, and methods control under-fill for dual-sided ball grid array packages using a film prior to attaching solder balls of the ball grid array.
  • the disclosed technologies also include under-filling one or more components and deflashing a portion of the under-fill to remove under-fill material prior to attaching solder balls.
  • the deflashing step removes a thin layer of under-fill material that may have coated contact pads for the ball grid array.
  • the solder balls are not present during under-fill, there is little capillary action drawing material away from the components being under-filled. This can advantageously reduce the frequency of voids under the components being under-filled. Accordingly, the disclosed systems, devices, and methods control under-fill for dual-sided ball grid array packages using under-fill deflash prior to attaching solder balls of the ball grid array.
  • the disclosed technologies also include using a dam on a packaging substrate.
  • the dam on the packaging substrate is configured to prevent or limit the flow of a capillary under-fill material.
  • the dam can form a controlled area so that the capillary under-fill material fills or flows substantially free within this area but does not flow outside of the area. This can prevent or limit the capillary under-fill material from flowing onto or contacting other components or elements on the packaging substrate, such as solder balls of a ball-grid array.
  • the disclosed systems, devices, and methods control under-fill for dual-sided ball grid array packages using a dam on a packaging substrate.
  • the disclosed technologies also include forming a trench in a packaging substrate.
  • the trench in the packaging substrate is configured to prevent or limit the flow of a capillary under-fill material.
  • the trench can form a controlled area so that the capillary under-fill material fills or flows substantially free within this area but does not flow outside of the area. This can prevent or limit the capillary under-fill material from flowing onto or contacting other components or elements on the packaging substrate, such as solder balls of a ball-grid array.
  • the disclosed systems, devices, and methods control under-fill for dual-sided ball grid array packages using a trench on a packaging substrate.
  • the disclosed technologies also include using an encapsulant on solder balls to limit distribution of an under-fill agent.
  • the encapsulant can be used in the ball attach process.
  • the fluxing agent leaves behind a material that encapsulates the base of each solder ball.
  • the encapsulant forms an obtuse angle with the substrate surface and with the ball surface. This reduces the tendency of the under-fill material to wick around the solder balls by capillary action. This can prevent or limit the capillary under-fill material from flowing onto or contacting other components or elements on the packaging substrate, such as solder balls of a ball-grid array. Accordingly, the disclosed systems, devices, and methods control under-fill for dual-sided ball grid array packages using an encapsulant on the solder balls.
  • RF circuits and related devices can be implemented in a packaged module. Such a packaged module can then be mounted on a circuit board such as a phone board.
  • Certain packaged modules can include dual-sided packages, with components mounted over and under a packaging substrate.
  • Such packaged modules can include an array of solder balls, or a ball grid array, on an underside of the packaging substrate, which collectively may be referred to as a dual-sided ball grid array (DS-BGA).
  • DS-BGA dual-sided ball grid array
  • FIG. 1 illustrates a dual-sided package 100 having a shielded package 102 and a lower component 104 mounted thereto.
  • a lower side of the shielded package 102 can include a side 103 of a packaging substrate that is to be mounted onto a circuit board such as a phone board.
  • the shielded package 102 can include such a packaging substrate and one or more upper components mounted on its upper side (when oriented as shown in FIG. 1 ).
  • the dual-sided property can include such upper component(s) mounted over the substrate and lower component(s) mounted under the substrate.
  • the package can be shielded using any suitable shielding method.
  • the package 100 can be shielded using a plurality of shielding wires that are electrically coupled to a ground plane within the packaging substrate.
  • the package 100 can be shielded using a conformal coating that is electrically coupled to a ground plane within the packaging substrate. Any suitable combination of features can be used to define a shielded volume or region. Such configurations can be implemented to provide shielding functionality between regions within and outside of the shielded package 100 , and/or between regions that are both within the shielded package 100 .
  • a lower component can include any device that can be mounted on the substrate and/or the circuit board.
  • a device can be an active radio-frequency (RF) device or a passive device that facilitates processing of RF signals.
  • RF radio-frequency
  • a passive device can include a die such as a semiconductor die, an integrated passive device (IPD), a surface-mount technology (SMT) device, and the like.
  • the lower component as described herein can be electrically coupled to the one or more upper components through, for example, the substrate.
  • FIG. 2 illustrates another example of a dual-sided package 200 having one or more lower components 204 that can be mounted under a shielded package 202 , generally within a volume defined on an underside of the shielded package.
  • a set of through-mold connections e.g., one or more through-mold connections
  • the set of through-mold connections may define a volume on the underside of the shielded package 202 .
  • a volume 208 under a shielded package 202 is shown to be defined by the underside of the shielded package 202 and solder balls 206 of a ball grid array (BGA).
  • the BGA may be a set of through-mold connections.
  • each solder ball 206 of the BGA may be a through-mold connection in the set of through-mold connections.
  • Other examples of through-mold connections include, but are not limited to solder balls, pillars, columns, posts, pedestals, etc.
  • the through-mold connections described herein may also be referred to as contact features.
  • the solder balls 206 allow the dual-sided package 200 to be mounted on a circuit board 210 such as a phone board.
  • the solder balls 206 can be configured so that when mounted to the circuit board 210 , there is sufficient vertical space between the upper surface of the circuit board 210 and the lower surface of the shielded package 202 for the lower component 204 .
  • the volume 208 can be at least partially filled with an over-mold 205 .
  • the over-mold 205 substantially encapsulates the lower component 204 .
  • at least a portion of the solder balls 206 may be exposed through the over-mold 205 . Exposing at least a portion of the solder balls 206 may provide a connection (e.g., an electrical and/or thermal connection) through the over-mold 205 .
  • the solder balls 206 may provide a connection (e.g., an electrical connection) to the lower component 204 and/or upper components 224 , 226 in the shield package 202 .
  • solder (or other conductive material) may be applied to the exposed portion of the solder balls 206 to form a connection (e.g., electrical connection) with the circuit board 210 .
  • the over-mold 205 may also be referred to as an over-mold structure.
  • the over-mold 205 and/or the solder balls 206 (e.g., the exposed portions of the solder balls 206 ) may form a land grid array (LGA) type/style package.
  • LGA land grid array
  • a close-up view of the solder ball 206 is also illustrated in FIG. 2 .
  • the bottom of the shielded package includes a pad 215 .
  • the pad 215 may be a metallic pad (or some other material) that may provide electrical and/or thermal conductivity between the solder ball 206 and components of the shield package 202 and/or the lower component 204 .
  • Solder mask 214 may be deposited over portions of the pad 215 to define a location where the solder ball 206 may be formed.
  • the solder ball 206 may be formed (e.g., implemented, formed, dropped, etc.) on top of the pad 215 and the solder mask 214 .
  • the dual-sided package 200 may be installed on the circuit board 210 using the solder ball 206 .
  • the solder ball 206 may be attached to the circuit board 210 (e.g., may be installed, mounted, fixed, etc., to the circuit board 210 ) via connection 216 .
  • the connection 216 may include solder material 221 and pad 219 .
  • the solder material 221 may be solder material from the solder ball 206 that is deposited/melted onto the pad 219 when the dual-sided package 200 is attached to the circuit board. For example, during a reflow process, heat may be applied to melt at least a portion of the solder ball 206 to form the solder material 221 .
  • the solder material 221 may also include additional material that is formed, implemented, deposited, etc., over the solder ball 206 .
  • the pad 219 may be part of the circuit board 210 .
  • the pad 219 may provide electrical and/or thermal conductivity between the dual-sided package 200 and other components/circuits attached to the circuit board 210 (not illustrated in the figures).
  • the pad 219 may include solder material.
  • the over-mold 205 has a surface 212 (facing downward toward the circuit board 210 ).
  • the surface 212 may not contact (e.g., may not physically touch) the surface 213 of the circuit board 210 .
  • a gap 209 may be present between the surface 212 and the surface 213 .
  • the gap 209 may help protect the lower component 204 from damage when there are linear displacements of the dual-sided package 200 due to flexing or dropping.
  • the gap 209 may help protect the lower component 204 from damage as the dual-sided package 200 is installed on the circuit board 200 (e.g., may prevent the lower component 204 from contacting the surface 213 of the circuit board 210 during installation/mounting of the dual-sided package).
  • the portion of the over-mold material 205 that covers the lower component 204 may provide additional protection from damage when there are linear displacements of the dual-sided package 200 due to flexing or dropping.
  • the over-mold material 205 may also prevent the lower component 204 from contacting the surface 213 of the circuit board 210 during installation/mounting of the dual-sided package.
  • the gap 209 may also allow the dual-sided package 200 to adapt to process/manufacturing variations when the dual-sided package 200 is installed on the circuit board 210 . For example, different temperatures may be used to melt the solder ball 206 during installation of the dual-sided package.
  • the gap 209 may help ensure that the dual-sided package 200 is properly installed by providing enough distance between the surface 212 (of over-mold 205 ) and the surface 213 (of circuit board 210 ) while still allowing the solder material of the solder ball 206 to properly bond with the pad 219 of the circuit board 210 .
  • the over-mold 205 and/or the gap 209 may prevent the component 204 from contacting the surface 213 (of the circuit board 210 )
  • the dual-sided package 200 and/or the component 204 may still operate/function properly even if the component 204 does contact the surface 213 .
  • the component 204 may remain undamaged and/or operable even after contacting the surface 213 of the circuit board 210 .
  • the dual-sided ball grid array package 200 can include a packaging substrate 222 (e.g., a laminate substrate) and a plurality of components mounted thereon.
  • a packaging substrate 222 e.g., a laminate substrate
  • a first component 224 can be mounted on the upper surface of the packaging substrate 222
  • electrical connections between the component 224 and the packaging substrate 222 can be facilitated by, for example, wire-bonds 228 .
  • a second component 226 is shown to be mounted on the upper surface of the packaging substrate 222 in a die-attach configuration. Electrical connections between the component 226 and the packaging substrate 222 can be facilitated by, for example, die-attach features.
  • an under-fill can be provided between the lower component 204 and an underside of the dual-sided package 200 .
  • An under-fill 230 can be provided between the lower component 204 and the underside of the package 200 to provide, for example, a more secure mounting of the lower component 204 .
  • solder balls and/or a BGA solder balls and/or a BGA
  • solder balls and/or a BGA are examples of through-mold connections.
  • other types of through-mold connections e.g., pillars, columns, etc., may be used to define a volume on an underside of a shielded package and an over-mold may be implemented in the volume (on the underside of the shielded package).
  • a through-mold connection (or a set of through-mold connections) may be any structure and/or component that may be used to define a volume on the underside of a shielded package and/or may be used to support the shielded package above a surface.
  • a zone is required between solder ball(s) and integrated circuit chips, dies, or other such components.
  • This zone (sometimes referred to as a “keep out” zone) is a design rule that calls out a targeted minimum distance between solder ball and component.
  • the keep out zone facilitates meeting manufacturing quality and reliability requirements. Defects such as voids under the component (e.g., an IC chip) where there is no under-fill material, or contamination of the solder balls with undesired material can occur if the keep out zone design rule is violated. It is advantageous to reduce the size of the keep out zone because it can enhance product performance and/or reduce package size.
  • the overall package size can be reduced and/or the chip size can be increased if the size of the keep out zone can be reduced. Decreasing the package size or increasing chip size may result in additional or improved functionality per unit area on the final product motherboard to which the dual-sided ball grid array package is mounted. Accordingly, described herein are systems, devices, and methods that advantageously reduce the keep out zone between solder balls and the IC chip in a dual-sided ball grid array package. This results in greater functionality per unit area when the package is mounted to the final product motherboard.
  • Typical fabrication techniques attempt to reduce or minimize the IC chip-to-solder ball keep out zone by controlling the capillary under-fill dispense process. This may be controlled through the needle selection, the dispense volume, the number of dispense passes, and/or the dispense temperature.
  • the keep out zone on the dispense side of the chip may be about 700 ⁇ m, and may be about 200 ⁇ m on the other three sides of the chip.
  • FIGS. 3A-3I illustrate a process flow for fabricating a dual-sided ball grid array package.
  • FIGS. 3A-3F illustrate a process for completing a top side assembly of a laminate strip (e.g., surface mount, die attach, wire bond, molding, and marking).
  • FIGS. 3G-3I illustrate a process for completing a bottom side assembly and forming individual packages through singulation.
  • a conformal shield material stack may be applied to individual packages.
  • the present disclosure improves on this fabrication process by applying a film to the bottom side of the packaging substrate prior to under-filling to protect the contact pads of the solder balls of the ball grid array and to control the distribution of the under-filling material.
  • FIGS. 4A-4F the present disclosure improves on this fabrication process by applying a film to the bottom side of the packaging substrate prior to under-filling to protect the contact pads of the solder balls of the ball grid array and to control the distribution of the under-filling material.
  • FIGS. 4A-4F improves on this fabrication
  • the present disclosure improves on this fabrication process by under-filling and deflashing a portion of the under-fill material prior to adding the solder balls of the ball grid array. Moreover, as illustrated in FIGS. 6A-6D , the present disclosure improves on this fabrication process by forming a dam on the substrate to impede or prevent the capillary under-fill material from flowing into the solder balls. Furthermore, as illustrated in FIGS. 7A and 7B , the present disclosure improves on this fabrication process by forming a trench in the substrate to impede or prevent the capillary under-fill material from flowing into the solder balls. Additionally, as illustrated in FIGS. 8A and 8B , the present disclosure improves on this fabrication process by using an encapsulant on the solder balls to impede or prevent the under-fill material from flowing onto the solder balls.
  • FIGS. 3A-3I illustrate various stages of a fabrication process in which dual-sided features can be implemented in a panel format having an array of to-be-separated units, and separation of the array into individual units (also referred to as singulation).
  • FIGS. 3A-3I, 4A-4F, 5A-5D, 6A, 6B, 7A, 7B, 8A, and 8B can also be implemented for fabrication of dual-sided packages having other types of mounting features.
  • the disclosed fabrication processes can be utilized for manufacturing dual-sided packages described herein and in U.S. Pat. No. 9,381,529 and U.S. patent application Ser. No. 15/724,722 (each of which has been expressly incorporated by reference herein).
  • FIG. 3A illustrates a cross-section view of a panel 300 having a plurality of to-be-singulated units. For example, singulation can occur at boundaries depicted by dashed lines 360 so at to yield singulated individual units.
  • the panel 300 includes a substrate 305 on which components are to be mounted.
  • the substrate 305 can be a laminate substrate, a ceramic substrate (e.g., a low-temperature co-fired ceramic substrate), or the like.
  • the substrate 305 can include surface features 310 that may provide mechanical support.
  • the panel 300 includes conductive material 315 that is configured to provide electrical connections between conductive layers, surface-mount devices, chips, solder balls, and the like.
  • the conductive material 315 can form contact pads on the upper and lower sides of the substrate 305 to provide electrical contact points for surface mount devices, chips, solder balls, pillars, any combination of these, or the like. Vias can be formed in the substrate where the conductive material 315 provides an electrical connection between conductive layers in the panel 300 .
  • FIG. 3B illustrates mounting of surface mount technology (SMT) devices 320 such that conductive points on the devices 320 are electrically coupled to contact pads formed by the conductive material 315 on the panel 300 .
  • SMT surface mount technology
  • solder paste can be applied on the substrate 305 to allow mounting of one or more SMT devices 320 .
  • a reflow operation can be performed to melt the solder paste to solder the one or more SMT devices on their respective contact pads.
  • Solder residue from the reflow operation can be removed by running the substrates through a solvent or aqueous cleaning step, for example.
  • FIG. 3C illustrates mounting of a die or chip 325 .
  • adhesive 326 can be applied on one or more selected areas on the substrate 305 .
  • the die 325 can be positioned on the selected area with adhesive applied thereon.
  • the adhesive 326 between the die 325 and the die-mounting area can be cured to secure the die 325 .
  • FIG. 3D illustrates forming electrical connections between the die 325 and contact pads using wirebonds 327 .
  • the wirebonds 327 can provide electrical connections for signals and/or power to and from one or more circuits of the die 325 .
  • FIG. 3E illustrates forming an over-mold 330 over the SMT component(s) 320 , die(s) 325 , and any other upper component on the substrate 305 .
  • molding compound can be introduced from one or more sides of a molding volume to form an upper over-molded volume 330 .
  • the over-mold 330 may completely encapsulate the upper components 320 , 325 .
  • FIG. 3F illustrates an optional process of marking the over-mold 330 .
  • marking may be accomplished using laser etching or similar techniques.
  • FIG. 3G illustrates attaching a lower component 335 to the underside (which may face upward during fabrication) of the substrate 305 .
  • an array of solder balls 340 can be formed on the underside of the substrate 305 .
  • the lower component 335 may be attached for each unit after the array of solder balls 340 is formed, or vice versa.
  • the lower component 335 and the array of solder balls 340 may be attached, implemented, and/or formed substantially simultaneously.
  • FIG. 3H illustrates filling a gap between the lower component 335 and the substrate 305 with an under-fill agent 345 or an under-fill material (also referred to as under-filling).
  • an under-fill material 345 such as a sealing resin or epoxy, can be deposited on the substrate 305 and the under-fill material 345 can penetrate into the gap between the lower component 335 and the substrate 305 by capillary forces.
  • the coating shape and amount of under-fill agent 345 vary depending on the package size, pitch, and gap.
  • the under-fill material 345 can be cured to provide mechanical support to the lower component 335 , to provide advantageous thermal properties, to improve solder-ball bonding reliability under external stresses, and the like.
  • FIG. 3I illustrates singulating individual units to yield a plurality of dual-sided packages 350 substantially ready to be mounted to circuit boards.
  • the fabrication process illustrated in FIGS. 3A-3I can be improved by applying a film to the bottom side of the packaging substrate prior to adding the solder balls and prior to under-filling the lower component. Upon removal of the film, the solder balls can be added. The film protects the contact pads of the solder balls and controls the distribution of the under-filling agent.
  • FIGS. 4A-4F illustrate a modified fabrication process, replacing steps illustrated in FIGS. 3G and 3H .
  • FIG. 4A illustrates a substrate 305 with a die area 337 (e.g., for mounting one or more lower components) and a plurality of solder ball contact pads 342 .
  • a film 447 can be added to the substrate 305 to protect the solder ball contact pads 342 and to expose the die area 337 for mounting one or more lower components.
  • the illustration on the left is shown without the film 447 while the illustration on the right is shown with the film 447 .
  • FIG. 4B illustrates the substrate 305 with the film 447 covering the contact pads 342 prior to addition of the lower component 335 and solder balls 340 and prior to under-filling the lower component 335 .
  • the film can be used to control the distribution of the under-filling agent, thereby making it possible to reduce the size of the keep out zone.
  • the process for applying the film 447 to the bottom side of the packaging substrate 305 can be similar to the process used in shielding DS-BGA packages.
  • openings can be laser cut in a tape adhesive. Strips can then be mounted to the film so that the film can protect the contact pads of the ball grid array from under-fill runout.
  • FIG. 4C illustrates that, after application of the film 447 , the lower component 335 can be added, as described herein with reference to FIG. 3G .
  • the solder balls of the ball grid array are not mounted to the substrate 305 as described in FIG. 3G .
  • FIG. 4D illustrates that, after reflow and cleaning, the under-fill agent 345 can be applied as described herein with reference to FIG. 3H .
  • the under-fill agent 345 can be applied as described herein with reference to FIG. 3H .
  • the film 447 prevents the under-fill material 345 from coating the solder ball contact pads 342 .
  • FIG. 4E illustrates an additional process step of removing the film 447 .
  • Removing the film 447 can prevent the under-fill material 345 from coating contact pads 342 of the solder balls and/or can remove any under-fill material 345 that would have coated those contact pads 342 . In this way, the size and extent of the keep out zone can be controlled.
  • FIG. 4F illustrates that, after removal of the film 447 , the solder balls 340 can be added as described in FIG. 3G . The process can then proceed to reflow again and then to singulate the individual units, as described herein with reference to FIG. 3I .
  • the fabrication process illustrated in FIGS. 3A-3I can be improved by adding the solder balls after under-filling the lower component and deflashing excess under-fill to control the distribution of under-fill agent.
  • FIGS. 5A-5D illustrate a modified fabrication process, replacing steps described herein with reference to FIGS. 3G and 3H .
  • a lower component 335 is added as described in FIG. 3G .
  • the solder balls of the ball grid array are not mounted to the substrate 305 as described in FIG. 3G .
  • the under-fill material 345 is applied as described in FIG. 3H .
  • FIG. 5C illustrates an additional process step of deflashing the under-fill material 345 .
  • Deflashing is configured to remove a thin layer of under-fill material from targeted locations 347 on the substrate.
  • deflashing can remove under-fill material that may have coated the contact pads for the solder balls. In this way, the size and extent of the keep out zone can be controlled.
  • FIG. 5D illustrates that, after deflashing, the solder balls 340 can be added as described in FIG. 3G .
  • the fabrication process illustrated in FIGS. 3A-3I can be improved by forming a dam or a series of raised features on the substrate 305 , wherein the dam or similar features is configured to control the distribution of under-fill agent in the process step illustrated in FIG. 3H .
  • a panel 600 can be provided wherein the substrate 605 includes a dam 607 on the underside of the substrate 605 , wherein the dam 607 can be an integral part of the substrate 605 or formed on the substrate 605 at a later time.
  • the dam 607 provides a way to control the distribution of the under-fill agent during manufacturing of the disclosed double-sided ball grid array packages.
  • the dam 607 contains the capillary under-fill material and may prevent it from contacting or contaminating the solder balls 340 .
  • the dam 607 can provide a repeatable volume of material to flow under the lower component 335 (e.g., a die), which reduces the frequency of voiding under the lower component 335 .
  • dam 607 is illustrated on a single side of the solder balls 340 , it is to be understood that the dam 607 can be configured to surround the solder balls 340 .
  • the dam 607 can be configured to have raised features on a plurality of sides of the solder balls 340 .
  • the dam 607 can surround individual solder balls 340 and/or surround or enclose the area that contains the solder balls 340 .
  • the substrate 605 can be a laminate substrate, a ceramic substrate (e.g., a low-temperature co-fired ceramic substrate), or the like.
  • the substrate 605 can include surface features 610 that may provide mechanical support.
  • the panel 600 includes conductive material 615 that is configured to provide electrical connections between conductive layers, surface-mount devices, chips, solder balls, and the like.
  • the conductive material 615 can form contact pads on the upper and lower sides of the substrate 605 to provide electrical contact points for surface mount devices, chips, solder balls, pillars, any combination of these, or the like. Vias can be formed in the substrate 605 where the conductive material 615 provides an electrical connection between conductive layers in the panel 600 .
  • the dam 607 can form continuous elevated structures, a plurality of disconnected elongated raised features, or a plurality of outcroppings in the substrate 605 .
  • the dam 607 can define one or more keep out areas on the underside of the substrate 605 .
  • FIG. 6A illustrates that the dam 607 forms part of the substrate 605 .
  • the dam 607 can be formed during an additional solder mask process during fabrication of the substrate 605 .
  • the panel 600 includes a substrate 605 having insulating material forming an upper side and a lower side.
  • the substrate 605 forms voids in which conducting material electrically couples contact pads to conductive layers or other contact pads.
  • the substrate 605 forms a dam 607 (e.g., elevated features, connected raised features, disconnected raised features, etc.) in the insulating material to form a feature that can block the spread of under-fill material during an under-fill process.
  • the dam 607 can be photolithographically defined during the original substrate manufacturing process. Then, when assembling the bottom side of the panel 600 , the process flow illustrated in FIGS. 3A-3I can be used.
  • FIG. 6B illustrates that the dam 607 can be added to the substrate 605 during fabrication after the ball and die attach process steps, illustrated in FIG. 3G .
  • jetting or needle dispensing may be used.
  • FIG. 6C illustrates that the dam 607 can be added to the substrate 605 during fabrication before the ball and die attach process steps, illustrated in FIG. 3G .
  • screen printing, jetting, or needle dispensing may be used.
  • FIG. 6D illustrates the modified process of under-filling in the presence of the dam 607 , compared to the under-filling process illustrated in FIG. 3H .
  • the dam 607 limits the distribution of the under-fill material 345 to maintain the under-fill material 345 a targeted or desired distance from the solder balls 340 while still providing targeted coverage under and around the lower component 335 .
  • the fabrication process illustrated in FIGS. 3A-3I can be improved by forming a trench or a series of valleys, holes, or the like in the substrate 305 , wherein these trenches or similar features are configured to control the distribution of under-fill agent in the process step illustrated in FIG. 3H .
  • a panel 700 can be provided wherein the substrate 705 includes trenches 708 on the underside of the substrate 705 .
  • the trenches provide a way to control the distribution of the under-fill agent during manufacturing of the disclosed double-sided ball grid array packages.
  • the substrate 705 can be a laminate substrate, a ceramic substrate (e.g., a low-temperature co-fired ceramic substrate), or the like.
  • the substrate 705 can include surface features 710 that may provide mechanical support.
  • the panel 700 includes conductive material 715 that is configured to provide electrical connections between conductive layers, surface-mount devices, chips, solder balls, and the like.
  • the conductive material 715 can form contact pads on the upper and lower sides of the substrate 705 to provide electrical contact points for surface mount devices, chips, solder balls, pillars, any combination of these, or the like. Vias can be formed in the substrate 705 where the conductive material 715 provides an electrical connection between conductive layers in the panel 700 .
  • vias can be formed in the substrate 705 , but instead of providing conductive paths between conductive layers, the vias for the trenches 708 can provide a void in the substrate structure to receive under-fill agent during the under-fill processing step.
  • the trench 708 can be formed during a solder mask process during fabrication of the substrate 705 .
  • the trenches 708 can form continuous trench structures, a plurality of disconnected elongated trenches, or a plurality of voids or holes in the substrate 705 .
  • the trenches 708 can define one or more keep out areas on the underside of the substrate 705 .
  • the panel 700 includes a substrate 705 having insulating material forming an upper side and a lower side.
  • the substrate 705 forms voids in which conducting material electrically couples contact pads to conductive layers or other contact pads.
  • the substrate 705 forms trenches 708 (e.g., elongated voids) in the insulating material to form a feature that can receive under-fill material during an under-fill process.
  • the trenches 708 do not include conductive material or do not penetrate to a conductive layer.
  • FIG. 7B illustrates the modified process of under-filling in the presence of trenches 708 in the substrate 705 , compared to the under-filling process illustrated in FIG. 3H .
  • the trenches 708 limit the distribution of the under-fill material 345 to maintain the under-fill material 345 a targeted or desired distance from the solder balls 340 while still providing targeted coverage under and around the lower component 335 .
  • FIGS. 3A-3I can be improved by using a special material during the ball attach process illustrated in FIG. 3G .
  • a fluxing agent can be used on the solder balls 340 that leaves behind a material which encapsulates the base of each solder ball 340 , forming encapsulant 842 .
  • This material may be a polymer.
  • This material can be configured so that it is not removed during a cleaning process that follows solder ball attach reflow.
  • the encapsulant 842 forms an obtuse angle with the surface of the substrate 305 and with the surface of the solder balls 340 .
  • the under-fill material 845 When the under-fill material 845 is dispensed in the process step illustrated in FIG. 8B , it no longer has a tendency to wick around the solder balls 340 by capillary action.
  • the obtuse angles formed by the encapsulant 842 reduce the surface energy driving force for capillary action. This reduces or prevents the under-fill material from flowing around the solder balls 340 . Instead, the under-fill material 345 primarily flows under the lower component 335 (e.g., an IC chip).
  • FIGS. 3A-3I can be improved by combining features and techniques described herein with respect to FIGS. 4A-4F, 5A-5D, 6A-6D, 7A, 7B, 8A, and 8B .
  • a dam e.g., as described herein with reference to FIGS. 6A-6D
  • a trench e.g., as described herein with reference to FIGS. 7A and 7B
  • the dam can be used in conjunction with a film, deflashing, trench, and/or an encapsulant.
  • the trench can be used in conjunction with a film, deflashing, dam, and/or an encapsulant.
  • deflashing can be used in conjunction with a film, dam, trench, and/or an encapsulant.
  • the film can be used in conjunction with deflashing, dam, trench, and/or an encapsulant.
  • encapsulant can be used in conjunction with a film, dam, trench, and/or deflashing.
  • FIG. 9A illustrates a panel 900 with a dam 907 or a series of raised features in conjunction with a trench 908 or a series of valleys, holes, or the like in a substrate 905 , wherein the dam 907 and the trench 908 are configured to control the distribution of under-fill agent 345 .
  • the panel 900 can be provided wherein the substrate 905 includes the dam 907 on the underside of the substrate 905 , wherein the dam 907 can be an integral part of the substrate 905 or formed on the substrate 905 at a later time. Similarly, the substrate 905 includes the trench 908 on the underside of the substrate 905 .
  • the dam 907 and the trenches 908 provide a way to control the distribution of the under-fill agent 345 during manufacturing of the disclosed double-sided ball grid array packages.
  • the combination of the dam 907 and the trenches 908 contains the capillary under-fill material 345 and may prevent it from contacting or contaminating the solder balls 340 .
  • the combination of the dam 907 and the trenches 908 can provide a repeatable volume of material to flow under the lower component 335 (e.g., a die), which reduces the frequency of voiding under the lower component 335 .
  • the combination of the dam 907 and the trenches 908 is illustrated on a single side of the solder balls 340 , it is to be understood that the dam 907 and/or the trenches 908 can be configured to surround the solder balls 340 .
  • the substrate 905 is similar to the substrate 605 and 705 described herein with reference to FIGS. 6A-6D, 7A, and 7B .
  • the substrate 905 can include surface features 910 that may provide mechanical support and conductive material 915 to provide electrical connections between layers and components.
  • the dam 907 can form continuous elevated structures, a plurality of disconnected elongated raised features, or a plurality of outcroppings in the substrate 905 .
  • vias can be formed in the substrate 905 , but instead of providing conductive paths between conductive layers, the vias for the trenches 908 can provide a void in the substrate structure to receive under-fill agent during the under-fill processing step.
  • the trenches 708 can form continuous trench structures, a plurality of disconnected elongated trenches, or a plurality of voids or holes in the substrate 705 .
  • the trenches 708 can define one or more keep out areas on the underside of the substrate 705 .
  • the combination of the dam 907 and the trenches 908 can define one or more keep out areas on the underside of the substrate 905 .
  • the dam 907 can be formed during an additional solder mask process during fabrication of the substrate 905 .
  • the trench 908 can be formed during a solder mask process during fabrication of the substrate 905 .
  • the process flow illustrated in FIGS. 3A-3I can be used.
  • the dam 907 can be added to the substrate 905 during fabrication after the ball and die attach process steps (e.g., as described herein with reference to FIG. 6B ) or the dam 907 can be added to the substrate 905 during fabrication before the ball and die attach process steps (e.g., as described herein with reference to FIG. 6C ).
  • FIG. 9B illustrates the modified process of under-filling in the presence of the combination of the dam 907 and the trench 908 , compared to the under-filling process illustrated in FIG. 3H .
  • the combination of the dam 907 and the trench 908 limits the distribution of the under-fill material 345 to maintain the under-fill material 345 a targeted or desired distance from the solder balls 340 while still providing targeted coverage under and around the lower component 335 .
  • the order of the steps and/or phases can be rearranged and certain steps and/or phases may be omitted entirely.
  • the methods described herein are to be understood to be open-ended, such that additional steps and/or phases to those shown and described herein can also be performed.

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Abstract

Disclosed herein are methods of fabricating a packaged radio-frequency (RF) device. The disclosed methods use a film during fabrication to control the distribution of an under-fill material between one or more components and a packaging substrate. The method includes mounting components to a first side of a packaging substrate and applying a film to a second side of a packaging substrate. The method also includes mounting a lower component to the second side of the packaging substrate and under-filling the lower component mounted on the second side of the packaging substrate with an under-filling agent. The method also includes removing the film on the second side of the packaging substrate and mounting solder balls to the second side of the packaging substrate after removal of the film.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application claims priority to U.S. Provisional Application No. 62/452,450 filed Jan. 31, 2017 and entitled “CONTROL OF UNDER-FILL USING A FILM DURING FABRICATION FOR A DUAL-SIDED BALL GRID ARRAY PACKAGE,” to U.S. Provisional Application No. 62/452,452 filed Jan. 31, 2017 and entitled “CONTROL OF UNDER-FILL USING UNDER-FILL DEFLASH FOR A DUAL-SIDED BALL GRID ARRAY PACKAGE,” to U.S. Provisional Application No. 62/452,457 filed Jan. 31, 2017 and entitled “CONTROL OF UNDER-FILL USING A FILM DURING FABRICATION FOR A DUAL-SIDED BALL GRID ARRAY PACKAGE,” to U.S. Provisional Application No. 62/452,458 filed Jan. 31, 2017 and entitled “CONTROL OF UNDER-FILL WITH A PACKAGING SUBSTRATE HAVING AN INTEGRATED TRENCH FOR A DUAL-SIDED BALL GRID ARRAY PACKAGE,” and to U.S. Provisional Application No. 62/452,460 filed Jan. 31, 2017 and entitled “CONTROL OF UNDER-FILL USING AN ENCAPSULANT FOR A DUAL-SIDED BALL GRID ARRAY PACKAGE,” each of which is expressly incorporated by reference herein in its entirety for all purposes.
  • This application is also related to U.S. Pat. No. 9,381,529 issued Jul. 5, 2016 and entitled “SYSTEMS, DEVICES AND METHODS RELATED TO PAINT RECIRCULATION DURING MANUFACTURE OF RADIO-FREQUENCY MODULES,” and to U.S. patent application Ser. No. 15/724,722 filed Oct. 4, 2017 and entitled “DUAL-SIDED RADIO-FREQUENCY PACKAGE WITH OVERMOLD STRUCTURE,” each of which is expressly incorporated by reference herein in its entirety for all purposes.
    • BACKGROUND Field
  • The present disclosure generally relates to fabrication of dual-sided packaged electronic modules.
    • Description of Related Art
  • The present disclosure relates to fabrication of packaged electronic modules such as radio-frequency (RF) modules. In radio-frequency applications, RF circuits and related devices can be implemented in a packaged module. Such a packaged module can then be mounted on a circuit board such as a phone board.
    • SUMMARY
  • According to a number of implementations, the present disclosure relates to a method of fabricating a packaged radio-frequency device. The method includes mounting components to a first side of a packaging substrate. The method also includes applying a film to a second side of a packaging substrate. The method also includes mounting a lower component to the second side of the packaging substrate after application of the film. The method also includes under-filling the lower component mounted on the second side of the packaging substrate with an under-fill agent. The method also includes removing the film on the second side of the packaging substrate. The method also includes mounting solder balls to the second side of the packaging substrate after removal of the film.
  • In some embodiments, the film covers contact pads of the solder balls. In some embodiments, applying the film includes laser cutting openings in a tape adhesive and mounting strips to the film.
  • The method also includes applying the film includes covering a first area of the second side of the packaging substrate while a second area of the second side of the packaging substrate remains uncovered by the film. In further embodiments, the first area includes a plurality of contact pads for the solder balls. In further embodiments, the second area includes a die area where the lower-component is mounted.
  • In some embodiments, a size of a keep out zone is reduced by application and removal of the film. In some embodiments, the under-fill agent at least partially covers the film prior to removal of the film. In further embodiments, the film prevents the under-fill agent from coating contact pads of the solder balls.
  • According to a number of implementations, the present disclosure relates to a method for manufacturing packaged radio-frequency devices. The method includes applying a film to an underside of a packaging substrate, the packaging substrate having an upper side with one or more upper components mounted thereto, the underside of the packaging substrate having a die area and a contact pad area having a plurality of contact pads for through-mold connections, application of the film including covering the contact pad area with the film while leaving the die area uncovered by the film. The method also includes after applying the film, mounting one or more lower components within the die area so that there is a gap between the one or more lower components and the packaging substrate. The method also includes after mounting the one or more lower components, depositing an under-fill material on the packaging substrate so that the under-fill material penetrates into the gap. The method also includes after depositing the under-fill material, removing the film from the underside of the packaging substrate.
  • In some embodiments, the method further includes mounting through-mold connections to the underside of the packaging substrate after removal of the film. In further embodiments, the through-mold connections include solder balls. In yet further embodiments, the method further includes singulating individual units from the packaging substrate to yield a plurality of dual-sided packages.
  • In some embodiments, the under-fill material includes a sealing resin or an epoxy. In some embodiments, the method further includes curing the under-fill material. In some embodiments, applying the film includes laser cutting openings in a tape adhesive and mounting strips to the film.
  • In some embodiments, the film is configured to control distribution of the under-fill material during deposition of the under-fill material. In further embodiments, the under-fill material contacts the film. In further embodiments, removing the film includes removing a portion of the under-fill material that covers the film. In further embodiments, removing the film further includes leaving the under-fill material deposited in the die area.
  • According to a number of implementations, the present disclosure relates to a method of fabricating a packaged radio-frequency (RF) device. The method includes mounting components to a first side of a packaging substrate. The method also includes mounting a lower component to a second side of the packaging substrate. The method also includes under-filling the lower component mounted on the second side of the packaging substrate with an under-filling agent. The method also includes deflashing a portion of the under-filling agent. The method also includes mounting solder balls to the second side of the packaging substrate after the portion of the under-filling agent has been deflashed.
  • In some embodiments, the portion of the under-filling agent that is deflashed includes under-filling agent that coats contact pads of the solder balls. In some embodiments, deflashing includes removing a thin layer of the under-filling agent. In some embodiments, a size of a keep out zone is reduced by deflashing a portion of the under-filling agent prior to mounting the solder balls.
  • In some embodiments, the second side of the packaging substrate includes a plurality of contact pads for mounting the solder balls. In further embodiments, the under-filling agent coats a portion of at least one of the plurality of contact pads. In further embodiments, deflashing includes removing the portion of the under-filling agent that coats the portion of the at least one of the plurality of contact pads.
  • According to a number of implementations, the present disclosure relates to a method for manufacturing packaged radio-frequency devices. The method includes mounting one or more lower components on an underside of a packaging substrate so that there is a gap between the one or more lower components and the packaging substrate, the packaging substrate having an upper side with one or more upper components mounted thereto, the underside of the packaging substrate having a die area and a contact pad area having a plurality of contact pads for through-mold connections. The method also includes after mounting the one or more lower components, depositing an under-fill material on the packaging substrate so that the under-fill material penetrates into the gap. The method also includes after depositing the under-fill material, deflashing a portion of the under-fill material that covers one or more targeted areas.
  • In some embodiments, the method further includes mounting through-mold connections to the underside of the packaging substrate after deflashing the portion of the under-fill material. In further embodiments, the through-mold connections include solder balls. In further embodiments, the methods further includes singulating individual units from the packaging substrate to yield a plurality of dual-sided packages.
  • In some embodiments, the under-fill material includes a sealing resin or an epoxy. In some embodiments, the method further includes curing the under-fill material. In some embodiments, the one or more targeted areas includes a portion of the contact pad area. In some embodiments, deflashing includes removing a thin layer of the under-fill material. In some embodiments, a size of a keep out zone is reduced by deflashing a portion of the under-fill material prior to mounting any through-mold connections to the underside of the packaging substrate.
  • In some embodiments, the under-fill material coats a portion of the contact pad area. In further embodiments, deflashing includes removing the portion of the under-fill material that coats the portion of the contact pad area.
  • According to a number of implementations, the present disclosure relates to a packaging substrate for a packaged radio-frequency (RF) device. The packaging substrate includes an insulating material forming a first side and a second side, the second side forming contact points for a ball grid array and a lower component, the contact points exposing electrically conducting material on the second side, the second side also forming a dam on the insulating material forming an area to receive under-fill agent during an under-fill process, the dam including a feature configured to block the spread of under-fill material during an under-fill process. The packaging substrate also includes one or more conducting layers formed within the insulating material. The packaging substrate also includes conducting paths electrically coupling contact pads formed on the insulating material to one of the one or more conducting layers.
  • In some embodiments, the dam is formed using a solder mask during fabrication of the packaging substrate. In some embodiments, the dam is photolithographically defined in the original substrate manufacturing process. In some embodiments, the dam includes a plurality of outcroppings. In some embodiments, the dam includes continuous elevated structures. In some embodiments, the dam includes a plurality of disconnected elongated raised features. In some embodiments, the dam defines a keep out region that includes contact points for the lower component and excludes contact points for the ball grid array. In some embodiments, the dam is configured to surround the contact points for the ball grid array.
  • According to a number of implementations, the present disclosure relates to a method of fabricating a packaged radio-frequency (RF) device. The method includes mounting components to a first side of a packaging substrate. The method also includes mounting a lower component to a second side of the packaging substrate. The method also includes mounting solder balls to the second side of the packaging substrate. The method also includes forming a dam on a second side of the packaging substrate after mounting the lower component and after mounting the solder balls. The method also includes under-filling the lower component mounted on the second side of the packaging substrate with an under-fill material such that the under-fill material at least partially contacts the dam formed on the packaging substrate.
  • In some embodiments, the dam is formed using an application method that includes jetting or needle dispensing. In some embodiments, the dam is configured to limit the distribution of the under-fill material to maintain the under-fill material a targeted distance from the solder balls while providing targeted coverage under and around the lower component. In some embodiments, the method further includes singulating individual units from the packaging substrate to yield a plurality of dual-sided packages. In some embodiments, the under-fill material includes a sealing resin or an epoxy. In some embodiments, the method further includes curing the under-fill material.
  • According to a number of implementations, the present disclosure relates to a method of fabricating a packaged radio-frequency (RF) device. The method includes mounting components to a first side of a packaging substrate. The method also includes forming a dam on a second side of the packaging substrate. The method also includes mounting a lower component to a second side of the packaging substrate after forming the dam. The method also includes mounting solder balls to the second side of the packaging substrate after forming the dam. The method also includes under-filling the lower component mounted on the second side of the packaging substrate with an under-fill material such that the under-fill material at least partially contacts the dam formed on the packaging substrate.
  • In some embodiments, the dam is formed using an application method that includes screen printing, jetting, or needle dispensing. In some embodiments, the dam is configured to limit the distribution of the under-fill material to maintain the under-fill material a targeted distance from the solder balls while providing targeted coverage under and around the lower component. In some embodiments, the method further includes singulating individual units from the packaging substrate to yield a plurality of dual-sided packages. In some embodiments, the under-fill material includes a sealing resin or an epoxy. In some embodiments, the method further includes curing the under-fill material.
  • According to a number of implementations, the present disclosure relates to a packaging substrate for a packaged radio-frequency (RF) device. The packaging substrate includes an insulating material forming a first side and a second side, the second side forming contact points for a ball grid array and a lower component, the contact points exposing electrically conducting material on the second side, the second side also forming trenches in the insulating material that include a feature to receive under-fill agent during an under-fill process. The packaging substrate also includes one or more conducting layers formed within the insulating material. The packaging substrate also includes conducting paths electrically coupling contact pads formed on the insulating material to one of the one or more conducting layers.
  • In some embodiments, the trenches are formed using a solder mask during fabrication of the packaging substrate. In some embodiments, the trenches do not expose electrically conducting material on the second side. In some embodiments, the trenches form continuous trench structures. In some embodiments, the trenches form a plurality of disconnected elongated trenches. In some embodiments, the trenches form a plurality of voids in the substrate. In some embodiments, the trenches define a keep out region that includes contact points for the lower component and excludes contact points for the ball grid array. In some embodiments, the substrate is configured to be singulated to yield a plurality of dual-sided packages.
  • According to a number of implementations, the present disclosure relates to a method of fabricating a packaged radio-frequency (RF) device. The method includes forming a trench in insulating material of a packaging substrate, the trench formed on an underside of the packaging substrate. The method also includes mounting components to an upper side of the packaging substrate. The method also includes mounting a lower component to the underside of the packaging substrate. The method also includes mounting solder balls to the underside of the packaging substrate. The method also includes under-filling the lower component mounted on the second side of the packaging substrate with an under-fill material such that the under-fill material at least partially fills the trench formed in the insulating material of the packaging substrate.
  • In some embodiments, the trench is configured to limit the distribution of the under-fill material to maintain the under-fill material a targeted distance from the solder balls while providing targeted coverage under and around the lower component. In some embodiments, the method further includes singulating individual units from the packaging substrate to yield a plurality of dual-sided packages. In some embodiments, the under-fill material includes a sealing resin or an epoxy. In some embodiments, the method further includes curing the under-fill material. In some embodiments, forming the trench includes using a solder mask process. In some embodiments, the trench includes continuous trench structures. In some embodiments, the trench includes a plurality of disconnected elongated trenches. In some embodiments, the trench includes a plurality of voids in the substrate. In some embodiments, forming the trench does not penetrate through the insulating material to a conductive layer. In some embodiments, the trench does not include conductive material. In some embodiments, the trench defines a keep out region that includes contact points for the lower component and excludes contact points for the solder balls.
  • According to a number of implementations, the present disclosure relates to a method of fabricating a packaged radio-frequency (RF) device. The method includes mounting components to a first side of a packaging substrate. The method also includes coating solder balls with a fluxing agent. The method also includes attaching the solder balls to a second side of the packaging substrate. The method also includes encapsulating the solder balls with an encapsulant that forms an obtuse angle with the packaging substrate. The method also includes attaching a lower component to the second side of the packaging substrate. The method also includes under-filling the lower component mounted on the second side of the packaging substrate with an under-filling agent such that the under-filling agent contacts the encapsulant.
  • In some embodiments, the encapsulant is a polymer. In some embodiments, the encapsulant is not removed in a cleaning process following attachment of the solder balls to the packaging substrate. In some embodiments, the encapsulant forms an obtuse angle to the solder balls. In some embodiments, the under-filling agent contacts the encapsulant and not the solder balls. In some embodiments, the method further includes singulating individual units from the packaging substrate to yield a plurality of dual-sided packages.
  • According to a number of implementations, the present disclosure relates to a method for manufacturing packaged radio-frequency devices. The method includes mounting one or more lower components within a die area on an underside of a packaging substrate so that there is a gap between the one or more lower components and the packaging substrate, the packaging substrate having an upper side with one or more upper components mounted thereto, the underside of the packaging substrate having the die area and a contact pad area having a plurality of contact pads for through-mold connections. The method also includes mounting the solder balls to the underside of the packaging substrate, the solder balls being coated with a fluxing agent that leaves behind a material that encapsulates the base of each solder balls, the material forming an encapsulant. The method also includes after mounting the solder balls, depositing an under-fill material on the packaging substrate so that the under-fill material penetrates into the gap.
  • In some embodiments, the encapsulant forms an obtuse angle with a surface of the underside of the packaging substrate and with a surface of the solder balls. In further embodiments, the obtuse angle is configured to reduce a surface energy driving force for capillary action of the under-fill material.
  • In some embodiments, the method further includes singulating individual units from the packaging substrate to yield a plurality of dual-sided packages. In some embodiments, the under-fill material includes a sealing resin or an epoxy. In some embodiments, the method further includes curing the under-fill material.
  • In some embodiments, the encapsulant is configured to control distribution of the under-fill material during deposition of the under-fill material. In further embodiments, the under-fill material contacts the encapsulant.
  • In some embodiments, the material is configured so that it is not removed during a cleaning process that follows solder ball attach reflow. In further embodiments, the material is a polymer. In some embodiments, the encapsulant is configured to reduce capillary action causing the under-fill material to wick around the solder balls.
  • According to a number of implementations, the present disclosure relates to a packaging substrate for a packaged radio-frequency (RF) device. The packaging substrate includes an insulating material forming a first side and a second side, the second side forming contact points for a ball grid array and a lower component, the contact points exposing electrically conducting material on the second side, the second side also forming trenches in the insulating material that include a feature to receive under-fill agent during an under-fill process, the second side also forming a dam on the insulating material forming an area to receive under-fill agent during an under-fill process, the dam including a feature configured to block the spread of under-fill material during an under-fill process. The packaging substrate also includes one or more conducting layers formed within the insulating material. The packaging substrate also includes conducting paths electrically coupling contact pads formed on the insulating material to one of the one or more conducting layers.
  • According to a number of implementations, the present disclosure relates to a method of fabricating a packaged radio-frequency (RF) device. The method includes forming a trench in insulating material of a packaging substrate, the trench formed on an underside of the packaging substrate. The method also includes forming a dam on the underside of the packaging substrate. The method also includes mounting components to an upper side of a packaging substrate. The method also includes mounting a lower component to the underside of the packaging substrate. The method also includes mounting solder balls to the underside of the packaging substrate. The method also includes under-filling the lower component mounted on the second side of the packaging substrate with an under-fill material such that the under-fill material at least partially flows into the trench or contacts the dam formed on the packaging substrate.
  • According to a number of implementations, the present disclosure relates to a method of fabricating a packaged radio-frequency (RF) device. The method includes forming a dam on an underside of the packaging substrate. The method also includes mounting components to an upper side of the packaging substrate. The method also includes mounting a lower component to the underside of the packaging substrate. The method also includes under-filling the lower component mounted on the second side of the packaging substrate with an under-fill material such that the under-fill material at least partially flows into the trench or contacts the dam formed on the packaging substrate. The method also includes deflashing a portion of the under-filling agent. The method also includes mounting solder balls to the underside of the packaging substrate.
  • According to a number of implementations, the present disclosure relates to a method of fabricating a packaged radio-frequency (RF) device. The method includes forming a trench in insulating material of a packaging substrate, the trench formed on an underside of the packaging substrate. The method also includes mounting components to an upper side of the packaging substrate. The method also includes mounting a lower component to the underside of the packaging substrate. The method also includes under-filling the lower component mounted on the second side of the packaging substrate with an under-fill material such that the under-fill material at least partially flows into the trench or contacts the dam formed on the packaging substrate. The method also includes deflashing a portion of the under-filling agent. The method also includes mounting solder balls to the underside of the packaging substrate.
  • For purposes of summarizing the disclosure, certain aspects, advantages and novel features have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment. Thus, the disclosed embodiments may be carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 illustrates a dual-sided package having a shielded package and a lower component mounted thereto.
  • FIG. 2 illustrates another example of a dual-sided package having one or more lower components that can be mounted under a shielded package, generally within a volume defined on an underside of the shielded package.
  • FIGS. 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, and 3I illustrate a typical process flow for fabricating a dual-sided ball grid array package.
  • FIGS. 4A, 4B, 4C, 4D, 4E, and 4F illustrate a modified fabrication process that uses a film to control distribution of an under-fill material.
  • FIGS. 5A, 5B, 5C, and 5D illustrate a modified fabrication process using under-fill deflash to control the distribution of an under-fill material.
  • FIGS. 6A, 6B, 6C, and 6D illustrate a modified fabrication process that includes using a dam to contain an under-fill material.
  • FIGS. 7A and 7B illustrate a modified fabrication process that uses a substrate with trenches on the underside of the substrate.
  • FIGS. 8A and 8B illustrate a modified fabrication process using encapsulant to control the distribution of an under-fill material.
  • FIGS. 9A and 9B illustrate a panel with a dam or a series of raised features in conjunction with a trench or a series of valleys, holes, or the like in a substrate, wherein the dam and the trench are configured to control the distribution of an under-fill material.
    •  DETAILED DESCRIPTION OF SOME EMBODIMENTS
  • The headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the claimed invention.
    • Overview
  • Described herein are technologies related to fabrication of dual-sided packaged electronic modules, such as radio-frequency modules, and devices, systems, and methods to control the distribution of an under-fill material between one or more components and a packaging substrate. The disclosed technologies include applying a film to targeted areas on the packaging substrate prior to under-filling one or more components and prior to attaching solder balls. By applying the film to the packaging substrate prior to under-filling, the region that receives under-fill material can be controlled to a greater degree. After under-filling, the film can be removed to expose clean contact pads for the solder balls. Furthermore, because the solder balls are not present during under-fill, there is little capillary action drawing material away from the components being under-filled. This can advantageously reduce the frequency of voids under the components being under-filled. Accordingly, the disclosed systems, devices, and methods control under-fill for dual-sided ball grid array packages using a film prior to attaching solder balls of the ball grid array.
  • The disclosed technologies also include under-filling one or more components and deflashing a portion of the under-fill to remove under-fill material prior to attaching solder balls. By adding the deflashing step and adding solder balls after deflashing, the region that has under-fill material can be controlled to a greater degree. The deflashing step removes a thin layer of under-fill material that may have coated contact pads for the ball grid array. Furthermore, because the solder balls are not present during under-fill, there is little capillary action drawing material away from the components being under-filled. This can advantageously reduce the frequency of voids under the components being under-filled. Accordingly, the disclosed systems, devices, and methods control under-fill for dual-sided ball grid array packages using under-fill deflash prior to attaching solder balls of the ball grid array.
  • The disclosed technologies also include using a dam on a packaging substrate. The dam on the packaging substrate is configured to prevent or limit the flow of a capillary under-fill material. For example, the dam can form a controlled area so that the capillary under-fill material fills or flows substantially free within this area but does not flow outside of the area. This can prevent or limit the capillary under-fill material from flowing onto or contacting other components or elements on the packaging substrate, such as solder balls of a ball-grid array. Accordingly, the disclosed systems, devices, and methods control under-fill for dual-sided ball grid array packages using a dam on a packaging substrate.
  • The disclosed technologies also include forming a trench in a packaging substrate. The trench in the packaging substrate is configured to prevent or limit the flow of a capillary under-fill material. For example, the trench can form a controlled area so that the capillary under-fill material fills or flows substantially free within this area but does not flow outside of the area. This can prevent or limit the capillary under-fill material from flowing onto or contacting other components or elements on the packaging substrate, such as solder balls of a ball-grid array. Accordingly, the disclosed systems, devices, and methods control under-fill for dual-sided ball grid array packages using a trench on a packaging substrate.
  • The disclosed technologies also include using an encapsulant on solder balls to limit distribution of an under-fill agent. The encapsulant can be used in the ball attach process. The fluxing agent leaves behind a material that encapsulates the base of each solder ball. The encapsulant forms an obtuse angle with the substrate surface and with the ball surface. This reduces the tendency of the under-fill material to wick around the solder balls by capillary action. This can prevent or limit the capillary under-fill material from flowing onto or contacting other components or elements on the packaging substrate, such as solder balls of a ball-grid array. Accordingly, the disclosed systems, devices, and methods control under-fill for dual-sided ball grid array packages using an encapsulant on the solder balls.
  • In radio-frequency (RF) applications, RF circuits and related devices can be implemented in a packaged module. Such a packaged module can then be mounted on a circuit board such as a phone board. Certain packaged modules can include dual-sided packages, with components mounted over and under a packaging substrate. Such packaged modules can include an array of solder balls, or a ball grid array, on an underside of the packaging substrate, which collectively may be referred to as a dual-sided ball grid array (DS-BGA).
  • FIG. 1 illustrates a dual-sided package 100 having a shielded package 102 and a lower component 104 mounted thereto. For the purpose of description, a lower side of the shielded package 102 can include a side 103 of a packaging substrate that is to be mounted onto a circuit board such as a phone board. Although not shown separately in FIG. 1, it will be understood that the shielded package 102 can include such a packaging substrate and one or more upper components mounted on its upper side (when oriented as shown in FIG. 1). Accordingly, the dual-sided property can include such upper component(s) mounted over the substrate and lower component(s) mounted under the substrate.
  • The package can be shielded using any suitable shielding method. For example, the package 100 can be shielded using a plurality of shielding wires that are electrically coupled to a ground plane within the packaging substrate. The package 100 can be shielded using a conformal coating that is electrically coupled to a ground plane within the packaging substrate. Any suitable combination of features can be used to define a shielded volume or region. Such configurations can be implemented to provide shielding functionality between regions within and outside of the shielded package 100, and/or between regions that are both within the shielded package 100.
  • For the purpose of description, it will be understood that a lower component can include any device that can be mounted on the substrate and/or the circuit board. Such a device can be an active radio-frequency (RF) device or a passive device that facilitates processing of RF signals. By way of non-limiting examples, such a device can include a die such as a semiconductor die, an integrated passive device (IPD), a surface-mount technology (SMT) device, and the like. In some embodiments, the lower component as described herein can be electrically coupled to the one or more upper components through, for example, the substrate.
  • FIG. 2 illustrates another example of a dual-sided package 200 having one or more lower components 204 that can be mounted under a shielded package 202, generally within a volume defined on an underside of the shielded package. In some embodiments, a set of through-mold connections (e.g., one or more through-mold connections) may be implemented, formed, located, and/or positioned on the underside (e.g., side 103 illustrated in FIG. 1) of the shielded package 202. The set of through-mold connections may define a volume on the underside of the shielded package 202. A volume 208 under a shielded package 202 is shown to be defined by the underside of the shielded package 202 and solder balls 206 of a ball grid array (BGA). The BGA may be a set of through-mold connections. For example, each solder ball 206 of the BGA may be a through-mold connection in the set of through-mold connections. Other examples of through-mold connections include, but are not limited to solder balls, pillars, columns, posts, pedestals, etc. The through-mold connections described herein may also be referred to as contact features. The solder balls 206 allow the dual-sided package 200 to be mounted on a circuit board 210 such as a phone board. The solder balls 206 can be configured so that when mounted to the circuit board 210, there is sufficient vertical space between the upper surface of the circuit board 210 and the lower surface of the shielded package 202 for the lower component 204. The volume 208 can be at least partially filled with an over-mold 205. The over-mold 205 substantially encapsulates the lower component 204. In certain embodiments, at least a portion of the solder balls 206 may be exposed through the over-mold 205. Exposing at least a portion of the solder balls 206 may provide a connection (e.g., an electrical and/or thermal connection) through the over-mold 205. For example, the solder balls 206 may provide a connection (e.g., an electrical connection) to the lower component 204 and/or upper components 224, 226 in the shield package 202. In various embodiments, solder (or other conductive material) may be applied to the exposed portion of the solder balls 206 to form a connection (e.g., electrical connection) with the circuit board 210. The over-mold 205 may also be referred to as an over-mold structure. In some embodiments, the over-mold 205 and/or the solder balls 206 (e.g., the exposed portions of the solder balls 206) may form a land grid array (LGA) type/style package.
  • A close-up view of the solder ball 206 is also illustrated in FIG. 2. As illustrated in the close-up view of the solder ball 206, the bottom of the shielded package includes a pad 215. The pad 215 may be a metallic pad (or some other material) that may provide electrical and/or thermal conductivity between the solder ball 206 and components of the shield package 202 and/or the lower component 204. Solder mask 214 may be deposited over portions of the pad 215 to define a location where the solder ball 206 may be formed. The solder ball 206 may be formed (e.g., implemented, formed, dropped, etc.) on top of the pad 215 and the solder mask 214.
  • The dual-sided package 200 may be installed on the circuit board 210 using the solder ball 206. The solder ball 206 may be attached to the circuit board 210 (e.g., may be installed, mounted, fixed, etc., to the circuit board 210) via connection 216. As illustrated in the close-up view of the solder ball 206, the connection 216 may include solder material 221 and pad 219. The solder material 221 may be solder material from the solder ball 206 that is deposited/melted onto the pad 219 when the dual-sided package 200 is attached to the circuit board. For example, during a reflow process, heat may be applied to melt at least a portion of the solder ball 206 to form the solder material 221. The solder material 221 may also include additional material that is formed, implemented, deposited, etc., over the solder ball 206. The pad 219 may be part of the circuit board 210. The pad 219 may provide electrical and/or thermal conductivity between the dual-sided package 200 and other components/circuits attached to the circuit board 210 (not illustrated in the figures). In some embodiments, the pad 219 may include solder material.
  • The over-mold 205 has a surface 212 (facing downward toward the circuit board 210). In some embodiments, the surface 212 may not contact (e.g., may not physically touch) the surface 213 of the circuit board 210. For example, a gap 209 may be present between the surface 212 and the surface 213. In some implementations, the gap 209 may help protect the lower component 204 from damage when there are linear displacements of the dual-sided package 200 due to flexing or dropping. For example, the gap 209 may help protect the lower component 204 from damage as the dual-sided package 200 is installed on the circuit board 200 (e.g., may prevent the lower component 204 from contacting the surface 213 of the circuit board 210 during installation/mounting of the dual-sided package). The portion of the over-mold material 205 that covers the lower component 204 may provide additional protection from damage when there are linear displacements of the dual-sided package 200 due to flexing or dropping. For example, the over-mold material 205 may also prevent the lower component 204 from contacting the surface 213 of the circuit board 210 during installation/mounting of the dual-sided package. In some embodiments, the gap 209 may also allow the dual-sided package 200 to adapt to process/manufacturing variations when the dual-sided package 200 is installed on the circuit board 210. For example, different temperatures may be used to melt the solder ball 206 during installation of the dual-sided package. The gap 209 may help ensure that the dual-sided package 200 is properly installed by providing enough distance between the surface 212 (of over-mold 205) and the surface 213 (of circuit board 210) while still allowing the solder material of the solder ball 206 to properly bond with the pad 219 of the circuit board 210. In some embodiments, although the over-mold 205 and/or the gap 209 may prevent the component 204 from contacting the surface 213 (of the circuit board 210), the dual-sided package 200 and/or the component 204 may still operate/function properly even if the component 204 does contact the surface 213. For example, the component 204 may remain undamaged and/or operable even after contacting the surface 213 of the circuit board 210.
  • The dual-sided ball grid array package 200 can include a packaging substrate 222 (e.g., a laminate substrate) and a plurality of components mounted thereon. For example, a first component 224 can be mounted on the upper surface of the packaging substrate 222, and electrical connections between the component 224 and the packaging substrate 222 can be facilitated by, for example, wire-bonds 228. In another example, a second component 226 is shown to be mounted on the upper surface of the packaging substrate 222 in a die-attach configuration. Electrical connections between the component 226 and the packaging substrate 222 can be facilitated by, for example, die-attach features.
  • In some embodiments, an under-fill can be provided between the lower component 204 and an underside of the dual-sided package 200. An under-fill 230 can be provided between the lower component 204 and the underside of the package 200 to provide, for example, a more secure mounting of the lower component 204.
  • Examples related to fabrication of dual-sided packages having similar configurations are described herein in greater detail. It will be understood that although such examples are described in the context of solder balls, other types of connection features that provide sufficient vertical space can also be utilized. Although the embodiments, examples, configurations, and/or implementations disclosed herein may refer to solder balls and/or a BGA, one having ordinary skill in the art understands that solder balls and/or a BGA are examples of through-mold connections. One having ordinary skill in the art understands that other types of through-mold connections (e.g., pillars, columns, etc.,) may be used to define a volume on an underside of a shielded package and an over-mold may be implemented in the volume (on the underside of the shielded package). In some embodiments, a through-mold connection (or a set of through-mold connections) may be any structure and/or component that may be used to define a volume on the underside of a shielded package and/or may be used to support the shielded package above a surface.
    • Examples of Fabricating Dual-Sided Ball Grid Array Packages
  • In a dual-sided ball grid array package structure, a zone is required between solder ball(s) and integrated circuit chips, dies, or other such components. This zone (sometimes referred to as a “keep out” zone) is a design rule that calls out a targeted minimum distance between solder ball and component. The keep out zone facilitates meeting manufacturing quality and reliability requirements. Defects such as voids under the component (e.g., an IC chip) where there is no under-fill material, or contamination of the solder balls with undesired material can occur if the keep out zone design rule is violated. It is advantageous to reduce the size of the keep out zone because it can enhance product performance and/or reduce package size. For example, the overall package size can be reduced and/or the chip size can be increased if the size of the keep out zone can be reduced. Decreasing the package size or increasing chip size may result in additional or improved functionality per unit area on the final product motherboard to which the dual-sided ball grid array package is mounted. Accordingly, described herein are systems, devices, and methods that advantageously reduce the keep out zone between solder balls and the IC chip in a dual-sided ball grid array package. This results in greater functionality per unit area when the package is mounted to the final product motherboard.
  • Typical fabrication techniques attempt to reduce or minimize the IC chip-to-solder ball keep out zone by controlling the capillary under-fill dispense process. This may be controlled through the needle selection, the dispense volume, the number of dispense passes, and/or the dispense temperature. By way of example, the keep out zone on the dispense side of the chip may be about 700 μm, and may be about 200 μm on the other three sides of the chip.
  • FIGS. 3A-3I illustrate a process flow for fabricating a dual-sided ball grid array package. FIGS. 3A-3F illustrate a process for completing a top side assembly of a laminate strip (e.g., surface mount, die attach, wire bond, molding, and marking). FIGS. 3G-3I illustrate a process for completing a bottom side assembly and forming individual packages through singulation. Optionally, a conformal shield material stack may be applied to individual packages. As illustrated in FIGS. 4A-4F, the present disclosure improves on this fabrication process by applying a film to the bottom side of the packaging substrate prior to under-filling to protect the contact pads of the solder balls of the ball grid array and to control the distribution of the under-filling material. In addition, as illustrated in FIGS. 5A-5D, the present disclosure improves on this fabrication process by under-filling and deflashing a portion of the under-fill material prior to adding the solder balls of the ball grid array. Moreover, as illustrated in FIGS. 6A-6D, the present disclosure improves on this fabrication process by forming a dam on the substrate to impede or prevent the capillary under-fill material from flowing into the solder balls. Furthermore, as illustrated in FIGS. 7A and 7B, the present disclosure improves on this fabrication process by forming a trench in the substrate to impede or prevent the capillary under-fill material from flowing into the solder balls. Additionally, as illustrated in FIGS. 8A and 8B, the present disclosure improves on this fabrication process by using an encapsulant on the solder balls to impede or prevent the under-fill material from flowing onto the solder balls.
  • FIGS. 3A-3I illustrate various stages of a fabrication process in which dual-sided features can be implemented in a panel format having an array of to-be-separated units, and separation of the array into individual units (also referred to as singulation). Although described in the context of BGA-based dual-sided packages, it will be understood that one or more features of the fabrication technique of FIGS. 3A-3I, 4A-4F, 5A-5D, 6A, 6B, 7A, 7B, 8A, and 8B can also be implemented for fabrication of dual-sided packages having other types of mounting features. In some implementations, the disclosed fabrication processes can be utilized for manufacturing dual-sided packages described herein and in U.S. Pat. No. 9,381,529 and U.S. patent application Ser. No. 15/724,722 (each of which has been expressly incorporated by reference herein).
  • FIG. 3A illustrates a cross-section view of a panel 300 having a plurality of to-be-singulated units. For example, singulation can occur at boundaries depicted by dashed lines 360 so at to yield singulated individual units. The panel 300 includes a substrate 305 on which components are to be mounted. The substrate 305 can be a laminate substrate, a ceramic substrate (e.g., a low-temperature co-fired ceramic substrate), or the like. The substrate 305 can include surface features 310 that may provide mechanical support. The panel 300 includes conductive material 315 that is configured to provide electrical connections between conductive layers, surface-mount devices, chips, solder balls, and the like. The conductive material 315 can form contact pads on the upper and lower sides of the substrate 305 to provide electrical contact points for surface mount devices, chips, solder balls, pillars, any combination of these, or the like. Vias can be formed in the substrate where the conductive material 315 provides an electrical connection between conductive layers in the panel 300.
  • FIG. 3B illustrates mounting of surface mount technology (SMT) devices 320 such that conductive points on the devices 320 are electrically coupled to contact pads formed by the conductive material 315 on the panel 300. By way of example, solder paste can be applied on the substrate 305 to allow mounting of one or more SMT devices 320. A reflow operation can be performed to melt the solder paste to solder the one or more SMT devices on their respective contact pads. Solder residue from the reflow operation can be removed by running the substrates through a solvent or aqueous cleaning step, for example.
  • FIG. 3C illustrates mounting of a die or chip 325. By way of example, adhesive 326 can be applied on one or more selected areas on the substrate 305. The die 325 can be positioned on the selected area with adhesive applied thereon. The adhesive 326 between the die 325 and the die-mounting area can be cured to secure the die 325.
  • FIG. 3D illustrates forming electrical connections between the die 325 and contact pads using wirebonds 327. The wirebonds 327 can provide electrical connections for signals and/or power to and from one or more circuits of the die 325.
  • FIG. 3E illustrates forming an over-mold 330 over the SMT component(s) 320, die(s) 325, and any other upper component on the substrate 305. By way of example, molding compound can be introduced from one or more sides of a molding volume to form an upper over-molded volume 330. In some embodiments, the over-mold 330 may completely encapsulate the upper components 320, 325.
  • FIG. 3F illustrates an optional process of marking the over-mold 330. By way of example, marking may be accomplished using laser etching or similar techniques.
  • FIG. 3G illustrates attaching a lower component 335 to the underside (which may face upward during fabrication) of the substrate 305. In addition, an array of solder balls 340 can be formed on the underside of the substrate 305. It will be understood that the lower component 335 may be attached for each unit after the array of solder balls 340 is formed, or vice versa. It shall also be understood that the lower component 335 and the array of solder balls 340 may be attached, implemented, and/or formed substantially simultaneously.
  • FIG. 3H illustrates filling a gap between the lower component 335 and the substrate 305 with an under-fill agent 345 or an under-fill material (also referred to as under-filling). By way of example, an under-fill material 345, such as a sealing resin or epoxy, can be deposited on the substrate 305 and the under-fill material 345 can penetrate into the gap between the lower component 335 and the substrate 305 by capillary forces. The coating shape and amount of under-fill agent 345 vary depending on the package size, pitch, and gap. The under-fill material 345 can be cured to provide mechanical support to the lower component 335, to provide advantageous thermal properties, to improve solder-ball bonding reliability under external stresses, and the like.
  • FIG. 3I illustrates singulating individual units to yield a plurality of dual-sided packages 350 substantially ready to be mounted to circuit boards.
    • Controlling Under-Fill Using a Film
  • To better control the size of the keep out area, the fabrication process illustrated in FIGS. 3A-3I can be improved by applying a film to the bottom side of the packaging substrate prior to adding the solder balls and prior to under-filling the lower component. Upon removal of the film, the solder balls can be added. The film protects the contact pads of the solder balls and controls the distribution of the under-filling agent.
  • FIGS. 4A-4F illustrate a modified fabrication process, replacing steps illustrated in FIGS. 3G and 3H. FIG. 4A illustrates a substrate 305 with a die area 337 (e.g., for mounting one or more lower components) and a plurality of solder ball contact pads 342. A film 447 can be added to the substrate 305 to protect the solder ball contact pads 342 and to expose the die area 337 for mounting one or more lower components. The illustration on the left is shown without the film 447 while the illustration on the right is shown with the film 447.
  • FIG. 4B illustrates the substrate 305 with the film 447 covering the contact pads 342 prior to addition of the lower component 335 and solder balls 340 and prior to under-filling the lower component 335. The film can be used to control the distribution of the under-filling agent, thereby making it possible to reduce the size of the keep out zone.
  • The process for applying the film 447 to the bottom side of the packaging substrate 305 can be similar to the process used in shielding DS-BGA packages. For example, openings can be laser cut in a tape adhesive. Strips can then be mounted to the film so that the film can protect the contact pads of the ball grid array from under-fill runout.
  • FIG. 4C illustrates that, after application of the film 447, the lower component 335 can be added, as described herein with reference to FIG. 3G. However, the solder balls of the ball grid array are not mounted to the substrate 305 as described in FIG. 3G.
  • FIG. 4D illustrates that, after reflow and cleaning, the under-fill agent 345 can be applied as described herein with reference to FIG. 3H. However, there is a lack of capillary action drawing the under-fill material 345 toward the solder balls because the solder balls are not yet installed. This can reduce the occurrence of under-fill voids under the lower component 335. In addition, the film 447 prevents the under-fill material 345 from coating the solder ball contact pads 342.
  • FIG. 4E illustrates an additional process step of removing the film 447. Removing the film 447 can prevent the under-fill material 345 from coating contact pads 342 of the solder balls and/or can remove any under-fill material 345 that would have coated those contact pads 342. In this way, the size and extent of the keep out zone can be controlled.
  • FIG. 4F illustrates that, after removal of the film 447, the solder balls 340 can be added as described in FIG. 3G. The process can then proceed to reflow again and then to singulate the individual units, as described herein with reference to FIG. 3I.
    • Controlling Under-Fill Using Deflashing
  • To better control the size of the keep out area, the fabrication process illustrated in FIGS. 3A-3I can be improved by adding the solder balls after under-filling the lower component and deflashing excess under-fill to control the distribution of under-fill agent.
  • FIGS. 5A-5D illustrate a modified fabrication process, replacing steps described herein with reference to FIGS. 3G and 3H. In FIG. 5A, a lower component 335 is added as described in FIG. 3G. However, the solder balls of the ball grid array are not mounted to the substrate 305 as described in FIG. 3G. In FIG. 5B, the under-fill material 345 is applied as described in FIG. 3H. However, there is a lack of capillary action drawing the under-fill material 345 toward the solder balls because the solder balls are not yet installed. This can reduce the occurrence of under-fill voids under the lower component 335.
  • FIG. 5C illustrates an additional process step of deflashing the under-fill material 345. Deflashing is configured to remove a thin layer of under-fill material from targeted locations 347 on the substrate. For example, deflashing can remove under-fill material that may have coated the contact pads for the solder balls. In this way, the size and extent of the keep out zone can be controlled. FIG. 5D illustrates that, after deflashing, the solder balls 340 can be added as described in FIG. 3G.
    • Controlling Under-Fill Using a Dam
  • To better control the size of the keep out area, the fabrication process illustrated in FIGS. 3A-3I can be improved by forming a dam or a series of raised features on the substrate 305, wherein the dam or similar features is configured to control the distribution of under-fill agent in the process step illustrated in FIG. 3H.
  • As illustrated in FIGS. 6A-6C, a panel 600 can be provided wherein the substrate 605 includes a dam 607 on the underside of the substrate 605, wherein the dam 607 can be an integral part of the substrate 605 or formed on the substrate 605 at a later time. The dam 607 provides a way to control the distribution of the under-fill agent during manufacturing of the disclosed double-sided ball grid array packages. The dam 607 contains the capillary under-fill material and may prevent it from contacting or contaminating the solder balls 340. The dam 607 can provide a repeatable volume of material to flow under the lower component 335 (e.g., a die), which reduces the frequency of voiding under the lower component 335. Although the dam 607 is illustrated on a single side of the solder balls 340, it is to be understood that the dam 607 can be configured to surround the solder balls 340. For example, the dam 607 can be configured to have raised features on a plurality of sides of the solder balls 340. The dam 607 can surround individual solder balls 340 and/or surround or enclose the area that contains the solder balls 340.
  • The substrate 605 can be a laminate substrate, a ceramic substrate (e.g., a low-temperature co-fired ceramic substrate), or the like. The substrate 605 can include surface features 610 that may provide mechanical support. The panel 600 includes conductive material 615 that is configured to provide electrical connections between conductive layers, surface-mount devices, chips, solder balls, and the like. The conductive material 615 can form contact pads on the upper and lower sides of the substrate 605 to provide electrical contact points for surface mount devices, chips, solder balls, pillars, any combination of these, or the like. Vias can be formed in the substrate 605 where the conductive material 615 provides an electrical connection between conductive layers in the panel 600. The dam 607 can form continuous elevated structures, a plurality of disconnected elongated raised features, or a plurality of outcroppings in the substrate 605. The dam 607 can define one or more keep out areas on the underside of the substrate 605.
  • FIG. 6A illustrates that the dam 607 forms part of the substrate 605. In some embodiments, the dam 607 can be formed during an additional solder mask process during fabrication of the substrate 605. In some embodiments, the panel 600 includes a substrate 605 having insulating material forming an upper side and a lower side. The substrate 605 forms voids in which conducting material electrically couples contact pads to conductive layers or other contact pads. The substrate 605 forms a dam 607 (e.g., elevated features, connected raised features, disconnected raised features, etc.) in the insulating material to form a feature that can block the spread of under-fill material during an under-fill process. The dam 607 can be photolithographically defined during the original substrate manufacturing process. Then, when assembling the bottom side of the panel 600, the process flow illustrated in FIGS. 3A-3I can be used.
  • FIG. 6B illustrates that the dam 607 can be added to the substrate 605 during fabrication after the ball and die attach process steps, illustrated in FIG. 3G. To apply the dam 607, jetting or needle dispensing may be used.
  • FIG. 6C illustrates that the dam 607 can be added to the substrate 605 during fabrication before the ball and die attach process steps, illustrated in FIG. 3G. To apply the dam 607, screen printing, jetting, or needle dispensing may be used.
  • FIG. 6D illustrates the modified process of under-filling in the presence of the dam 607, compared to the under-filling process illustrated in FIG. 3H. The dam 607 limits the distribution of the under-fill material 345 to maintain the under-fill material 345 a targeted or desired distance from the solder balls 340 while still providing targeted coverage under and around the lower component 335.
    • Controlling Under-Fill Using a Trench
  • To better control the size of the keep out area, the fabrication process illustrated in FIGS. 3A-3I can be improved by forming a trench or a series of valleys, holes, or the like in the substrate 305, wherein these trenches or similar features are configured to control the distribution of under-fill agent in the process step illustrated in FIG. 3H.
  • As illustrated in FIG. 7A, a panel 700 can be provided wherein the substrate 705 includes trenches 708 on the underside of the substrate 705. The trenches provide a way to control the distribution of the under-fill agent during manufacturing of the disclosed double-sided ball grid array packages. The substrate 705 can be a laminate substrate, a ceramic substrate (e.g., a low-temperature co-fired ceramic substrate), or the like. The substrate 705 can include surface features 710 that may provide mechanical support. The panel 700 includes conductive material 715 that is configured to provide electrical connections between conductive layers, surface-mount devices, chips, solder balls, and the like. The conductive material 715 can form contact pads on the upper and lower sides of the substrate 705 to provide electrical contact points for surface mount devices, chips, solder balls, pillars, any combination of these, or the like. Vias can be formed in the substrate 705 where the conductive material 715 provides an electrical connection between conductive layers in the panel 700.
  • To form the trenches 708, vias can be formed in the substrate 705, but instead of providing conductive paths between conductive layers, the vias for the trenches 708 can provide a void in the substrate structure to receive under-fill agent during the under-fill processing step. By way of example, the trench 708 can be formed during a solder mask process during fabrication of the substrate 705. The trenches 708 can form continuous trench structures, a plurality of disconnected elongated trenches, or a plurality of voids or holes in the substrate 705. The trenches 708 can define one or more keep out areas on the underside of the substrate 705.
  • In some embodiments, the panel 700 includes a substrate 705 having insulating material forming an upper side and a lower side. The substrate 705 forms voids in which conducting material electrically couples contact pads to conductive layers or other contact pads. The substrate 705 forms trenches 708 (e.g., elongated voids) in the insulating material to form a feature that can receive under-fill material during an under-fill process. In some embodiments, the trenches 708 do not include conductive material or do not penetrate to a conductive layer.
  • FIG. 7B illustrates the modified process of under-filling in the presence of trenches 708 in the substrate 705, compared to the under-filling process illustrated in FIG. 3H. The trenches 708 limit the distribution of the under-fill material 345 to maintain the under-fill material 345 a targeted or desired distance from the solder balls 340 while still providing targeted coverage under and around the lower component 335.
    • Controlling Under-Fill Using Encapsulant
  • To better control the size of the keep out area, the fabrication process illustrated in FIGS. 3A-3I can be improved by using a special material during the ball attach process illustrated in FIG. 3G. As illustrated in FIG. 8A, a fluxing agent can be used on the solder balls 340 that leaves behind a material which encapsulates the base of each solder ball 340, forming encapsulant 842. This material may be a polymer. This material can be configured so that it is not removed during a cleaning process that follows solder ball attach reflow. The encapsulant 842 forms an obtuse angle with the surface of the substrate 305 and with the surface of the solder balls 340.
  • When the under-fill material 845 is dispensed in the process step illustrated in FIG. 8B, it no longer has a tendency to wick around the solder balls 340 by capillary action. The obtuse angles formed by the encapsulant 842 reduce the surface energy driving force for capillary action. This reduces or prevents the under-fill material from flowing around the solder balls 340. Instead, the under-fill material 345 primarily flows under the lower component 335 (e.g., an IC chip).
    • Controlling Under-Fill Using a Combination of Features
  • To better control the size of the keep out area, the fabrication process illustrated in FIGS. 3A-3I can be improved by combining features and techniques described herein with respect to FIGS. 4A-4F, 5A-5D, 6A-6D, 7A, 7B, 8A, and 8B. For example, a dam (e.g., as described herein with reference to FIGS. 6A-6D) can be used in combination with a trench (e.g., as described herein with reference to FIGS. 7A and 7B), which is illustrated in FIGS. 9A and 9B. Other combinations can be implemented as well. For example, the dam can be used in conjunction with a film, deflashing, trench, and/or an encapsulant. As another example, the trench can be used in conjunction with a film, deflashing, dam, and/or an encapsulant. Similarly, deflashing can be used in conjunction with a film, dam, trench, and/or an encapsulant. As another example, the film can be used in conjunction with deflashing, dam, trench, and/or an encapsulant. Likewise, encapsulant can be used in conjunction with a film, dam, trench, and/or deflashing.
  • FIG. 9A illustrates a panel 900 with a dam 907 or a series of raised features in conjunction with a trench 908 or a series of valleys, holes, or the like in a substrate 905, wherein the dam 907 and the trench 908 are configured to control the distribution of under-fill agent 345.
  • The panel 900 can be provided wherein the substrate 905 includes the dam 907 on the underside of the substrate 905, wherein the dam 907 can be an integral part of the substrate 905 or formed on the substrate 905 at a later time. Similarly, the substrate 905 includes the trench 908 on the underside of the substrate 905. The dam 907 and the trenches 908 provide a way to control the distribution of the under-fill agent 345 during manufacturing of the disclosed double-sided ball grid array packages. For example, the combination of the dam 907 and the trenches 908 contains the capillary under-fill material 345 and may prevent it from contacting or contaminating the solder balls 340. The combination of the dam 907 and the trenches 908 can provide a repeatable volume of material to flow under the lower component 335 (e.g., a die), which reduces the frequency of voiding under the lower component 335. Although the combination of the dam 907 and the trenches 908 is illustrated on a single side of the solder balls 340, it is to be understood that the dam 907 and/or the trenches 908 can be configured to surround the solder balls 340.
  • The substrate 905 is similar to the substrate 605 and 705 described herein with reference to FIGS. 6A-6D, 7A, and 7B. For example, the substrate 905 can include surface features 910 that may provide mechanical support and conductive material 915 to provide electrical connections between layers and components. The dam 907 can form continuous elevated structures, a plurality of disconnected elongated raised features, or a plurality of outcroppings in the substrate 905. To form the trenches 908, vias can be formed in the substrate 905, but instead of providing conductive paths between conductive layers, the vias for the trenches 908 can provide a void in the substrate structure to receive under-fill agent during the under-fill processing step. The trenches 708 can form continuous trench structures, a plurality of disconnected elongated trenches, or a plurality of voids or holes in the substrate 705. The trenches 708 can define one or more keep out areas on the underside of the substrate 705. The combination of the dam 907 and the trenches 908 can define one or more keep out areas on the underside of the substrate 905.
  • In some embodiments, as described herein with reference to FIG. 6A, the dam 907 can be formed during an additional solder mask process during fabrication of the substrate 905. In some embodiments, the trench 908 can be formed during a solder mask process during fabrication of the substrate 905. Then, when assembling the bottom side of the panel 900, the process flow illustrated in FIGS. 3A-3I can be used. In some embodiments, the dam 907 can be added to the substrate 905 during fabrication after the ball and die attach process steps (e.g., as described herein with reference to FIG. 6B) or the dam 907 can be added to the substrate 905 during fabrication before the ball and die attach process steps (e.g., as described herein with reference to FIG. 6C).
  • FIG. 9B illustrates the modified process of under-filling in the presence of the combination of the dam 907 and the trench 908, compared to the under-filling process illustrated in FIG. 3H. The combination of the dam 907 and the trench 908 limits the distribution of the under-fill material 345 to maintain the under-fill material 345 a targeted or desired distance from the solder balls 340 while still providing targeted coverage under and around the lower component 335.
    • Terminology
  • The present disclosure describes various features, no single one of which is solely responsible for the benefits described herein. It will be understood that various features described herein may be combined, modified, or omitted, as would be apparent to one of ordinary skill. Other combinations and sub-combinations than those specifically described herein will be apparent to one of ordinary skill, and are intended to form a part of this disclosure. Various methods are described herein in connection with various flowchart steps and/or phases. It will be understood that in many cases, certain steps and/or phases may be combined together such that multiple steps and/or phases shown in the flowcharts can be performed as a single step and/or phase. Also, certain steps and/or phases can be broken into additional sub-components to be performed separately. In some instances, the order of the steps and/or phases can be rearranged and certain steps and/or phases may be omitted entirely. Also, the methods described herein are to be understood to be open-ended, such that additional steps and/or phases to those shown and described herein can also be performed.
  • Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list. The word “exemplary” is used exclusively herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations.
  • The disclosure is not intended to be limited to the implementations shown herein. Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other implementations without departing from the spirit or scope of this disclosure. The teachings of the invention provided herein can be applied to other methods and systems, and are not limited to the methods and systems described above, and elements and acts of the various embodiments described above can be combined to provide further embodiments. Accordingly, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.

Claims (20)

What is claimed is:
1. A method of fabricating a packaged radio-frequency device, the method comprising:
mounting components to a first side of a packaging substrate;
applying a film to a second side of a packaging substrate;
mounting a lower component to the second side of the packaging substrate after application of the film;
under-filling the lower component mounted on the second side of the packaging substrate with an under-fill agent;
removing the film on the second side of the packaging substrate; and
mounting solder balls to the second side of the packaging substrate after removal of the film.
2. The method of claim 1 wherein the film covers contact pads of the solder balls.
3. The method of claim 1 wherein applying the film includes laser cutting openings in a tape adhesive and mounting strips to the film.
4. The method of claim 1 wherein applying the film includes covering a first area of the second side of the packaging substrate while a second area of the second side of the packaging substrate remains uncovered by the film.
5. The method of claim 4 wherein the first area includes a plurality of contact pads for the solder balls.
6. The method of claim 5 wherein the second area includes a die area where the lower-component is mounted.
7. The method of claim 1 wherein a size of a keep out zone is reduced by application and removal of the film.
8. The method of claim 1 wherein the under-fill agent at least partially covers the film prior to removal of the film.
9. The method of claim 9 wherein the film prevents the under-fill agent from coating contact pads of the solder balls.
10. A method for manufacturing packaged radio-frequency devices, the method comprising:
applying a film to an underside of a packaging substrate, the packaging substrate having an upper side with one or more upper components mounted thereto, the underside of the packaging substrate having a die area and a contact pad area having a plurality of contact pads for through-mold connections, application of the film including covering the contact pad area with the film while leaving the die area uncovered by the film;
after applying the film, mounting one or more lower components within the die area so that there is a gap between the one or more lower components and the packaging substrate;
after mounting the one or more lower components, depositing an under-fill material on the packaging substrate so that the under-fill material penetrates into the gap; and
after depositing the under-fill material, removing the film from the underside of the packaging substrate.
11. The method of claim 10 further comprising mounting through-mold connections to the underside of the packaging substrate after removal of the film.
12. The method of claim 11 wherein the through-mold connections include solder balls.
13. The method of claim 11 further comprising singulating individual units from the packaging substrate to yield a plurality of dual-sided packages.
14. The method of claim 10 wherein the under-fill material includes a sealing resin or an epoxy.
15. The method of claim 10 further comprising curing the under-fill material.
16. The method of claim 10 wherein the film is configured to control distribution of the under-fill material during deposition of the under-fill material.
17. The method of claim 16 wherein the under-fill material contacts the film.
18. The method of claim 17 wherein removing the film includes removing a portion of the under-fill material that covers the film.
19. The method of claim 18 wherein removing the film further includes leaving the under-fill material deposited in the die area.
20. The method of claim 10 wherein applying the film includes laser cutting openings in a tape adhesive and mounting strips to the film.
US15/885,775 2017-01-31 2018-01-31 Control of under-fill using a film during fabrication for a dual-sided ball grid array package Abandoned US20180226271A1 (en)

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US201762452450P 2017-01-31 2017-01-31
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US15/885,775 Abandoned US20180226271A1 (en) 2017-01-31 2018-01-31 Control of under-fill using a film during fabrication for a dual-sided ball grid array package
US15/885,779 Active US10410885B2 (en) 2017-01-31 2018-01-31 Control of under-fill using under-fill deflash for a dual-sided ball grid array package
US15/885,782 Active US10593565B2 (en) 2017-01-31 2018-01-31 Control of under-fill with a packaging substrate having an integrated trench for a dual-sided ball grid array package
US15/885,787 Active US10460957B2 (en) 2017-01-31 2018-01-31 Control of under-fill using an encapsulant for a dual-sided ball grid array package
US16/566,844 Active US10770312B2 (en) 2017-01-31 2019-09-10 Under-fill deflash for a dual-sided ball grid array package
US16/666,820 Abandoned US20200152483A1 (en) 2017-01-31 2019-10-29 Control of under-fill using an encapsulant and a trench or dam for a dual-sided ball grid array package
US17/014,174 Active US11244835B2 (en) 2017-01-31 2020-09-08 Control of under-fill using a film during fabrication for a dual-sided ball grid array package
US17/549,933 Abandoned US20220130686A1 (en) 2017-01-31 2021-12-14 Control of under-fill using an encapsulant and a trench or dam for a dual-sided ball grid array package

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US15/885,782 Active US10593565B2 (en) 2017-01-31 2018-01-31 Control of under-fill with a packaging substrate having an integrated trench for a dual-sided ball grid array package
US15/885,787 Active US10460957B2 (en) 2017-01-31 2018-01-31 Control of under-fill using an encapsulant for a dual-sided ball grid array package
US16/566,844 Active US10770312B2 (en) 2017-01-31 2019-09-10 Under-fill deflash for a dual-sided ball grid array package
US16/666,820 Abandoned US20200152483A1 (en) 2017-01-31 2019-10-29 Control of under-fill using an encapsulant and a trench or dam for a dual-sided ball grid array package
US17/014,174 Active US11244835B2 (en) 2017-01-31 2020-09-08 Control of under-fill using a film during fabrication for a dual-sided ball grid array package
US17/549,933 Abandoned US20220130686A1 (en) 2017-01-31 2021-12-14 Control of under-fill using an encapsulant and a trench or dam for a dual-sided ball grid array package

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180096951A1 (en) * 2016-10-04 2018-04-05 Skyworks Solutions, Inc. Circuits and methods related to radio-frequency devices with overmold structure
US10410885B2 (en) 2017-01-31 2019-09-10 Skyworks Solutions, Inc. Control of under-fill using under-fill deflash for a dual-sided ball grid array package
KR20210082354A (en) 2019-12-25 2021-07-05 가부시키가이샤 무라타 세이사쿠쇼 Radio frequency module and communication device

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3893612A4 (en) 2018-12-28 2021-12-08 Huawei Technologies Co., Ltd. Printed circuit board and manufacturing method therefor, and electronic device
US11503704B2 (en) * 2019-12-30 2022-11-15 General Electric Company Systems and methods for hybrid glass and organic packaging for radio frequency electronics
TWI759698B (en) * 2020-03-04 2022-04-01 矽品精密工業股份有限公司 Electronic package and carrier structure thereof
US11342277B2 (en) * 2020-06-10 2022-05-24 Micron Technology, Inc. Semiconductor device assemblies with conductive underfill dams for grounding EMI shields and methods for making the same
KR20210156446A (en) 2020-06-18 2021-12-27 삼성전자주식회사 Semiconductor package
KR102400533B1 (en) 2020-08-12 2022-05-19 삼성전기주식회사 Electronic component module and manufacturing method thereof

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6291264B1 (en) * 2000-07-31 2001-09-18 Siliconware Precision Industries Co., Ltd. Flip-chip package structure and method of fabricating the same
US20090170242A1 (en) * 2007-12-26 2009-07-02 Stats Chippac, Ltd. System-in-Package Having Integrated Passive Devices and Method Therefor
US20120083073A1 (en) * 2010-09-30 2012-04-05 Renesas Electronics Corporation Method of manufacturing semiconductor device
US8314499B2 (en) * 2008-11-14 2012-11-20 Fairchild Semiconductor Corporation Flexible and stackable semiconductor die packages having thin patterned conductive layers
US20140001644A1 (en) * 2012-06-29 2014-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package Structures and Methods for Forming the Same
US20140070348A1 (en) * 2012-09-07 2014-03-13 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and Apparatus for Sensor Module
US20150001729A1 (en) * 2013-06-27 2015-01-01 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Trench and Disposing Semiconductor Die Over Substrate to Control Outward Flow of Underfill Material
US20160218093A1 (en) * 2011-08-16 2016-07-28 Intel Corporation Offset interposers for large-bottom packages and large-die package-on-package structures
US20160260690A1 (en) * 2014-07-11 2016-09-08 Intel Corporation Scalable package architecture and associated techniques and configurations
US20180226272A1 (en) * 2017-01-31 2018-08-09 Skyworks Solutions, Inc. Control of under-fill using under-fill deflash for a dual-sided ball grid array package

Family Cites Families (75)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6121689A (en) 1997-07-21 2000-09-19 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
US6546620B1 (en) 2000-06-29 2003-04-15 Amkor Technology, Inc. Flip chip integrated circuit and passive chip component package fabrication method
US20020064931A1 (en) 2000-07-03 2002-05-30 E. C. Ong Method and apparatus for applying a protective over-coating to a ball-grid-array (BGA) structure
US6803324B2 (en) * 2001-01-31 2004-10-12 Sony Corporation Semiconductor device and its manufacturing method
US6459144B1 (en) 2001-03-02 2002-10-01 Siliconware Precision Industries Co., Ltd. Flip chip semiconductor package
US6770510B1 (en) * 2002-09-06 2004-08-03 Taiwan Semiconductor Manufacturing Company Flip chip process of flux-less no-flow underfill
US6790758B2 (en) 2002-11-25 2004-09-14 Silicon Integrated Systems Corp. Method for fabricating conductive bumps and substrate with metal bumps for flip chip packaging
JP3680839B2 (en) * 2003-03-18 2005-08-10 セイコーエプソン株式会社 Semiconductor device and manufacturing method of semiconductor device
JP4534062B2 (en) 2005-04-19 2010-09-01 ルネサスエレクトロニクス株式会社 Semiconductor device
TWI283553B (en) * 2005-04-21 2007-07-01 Ind Tech Res Inst Thermal enhanced low profile package structure and method for fabricating the same
US7763963B2 (en) 2005-05-04 2010-07-27 Stats Chippac Ltd. Stacked package semiconductor module having packages stacked in a cavity in the module substrate
JP2007059767A (en) * 2005-08-26 2007-03-08 Shinko Electric Ind Co Ltd Substrate with electronic component mounted thereon employing underfill material and its manufacturing method
US7692295B2 (en) 2006-03-31 2010-04-06 Intel Corporation Single package wireless communication device
US7495321B2 (en) 2006-07-24 2009-02-24 Stats Chippac, Ltd. Leaded stacked packages having elevated die paddle
US8159828B2 (en) 2007-02-23 2012-04-17 Alpha & Omega Semiconductor, Inc. Low profile flip chip power module and method of making
JP4441545B2 (en) 2007-03-30 2010-03-31 Ｏｋｉセミコンダクタ株式会社 Semiconductor device
US7576434B2 (en) 2007-06-26 2009-08-18 Intel Corporation Wafer-level solder bumps
JP4986738B2 (en) 2007-06-27 2012-07-25 新光電気工業株式会社 Semiconductor package and semiconductor device using the same
JP5162226B2 (en) * 2007-12-12 2013-03-13 新光電気工業株式会社 Wiring substrate and semiconductor device
JP2009206286A (en) 2008-02-27 2009-09-10 Kyocera Corp Printed circuit board and portable electronic equipment using the same
US20100007015A1 (en) * 2008-07-11 2010-01-14 Bernardo Gallegos Integrated circuit device with improved underfill coverage
US7989950B2 (en) 2008-08-14 2011-08-02 Stats Chippac Ltd. Integrated circuit packaging system having a cavity
TW201017839A (en) * 2008-10-24 2010-05-01 Advanced Semiconductor Eng Substrate for window ball grid array package and mehtod for making the same
KR101089956B1 (en) * 2009-10-28 2011-12-05 삼성전기주식회사 Flip chip package and manufacturing method of the same
US8952552B2 (en) * 2009-11-19 2015-02-10 Qualcomm Incorporated Semiconductor package assembly systems and methods using DAM and trench structures
JP5342422B2 (en) * 2009-12-10 2013-11-13 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US8143110B2 (en) 2009-12-23 2012-03-27 Intel Corporation Methods and apparatuses to stiffen integrated circuit package
JP5481724B2 (en) * 2009-12-24 2014-04-23 新光電気工業株式会社 Semiconductor device embedded substrate
US9385095B2 (en) * 2010-02-26 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US8299595B2 (en) 2010-03-18 2012-10-30 Stats Chippac Ltd. Integrated circuit package system with package stacking and method of manufacture thereof
US8399300B2 (en) 2010-04-27 2013-03-19 Stats Chippac, Ltd. Semiconductor device and method of forming adjacent channel and DAM material around die attach area of substrate to control outward flow of underfill material
JP2012009586A (en) 2010-06-24 2012-01-12 Shinko Electric Ind Co Ltd Wiring board, semiconductor device and wiring board manufacturing method
US8525318B1 (en) 2010-11-10 2013-09-03 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
KR101817159B1 (en) 2011-02-17 2018-02-22 삼성전자 주식회사 Semiconductor package having TSV interposer and method of manufacturing the same
KR101740483B1 (en) 2011-05-02 2017-06-08 삼성전자 주식회사 Stack Packages having a Fastening Element and a Halogen-free inter-packages connector
TWI506738B (en) 2011-06-09 2015-11-01 Unimicron Technology Corp Semiconductor package and fabrication method thereof
US8409923B2 (en) * 2011-06-15 2013-04-02 Stats Chippac Ltd. Integrated circuit packaging system with underfill and method of manufacture thereof
US8815650B2 (en) 2011-09-23 2014-08-26 Stats Chippac Ltd. Integrated circuit packaging system with formed under-fill and method of manufacture thereof
KR101236797B1 (en) 2011-09-26 2013-02-25 앰코 테크놀로지 코리아 주식회사 Method for manufacturing semiconductor package
US8609462B2 (en) 2011-10-12 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming 3DIC package
US9123830B2 (en) 2011-11-11 2015-09-01 Sumitomo Bakelite Co., Ltd. Manufacturing method for semiconductor device
US8982577B1 (en) * 2012-02-17 2015-03-17 Amkor Technology, Inc. Electronic component package having bleed channel structure and method
US8587132B2 (en) * 2012-02-21 2013-11-19 Broadcom Corporation Semiconductor package including an organic substrate and interposer having through-semiconductor vias
US9842798B2 (en) * 2012-03-23 2017-12-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a PoP device with embedded vertical interconnect units
US9202714B2 (en) 2012-04-24 2015-12-01 Micron Technology, Inc. Methods for forming semiconductor device packages
US9502390B2 (en) * 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US20140048934A1 (en) 2012-08-15 2014-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method to control underfill fillet width
US9381529B2 (en) * 2012-09-13 2016-07-05 Skyworks Solutions, Inc. Systems, devices and methods related to paint recirculation during manufacture of radio-frequency modules
US9355924B2 (en) 2012-10-30 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit underfill scheme
JP6125209B2 (en) * 2012-11-19 2017-05-10 株式会社ジェイデバイス Semiconductor device and manufacturing method thereof
US8994176B2 (en) * 2012-12-13 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for package with interposers
US9431274B2 (en) * 2012-12-20 2016-08-30 Intel Corporation Method for reducing underfill filler settling in integrated circuit packages
US8987918B2 (en) 2013-03-14 2015-03-24 Intel Corporation Interconnect structures with polymer core
US20140291834A1 (en) * 2013-03-27 2014-10-02 Micron Technology, Inc. Semiconductor devices and packages including conductive underfill material and related methods
US9041205B2 (en) * 2013-06-28 2015-05-26 Intel Corporation Reliable microstrip routing for electronics components
US9343431B2 (en) 2013-07-10 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Dam structure for enhancing joint yield in bonding processes
US9659891B2 (en) * 2013-09-09 2017-05-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having a boundary structure, a package on package structure, and a method of making
US10056267B2 (en) 2014-02-14 2018-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US10026671B2 (en) 2014-02-14 2018-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9373559B2 (en) * 2014-03-05 2016-06-21 International Business Machines Corporation Low-stress dual underfill packaging
JP2015195263A (en) * 2014-03-31 2015-11-05 マイクロン テクノロジー， インク． Semiconductor device and manufacturing method or the same
US9638596B2 (en) 2014-04-08 2017-05-02 Freescale Semiconductor, Inc. Cavity-down pressure sensor device
US9627352B2 (en) * 2014-05-12 2017-04-18 Skyworks Solutions, Inc. Devices and methods for processing singulated radio-frequency units
US20160099192A1 (en) * 2014-07-31 2016-04-07 Skyworks Solutions, Inc. Dual-sided radio-frequency package having ball grid array
US20160111375A1 (en) * 2014-10-17 2016-04-21 Tango Systems, Inc. Temporary bonding of packages to carrier for depositing metal layer for shielding
TWI556387B (en) * 2015-04-27 2016-11-01 南茂科技股份有限公司 Multi chip package structure, wafer level chip package structure and manufacturing method thereof
US20170084594A1 (en) * 2015-09-20 2017-03-23 Qualcomm Incorporated Embedding die technology
US20170092594A1 (en) 2015-09-25 2017-03-30 Qualcomm Incorporated Low profile package with passive device
KR102468773B1 (en) 2015-10-19 2022-11-22 삼성전자주식회사 Semiconductor device
US9609746B1 (en) * 2015-12-14 2017-03-28 Unimicron Technology Corp. Circuit board structure and manufacturing method thereof
US9842788B2 (en) * 2015-12-31 2017-12-12 Taiwan Semiconductor Manufacturing Company, Ltd. Underfill control structures and method
KR102491574B1 (en) 2016-02-29 2023-01-25 삼성전자주식회사 Method of manufacturing semiconductor package
TWI578421B (en) 2016-04-29 2017-04-11 力成科技股份有限公司 Stackable semiconductor package and the method for manufacturing the same
WO2018067578A1 (en) * 2016-10-04 2018-04-12 Skyworks Solutions, Inc. Dual-sided radio-frequency package with overmold structure
IT201700091124A1 (en) * 2017-08-07 2019-02-07 Terno Scorrevoli S P A Unipersonale Device for the floor movement of sliding doors

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6291264B1 (en) * 2000-07-31 2001-09-18 Siliconware Precision Industries Co., Ltd. Flip-chip package structure and method of fabricating the same
US20090170242A1 (en) * 2007-12-26 2009-07-02 Stats Chippac, Ltd. System-in-Package Having Integrated Passive Devices and Method Therefor
US8314499B2 (en) * 2008-11-14 2012-11-20 Fairchild Semiconductor Corporation Flexible and stackable semiconductor die packages having thin patterned conductive layers
US20120083073A1 (en) * 2010-09-30 2012-04-05 Renesas Electronics Corporation Method of manufacturing semiconductor device
US8389339B2 (en) * 2010-09-30 2013-03-05 Renesas Electronics Corporation Method of manufacturing semiconductor device
US20160218093A1 (en) * 2011-08-16 2016-07-28 Intel Corporation Offset interposers for large-bottom packages and large-die package-on-package structures
US20140001644A1 (en) * 2012-06-29 2014-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package Structures and Methods for Forming the Same
US20140070348A1 (en) * 2012-09-07 2014-03-13 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and Apparatus for Sensor Module
US20150001729A1 (en) * 2013-06-27 2015-01-01 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Trench and Disposing Semiconductor Die Over Substrate to Control Outward Flow of Underfill Material
US20160260690A1 (en) * 2014-07-11 2016-09-08 Intel Corporation Scalable package architecture and associated techniques and configurations
US20180226272A1 (en) * 2017-01-31 2018-08-09 Skyworks Solutions, Inc. Control of under-fill using under-fill deflash for a dual-sided ball grid array package

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180096951A1 (en) * 2016-10-04 2018-04-05 Skyworks Solutions, Inc. Circuits and methods related to radio-frequency devices with overmold structure
US20180096950A1 (en) * 2016-10-04 2018-04-05 Skyworks Solutions, Inc. Radio-frequency device with dual-sided overmold structure
US10607944B2 (en) 2016-10-04 2020-03-31 Skyworks Solutions, Inc. Dual-sided radio-frequency package with overmold structure
US11961805B2 (en) 2016-10-04 2024-04-16 Skyworks Solutions, Inc. Devices and methods related to dual-sided radio-frequency package with overmold structure
US10410885B2 (en) 2017-01-31 2019-09-10 Skyworks Solutions, Inc. Control of under-fill using under-fill deflash for a dual-sided ball grid array package
US10460957B2 (en) 2017-01-31 2019-10-29 Skyworks Solutions, Inc. Control of under-fill using an encapsulant for a dual-sided ball grid array package
US10593565B2 (en) 2017-01-31 2020-03-17 Skyworks Solutions, Inc. Control of under-fill with a packaging substrate having an integrated trench for a dual-sided ball grid array package
US11201066B2 (en) 2017-01-31 2021-12-14 Skyworks Solutions, Inc. Control of under-fill using a dam on a packaging substrate for a dual-sided ball grid array package
KR20210082354A (en) 2019-12-25 2021-07-05 가부시키가이샤 무라타 세이사쿠쇼 Radio frequency module and communication device

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US20180226274A1 (en) 2018-08-09
US20220130686A1 (en) 2022-04-28
US20180226273A1 (en) 2018-08-09
US10593565B2 (en) 2020-03-17
KR20200106001A (en) 2020-09-10
US10770312B2 (en) 2020-09-08
US20200152483A1 (en) 2020-05-14
US11244835B2 (en) 2022-02-08
US20200075349A1 (en) 2020-03-05
US10410885B2 (en) 2019-09-10
US20210143024A1 (en) 2021-05-13
US10460957B2 (en) 2019-10-29
US20180218922A1 (en) 2018-08-02
US20180226272A1 (en) 2018-08-09
US11201066B2 (en) 2021-12-14

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