US8609462B2 - Methods for forming 3DIC package - Google Patents
Methods for forming 3DIC package Download PDFInfo
- Publication number
- US8609462B2 US8609462B2 US13/272,032 US201113272032A US8609462B2 US 8609462 B2 US8609462 B2 US 8609462B2 US 201113272032 A US201113272032 A US 201113272032A US 8609462 B2 US8609462 B2 US 8609462B2
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- United States
- Prior art keywords
- package component
- package
- curing
- underfill
- vacuuming
- Prior art date
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- Expired - Fee Related, expires
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- 238000000034 method Methods 0.000 title claims abstract description 49
- 238000007664 blowing Methods 0.000 claims abstract description 22
- 230000009471 action Effects 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims description 75
- 230000008569 process Effects 0.000 claims description 21
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 2
- 238000007669 thermal treatment Methods 0.000 claims 1
- 238000001723 curing Methods 0.000 description 33
- 239000002184 metal Substances 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000003989 dielectric material Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000012858 packaging process Methods 0.000 description 3
- 238000011415 microwave curing Methods 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 238000001029 thermal curing Methods 0.000 description 2
- 238000003848 UV Light-Curing Methods 0.000 description 1
- 239000002318 adhesion promoter Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000003302 ferromagnetic material Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 230000005291 magnetic effect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23Q—DETAILS, COMPONENTS, OR ACCESSORIES FOR MACHINE TOOLS, e.g. ARRANGEMENTS FOR COPYING OR CONTROLLING; MACHINE TOOLS IN GENERAL CHARACTERISED BY THE CONSTRUCTION OF PARTICULAR DETAILS OR COMPONENTS; COMBINATIONS OR ASSOCIATIONS OF METAL-WORKING MACHINES, NOT DIRECTED TO A PARTICULAR RESULT
- B23Q3/00—Devices holding, supporting, or positioning work or tools, of a kind normally removable from the machine
- B23Q3/18—Devices holding, supporting, or positioning work or tools, of a kind normally removable from the machine for positioning only
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Definitions
- dies may be packaged onto package substrates, which include metal connections that are used to route electrical signals between opposite sides of the package substrates.
- the dies may be bonded onto one side of a package substrate using flip chip bonding, and a reflow is performed to melt the solder balls that interconnect the dies and the laminate substrate.
- the package substrates may use materials that can be easily laminated.
- organic materials may be used as the dielectric materials of the package substrate. These materials, however, are prone to the warpage caused by the elevated temperatures used in the reflow of the solder.
- CTEs coefficients of thermal expansion
- the warpage in the dies and the package substrates is worsened.
- the silicon in the dies may have a CTE of 3.2
- the package substrates may have a CTE between about 17 and 20, or even higher.
- the warpage in the package substrates may cause irregular joints and/or bump cracks. As a result, the yield of the packaging process is adversely affected.
- FIGS. 1 through 6 are cross-sectional views and top views of intermediate stages in the manufacturing of a package in accordance with various embodiments.
- FIGS. 7A through 7F are exemplary configurations of the openings in the bottom jig.
- FIG. 1 illustrates a schematic top view of lower jig 20 .
- lower jig 20 may be formed of a dielectric material, a ferromagnetic material, or the like.
- Lower jig 20 may have a rectangular shape, although other shapes such as the rounded shape of a wafer may also be used.
- Lower jig 20 may comprise a plurality of through-openings 22 extending from the top side to the bottom side of lower jig 20 (please refer to FIGS. 4A through 5C ).
- the top-view shape of openings 22 may be circles, rectangles, strips, or other shapes. Openings 22 may be distributed throughout lower jig 20 .
- FIG. 2A illustrates a top view of package component 30 .
- Package component 30 may be a package substrate strip, and hence is referred to as package substrate strip 30 hereinafter, although package component 30 may be another type of package component such as an interposer.
- package substrate strip 30 includes a plurality of package substrates 32 that are identical to each other.
- package substrates 32 are distributed uniformly throughout package substrate strip 30 , and may have a pattern of an array.
- package substrates 32 may be disposed as a plurality of groups, with the inter-group spacing between the groups greater than the inner-group spacing between package substrates 32 that are in the same group.
- FIG. 2B schematically illustrates a cross-sectional view of one of package substrates 32 , wherein the cross-sectional view is obtained from the plane crossing line 2 B- 2 B in FIG. 2A .
- a plurality of connectors 36 which may be pre-solder regions, metal pads, or non-reflowable metal bumps, is formed on a side of package substrate 32 .
- Metal features 36 are electrically coupled to metal features such as bond pads 38 on the opposite side of package substrate 32 .
- Dashed lines 34 represent the electrical coupling between features 36 and 38 , and may include a plurality of metal lines and vias interconnecting the metal lines.
- FIG. 3 illustrates a top view of upper jig 40 in accordance with some embodiments.
- lower jig 20 and upper jig 40 in combination are referred to as a jig set.
- Upper jig 40 may also be formed of a dielectric material, a metal, or the like.
- Upper jig 40 may have a rectangular shape, and may have substantially the same top-view size as lower jig 20 ( FIG. 1 ).
- Upper jig 40 may include a plurality of openings 42 . The size of each of openings 42 may be great enough to allow one package substrate 32 ( FIG. 2 ), or a group of package substrates 32 to expose through when upper jig 40 is placed over lower jig 20 .
- FIG. 4A illustrates a cross-sectional view showing the bonding of package components 50 onto package substrates 32 .
- package components 50 may be dies (such as device dies comprising CMOS devices), packages, or the like.
- package substrate strip 30 is first placed on lower jig 20 .
- Upper jig 40 is placed on package substrate strip 30 , with package substrates 32 exposed through openings 42 in upper jig 40 .
- through-openings 22 of lower jig 20 may be, or may not be, aligned to openings 42 in upper jig 40 .
- Upper jig 40 may be clamped onto lower jig 20 .
- upper jig 40 and lower jig 20 may be attracted to each other through a magnetic force. Accordingly, package substrates 32 are fixed in position by upper jig 40 and lower jig 20 .
- Package components 50 are then placed on package substrates 32 , with the electrical features in one of package components 50 placed on, and electrically coupled to, the electrical features in a corresponding one of package substrates 32 .
- the bonding may be performed through solder bonding, wherein a reflow process is performed. Due to the heating and the temperature lowering steps in the reflow, after the reflow is finished, a warpage may be generated in package substrates 32 , and possibly in package components 50 .
- FIG. 4 illustrate the positive warpage generated in package substrates 32 and package components 50 .
- a positive warpage of a package component indicates that the central portion of the package component is higher than the edge portions of the package component.
- a warpage can be a negative warpage (not shown in FIG. 4A , please refer to FIG. 4B ), wherein the central portion of the package component is lower than the edge portions.
- underfill 52 is dispensed into the spacing between package components 50 and package substrates 32 , as shown in FIG. 5A , and the curing of the underfill 52 is performed to solidify underfill 52 .
- the curing is performed through a thermal process.
- Arrows 54 represents that vacuuming is performed through openings 22 in lower jig 20 during the curing of underfill 52 .
- the vacuuming may be started before the curing of underfill 52 is started, and may be started before, during, or after the dispensing of underfill 52 . At the time the vacuuming is started, underfill 52 is still a liquid.
- the vacuuming may be ended after the curing step is finished.
- the vacuuming may be ended wherein the dispensed underfill 52 is at least substantially solidified, or fully solidified.
- the vacuuming may be started before the heating action is started, and stopped when the temperatures of package components 50 , package substrate 32 , and/or underfill 52 are lowered to substantially equal to the room temperature.
- the pressure in air-pressure boat 60 when the vacuuming is performed may be between about 0.001 Torr and about 100 Torr, although higher pressures that are lower than one atmosphere may be used.
- FIGS. 4A and 5A also illustrate an exemplary embodiment wherein lower jig is integrated as a top surface part of air-pressure boat 60 , which includes inner space 62 .
- Openings 22 in lower jig 20 and pipe (outlet) 64 are connected to the same inner space 62 . Accordingly, by pumping air out of inner space 62 , inner space 62 and openings 22 are vacuumed. The vacuuming may be performed through pump 66 , which is connected to pipe 64 .
- FIG. 6 schematically illustrates the resulting package that includes package substrates 32 and package components 50 after the curing is finished.
- FIGS. 4A and 5A in combination illustrate that if the positive warpage occurs, the vacuuming is used in the underfill-curing process to reduce the warpage.
- FIGS. 4B and 5B in combination illustrate that if a negative warpage occurs, an air blowing is performed in the underfill-curing process to reduce the warpage.
- package components 50 are bonded to package substrate strip 30 .
- the bonding process is essentially the same as shown in FIG. 4A , except that the negative warpage is generated in package substrates 32 and package components 50 , and the center portion of package substrates 32 may be lower than the edge portions.
- FIGS. 5B and 5C illustrate the dispensing of underfill 52 into the spacing between package components 50 and package substrates 32 , and the curing of underfill 52 through a thermal process, for example.
- Underfill 52 may comprise epoxy resins, fillers, curing agents, adhesion promoters, and/or the like.
- An air blowing is performed through openings 22 in lower jig 20 , wherein arrows 55 represent the blowing direction of the air during the curing of underfill 52 .
- the air blowing may be started before the curing of underfill 52 is started, and may be started before, during, or after the dispensing of underfill 52 .
- the air blowing may be ended after the curing step is finished.
- the air blowing may be ended wherein the dispensed underfill 52 is at least substantially solidified, or fully solidified.
- the air blowing may be started before the respective heating process, and finished when the temperature is lowered to substantially equal to the room temperature.
- the pressure applied by the air blowing to package substrates 32 may be between about 1 atmosphere and about 10 atmospheres. It is realized that these values are merely examples, and may change depending on the material and the structure of package substrates 32 and package components 50 .
- the air blowing may be performed by blowing air into pipe 64 .
- the air as represented by arrows 55 , may be blown to openings 22 and in turn to package substrates 32 .
- the air blowing may be performed through air blower 67 , which is connected to pipe 64 .
- Air blower 67 in FIG. 5B and pump 66 in FIG. 5A may be the same device that is capable to drive air in opposite directions, and hence may operate as a pump when configured to drive air out of inner space 62 , and operate as an air blower when configured to drive air into inner space 62 . Due to the air blowing, an upward force is applied to package substrates 32 , and hence package substrates 32 are flattened. Since underfill 52 is cured with package substrates 32 being flattened, after the curing, package substrates 32 and package components 50 are substantially flat, or at least flatter than before the curing process. The warpage is thus reduced.
- FIG. 5C illustrates an underfill dispensing and curing process similar to what is shown in FIG. 5B , except that blocker 56 is added to prevent the over-correction of warpage.
- Blocker 56 comprises bottom surface 56 A in contact with top surfaces 50 A of package components 50 , and hence blocker 56 may prevent package substrates 32 from being blown upwardly. For example, assuming that the blowing force applied by air blower 67 on package substrates 32 is greater than necessary, if blocker 56 does not exist, package substrates 32 may have a positive warpage after the curing of underfill 52 . With blocker 56 being in the way of package substrates 32 , the upward movement of package substrates 32 is stopped by blocker 56 .
- Blocker 56 may be formed of metals, dielectric materials such as ceramics, organic materials, or the like. Blocker 56 may be clamped or screwed on air-pressure boat 60 , for example using the schematically illustrated clamps 61 . Alternatively, blocker 56 is not clamped or screwed, and stops the upward movement of package substrates 32 through the weight of blocker 56 . In some exemplary embodiments, the weight of blocker 56 applied to each of package components 32 may be between about 5 grams and about 5000 grams.
- the curing is a thermal curing with a temperature between about 50° C. and about 200° C.
- the duration of the thermal curing may be between about 10 minutes and about 200 minutes.
- the curing is a ultra-violet (UV) curing, wherein the duration of the UV curing may be between about 10 minutes and about 200 minutes.
- the curing is an Infrared Radiation (IR) curing, wherein the duration of the IR curing may be between about 10 minutes and about 200 minutes.
- the curing is a microwave curing, wherein the duration of the microwave curing may be between about 10 minutes and about 200 minutes.
- FIG. 6 schematically illustrates the package after the curing step (as shown in FIG. 5B or 5 C) is finished.
- FIGS. 7A through 7F illustrate some example configurations of openings 22 , wherein the top views of openings 22 may be obtained from the structure shown in FIGS. 5A and 5B .
- Package substrates 32 are also illustrated to show the relative positions of openings 22 and package substrates 32 .
- the top view shapes of openings 22 may be circles, rectangles (such as squares, strips, hexagons, octagons, or the like.
- openings 22 are uniformly distributed within the boundary of the respective package substrates 32 , and may have a substantially uniform size.
- openings 22 are uniformly distributed throughout lower jig 20 .
- the central opening 22 that corresponding to the center of each of package substrates 32 may have a size larger than remaining ones of openings 22 that are aligned to the same package substrate 32 .
- FIG. 7D there is one opening 22 under, and possibly aligned to the center, of each of package substrates 32 .
- openings 22 have strip shapes.
- FIG. 7F strip openings are distributed throughout lower jig 20 , wherein the strip openings may have various top-view shapes including crosses, for example. It is realized that these configurations are merely examples, and there are various alternative applicable configurations, as long as the needed air pressures may be applied through openings 22 during the curing of underfill 52 ( FIGS. 4A through 5C ).
- jigs may be used to press the package substrates from opposite sides.
- the jigs may include a lower jig and an upper jig.
- the upper jig typically has a grid pattern with openings therein, and a package substrate is sandwiched between the lower jig and the upper jig. Portions of the package substrate are exposed through the openings in the upper jig. Dies are bonded to the package substrate through the openings.
- jigs may alleviate the warpage, warpage still exists.
- a correction force is applied to the package components that are being packaged, either through vacuuming or air blowing. The warpage generated in the packaging process may thus be corrected.
- a method includes dispensing an underfill between a first package component and a second package component, wherein the first package component is placed on a lower jig, and the second package component is over and bonded to the first package component.
- a through-opening is in the lower jig and under the first package component.
- the underfill is cured, wherein during the step of curing the underfill, a force is applied to flatten the first package component. The force is applied by performing an action selected from the group consisting essentially of vacuuming and air blowing through the through-opening.
- a method includes placing a first package component over a lower jig, wherein the first package component covers an opening extending from a top surface to a bottom surface of the lower jig.
- An upper jig is placed over the first package component, wherein the upper jig secures the first package component on the lower jig.
- a second package component is bonded onto the first package component.
- An underfill is dispensed between the first package component and the second package component. The underfill is cured, wherein at a time between a starting time and an ending time of the step of curing the underfill, an action selected from the group consisting essentially of vacuuming and air blowing is performed, and wherein the action is performed through the through-opening.
- an air-pressure boat includes a lower jig at a top surface of the air-pressure boat.
- the lower jig comprises a through-opening extending from a top surface to a bottom surface of the lower jig.
- the device further includes an upper jig comprising an opening, wherein the upper jig is configured has a top-view size substantially equal to a top-view size of the lower jig.
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
Description
Claims (20)
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US13/272,032 US8609462B2 (en) | 2011-10-12 | 2011-10-12 | Methods for forming 3DIC package |
US14/096,263 US9073158B2 (en) | 2011-10-12 | 2013-12-04 | Methods for forming 3DIC package |
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US13/272,032 US8609462B2 (en) | 2011-10-12 | 2011-10-12 | Methods for forming 3DIC package |
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US14/096,263 Division US9073158B2 (en) | 2011-10-12 | 2013-12-04 | Methods for forming 3DIC package |
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US20130095608A1 US20130095608A1 (en) | 2013-04-18 |
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US13/272,032 Expired - Fee Related US8609462B2 (en) | 2011-10-12 | 2011-10-12 | Methods for forming 3DIC package |
US14/096,263 Active US9073158B2 (en) | 2011-10-12 | 2013-12-04 | Methods for forming 3DIC package |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140183760A1 (en) * | 2012-12-28 | 2014-07-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and Method to Improve Package and 3DIC Yield in Underfill Process |
US20140377571A1 (en) * | 2013-06-24 | 2014-12-25 | International Business Machines Corporation | Injection of a filler material with homogeneous distribution of anisotropic filler particles through implosion |
Families Citing this family (5)
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CN102382918B (en) * | 2011-10-11 | 2014-08-27 | 高征铠 | System and method for measuring blast furnace burden surface on line |
US10199351B2 (en) | 2015-12-30 | 2019-02-05 | Skyworks Solutions, Inc. | Method and device for improved die bonding |
US20180177045A1 (en) * | 2016-12-21 | 2018-06-21 | At&S Austria Technologie & Systemtechnik Aktiengesellschaft | Embedding Component in Component Carrier by Component Fixation Structure |
US10593565B2 (en) | 2017-01-31 | 2020-03-17 | Skyworks Solutions, Inc. | Control of under-fill with a packaging substrate having an integrated trench for a dual-sided ball grid array package |
CN115648532A (en) * | 2022-10-31 | 2023-01-31 | 长电科技管理有限公司 | Semiconductor package injection mold, injection device and semiconductor package injection method |
Citations (1)
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US7875496B2 (en) * | 2005-05-17 | 2011-01-25 | Panasonic Corporation | Flip chip mounting method, flip chip mounting apparatus and flip chip mounting body |
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JP3920172B2 (en) * | 2002-08-26 | 2007-05-30 | Necエレクトロニクス株式会社 | Lid holding frame and electronic component sealing method |
US7569471B2 (en) * | 2006-06-29 | 2009-08-04 | Intel Corporation | Method of providing mixed size solder bumps on a substrate using a solder delivery head |
-
2011
- 2011-10-12 US US13/272,032 patent/US8609462B2/en not_active Expired - Fee Related
-
2013
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US7875496B2 (en) * | 2005-05-17 | 2011-01-25 | Panasonic Corporation | Flip chip mounting method, flip chip mounting apparatus and flip chip mounting body |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140183760A1 (en) * | 2012-12-28 | 2014-07-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and Method to Improve Package and 3DIC Yield in Underfill Process |
US8945983B2 (en) * | 2012-12-28 | 2015-02-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method to improve package and 3DIC yield in underfill process |
US20140377571A1 (en) * | 2013-06-24 | 2014-12-25 | International Business Machines Corporation | Injection of a filler material with homogeneous distribution of anisotropic filler particles through implosion |
US9321245B2 (en) * | 2013-06-24 | 2016-04-26 | Globalfoundries Inc. | Injection of a filler material with homogeneous distribution of anisotropic filler particles through implosion |
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US9073158B2 (en) | 2015-07-07 |
US20140091509A1 (en) | 2014-04-03 |
US20130095608A1 (en) | 2013-04-18 |
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