TWI531013B - Wafer holding tool for flip chip bonding and method for flip chip bonding - Google Patents

Description

Wafer holding tool for flip chip bonding and method for flip chip bonding

The present invention relates to a structure of a wafer holding tool for flip chip bonding and a flip chip method using the wafer holding tool.

Regarding a method of mounting a semiconductor wafer as an electronic component on a substrate, a flip chip is widely used, that is, a plurality of bumps (protruding electrodes) are formed on a circuit surface of a semiconductor wafer by using a material such as solder, and the bump is used. The semiconductor wafer is directly bonded to the circuit substrate by heat fusion and bonding to a plurality of electrodes formed on the circuit substrate.

In the flip chip, a method of applying a thermosetting non-conductive paste (NCP) on a circuit board by a dispenser to push the heated semiconductor wafer to the electrode of the substrate is used. The bump is heated and melted to bond the semiconductor wafer to the substrate, and at the same time, the non-conductive paste (NCP) is heat-hardened by the semiconductor wafer to resin-sealate the semiconductor wafer and the circuit substrate (for example, refer to Patent Document 1) ).

The die bonding tool used in the flip chip is, for example, as shown in FIG. 1 or FIG. 2 of Patent Document 2, and includes a square substrate in a square shape and is adsorbed and disposed in the substrate. A thin rectangular parallelepiped wafer holding stage of a semiconductor wafer of the core. The size of the wafer holding stage is substantially the same as the size of the die-bonded semiconductor wafer. The die bonding tool is integrally formed to be thin so as to efficiently transfer the heat of the heater to the semiconductor wafer held by the wafer holding stage, and the height of the wafer holding stage protruding from the substrate becomes such that it does not contact the adjacent semiconductor wafer when the crystal is bonded. Height (for example, refer to Patent Document 2).

[Previous Technical Literature]

[Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2005-150446

[Patent Document 2] Japanese Patent Laid-Open Publication No. 2002-16091

However, in recent years, it has been increasingly required to bond a plurality of semiconductor wafers 45 to a substrate 40 with a narrow interstitial spacing. In this case, the wafer holding tool 100 can be replaced with a wafer holding tool having a small size of the wafer holding stage 105 according to the size of the die-bonded semiconductor wafer 45, and in many cases, the heater 20 is of the same size. The heater, and thus the size of the substrate 101 of the heater 20 fixed to the wafer holding tool 100, is substantially fixed regardless of the size of the semiconductor wafer 45. Therefore, as shown in FIG. 4, when the semiconductor wafer 45 is die-bonded at a die-pitch pitch XP narrower than the length C0 of the heater 20 or the substrate 101, the heater 20, or half the length C0 of the wafer holding tool 100 The length C1 is longer than 1/2 of the die bond pitch XP of the semiconductor wafer 45, so that the surface 102 extends to the upper surface of the unbonded non-conductive paste (NCP) 42 applied to the adjacent die position at the time of die bonding. And covered on it. The heater 20 heats the semiconductor wafer 45 to a temperature of 300 ° C to 350 ° C, so that the surface 102 of the wafer holding stage 105 also reaches a relatively high temperature, as shown in FIG. The surface of the unbonded non-conductive paste (NCP) 42 is heated as indicated by the lower arrow. If the non-conductive paste (NCP) 42 is heated to about 70 ° C, it will start to deteriorate in many cases, and as shown in FIG. 4, if it is heated to a high temperature by the surface 102 exposed to the periphery of the wafer holding stage 105, Sometimes it will start to deteriorate before the sticky crystal, or it will begin to harden. Therefore, the die pitch XP of the semiconductor wafer 45 is narrower than the heater 20, or the length C0 of the wafer holding tool 100, and the heat of the heater 20 is radiated from the surface 102 of the wafer holding tool 100 to the unbonded non-conductive paste ( In the case of NCP) 42, for example, a method in which a non-conductive paste (NCP) 42 is temporarily applied at every other die bonding position, and the semiconductor wafer 45 is bonded at this position, is again in the unbonded semiconductor. The position of the wafer 45 is coated with a non-conductive paste (NCP) 42, and the semiconductor wafer 45 is bonded at this position. In this way, the die-bonding pitch is set to twice the XP and the die-bonding is performed twice, so that there is a de-bonding crystal. The problem of time-consuming and sticky crystals becomes complicated.

It is an object of the present invention to perform a flip-chip bonding of a semiconductor wafer with a narrow interstitial spacing by a simple method.

The wafer holding tool of the present invention is a wafer holding tool for flip chip bonding, and includes: a base portion; and a wafer holding table protruding from a surface of the base portion and holding a semiconductor wafer on a front end surface thereof, the characteristics of the wafer holding tool The wafer holding stage is offset from the base portion, and the offset of the wafer holding stage is longer than the length obtained by subtracting 1/2 of the thickness of the semiconductor wafer from the 1/2 of the length of the base portion.

In the wafer holding tool of the present invention, preferably, the wafer holding table is preferably used. The offset is shorter than 1/2 of the width of the wafer holding stage.

A flip chip method for bonding a plurality of semiconductor wafers on a substrate, comprising: a step of setting a wafer holding tool on a flip chip device, the wafer holding tool comprising a base portion and a wafer holding table, the wafer The holding stage is offset from the base portion and protrudes from the surface of the base portion in such a manner that the semiconductor wafer is held on the front end surface, and the offset of the wafer holding stage is smaller than 1/2 of the length of the base portion minus the die bond of the semiconductor wafer The length obtained by 1/2 of the pitch is long; and the die bonding step alternately repeats the bonding of the semiconductor wafer toward the offset side of the wafer holding stage and the movement of the semiconductor wafer by the relative position of the wafer holding tool relative to the substrate The amount of the semiconductor wafer is thus bonded to the substrate.

The present invention achieves the effect that the semiconductor wafer can be flip-chip bonded with a narrow interstitial spacing by a simple method.

10, 100‧‧‧ wafer holding tools

11, 101‧‧‧ base

12, 41, 102‧‧‧ surface

13,103‧‧‧heater connection surface

15, 105‧‧‧ wafer holding station

16, 106‧‧‧ front end

17‧‧‧Adsorption holes

20‧‧‧heater

22‧‧‧ Lower surface

30‧‧‧ Sticky crystal head

40‧‧‧Substrate

42‧‧‧ Non-conductive paste

43,431-436‧‧‧ hardened resin

45, 451-456‧‧‧ semiconductor wafer

51, 52, 53, 61-63‧‧‧ center line

55, 65‧‧‧ center point

91, 92‧‧‧ arrows

C0‧‧‧Length length

C1‧‧‧ Length of half the length of the wafer holding tool

D0‧‧‧base length in the X direction

D1‧‧‧The length of the offset side of the wafer holding table in the X direction

D2‧‧‧ wafer holder length in the X direction

D3‧‧‧Deviation side length of the wafer holding table in the X direction

E0‧‧‧The length of the base in the Y direction

E1‧‧‧The length of the offset side of the wafer holding table in the Y direction

E2‧‧‧Y-direction length of wafer holding table

E3‧‧‧Deviation side length in the Y direction of the wafer holding table

H0‧‧‧The overall thickness of the wafer holding tool

H1, H2‧‧‧ thickness

X, Y, Z‧‧ Direction

XP, YP‧‧‧Core spacing

△X, △Y‧‧‧ offset

1(a) and 1(b) are a front view and a plan view of a wafer holding tool according to an embodiment of the present invention.

Fig. 2 is a vertical view showing a die bonding step performed by using a wafer holding tool according to an embodiment of the present invention.

Fig. 3 is a plan view showing a die bonding step of a wafer holding tool according to an embodiment of the present invention.

Figure 4 is a view showing a die bonding step performed using a wafer holding tool of the prior art Vertical view

Hereinafter, embodiments of the present invention will be described with reference to the drawings. As shown in FIGS. 1(a) and 1(b), the wafer holding tool 10 of the present embodiment includes a flat substrate 11 as a base portion fixed to the heater 20, and protrudes from the surface 12 of the substrate 11 and The wafer holding stage 15 of the semiconductor wafer is held at the front end face 16. Further, an adsorption hole 17 for adsorbing and fixing the semiconductor wafer is provided at the center of the front end surface 16. 1(a) and 1(b) show a state in which the wafer holding tool 10 is adsorbed and fixed to the lower surface 22 of the heater 20 fixed to the tip end of the die bonding head 30, and the substrate conveying direction of the flip chip bonding device is shown. In the X direction, a direction perpendicular to the X direction in the horizontal plane is referred to as a Y direction, and a vertical direction is referred to as a Z direction. The directions of XYZ in the following figures are also the same.

As shown in FIGS. 1(a) and 1(b), the base 11 is a rectangular flat plate having a thickness (Z direction) H1, a width (X direction) D0, and a depth (Y direction) E0, and is substantially the same as the heater 20. the size of. The heater connection surface 13 on the heater 20 side is fixed to the lower surface 22 (surface on the minus side in the Z direction) of the heater 20 by vacuum suction. The wafer holding stage 15 is disposed on the opposite side of the base 11 from the heater connection surface 13, and the front end surface 16 (the front end surface on the negative side in the Z direction) of the semiconductor wafer is adsorbed from the surface 12 of the substrate 11 at a height H2 to the Z direction. a base of a rectangular parallelepiped having a thickness (Z direction) H2, a width (X direction) D2, and a depth (Y direction) E2 protruding from the negative side, and the sides of the square wafer holding stage 15 in the XY direction are aligned with the XY direction of the substrate 11. Each side is configured in a parallel manner. The thickness H2 of the wafer holding stage 15 is as follows The degree, that is, when the semiconductor wafer is die-bonded, is not in contact with an adjacent semiconductor wafer or a non-conductive paste (NCP) 42 applied to the substrate. Moreover, the overall thickness of the wafer holding tool 10 is H0.

As shown in Fig. 1 (a) and Fig. 1 (b), the intersection of the center line 51 in the X direction of the base 11 and the center line 52 in the Y direction, that is, the center point 55 in the XY plane of the base 11, and the heater 20 The center point of the bonding head 30 in the XY plane is the same point. As shown in FIG. 1(a), the Z-direction center line 53 passing through the center point 55 is in the heater 20, the bonding head 30, and the substrate 11. Share. On the other hand, the center line 61 in the X direction and the center line 62 in the Y direction of the wafer holding stage 15 are at a distance ΔX and a distance ΔY from the center line 51 in the X direction of the base 11 and the center line 52 in the Y direction. The position is deviated from the negative side in the X direction and the positive side in the Y direction. Further, the intersection of the center line 61 in the X direction of the wafer holding stage 15 and the center line 62 in the Y direction, that is, the position of the center point 65 of the wafer holding stage 15 in the XY plane, and the center axis of the Z direction passing through the center point 65 63, also at the intersection of the center line 51 in the X direction from the base 11 and the center line 52 in the Y direction, that is, the center point 55 of the base 11 in the XY plane and the center line 53 are separated by ΔX and distance ΔY, respectively. The obtained position is shifted to the negative side in the X direction and the positive side in the Y direction. That is, the wafer holding stage 15 is disposed with respect to the base 11 and shifted by ΔX and ΔY with respect to the XY direction.

Therefore, the offset side length D1 of the wafer holding stage 15 in the X direction (the negative side length in the X direction from the Y direction center line 62 or the Z direction center line 63) is shorter than 1/2 of the X direction length D0 of the base 11 The X-direction offset amount ΔX (D1 = D0/2 - ΔX). Similarly, the offset side length of the wafer holding stage 15 in the Y direction E1 (the length in the Y direction from the X-direction center line 61 or the Z-direction center line 63) is also shorter than the 1/2 of the Y-direction length E0 of the base 11 by the Y-direction offset amount ΔY (E1=E0/ 2-△Y). Further, as shown in FIGS. 2 and 3, the X-direction offset amount ΔX and the Y-direction offset amount ΔY of the wafer holding stage 15 are long, for example, the length is the length D0 from the X direction of the substrate 11, 1/2 of the length E0 in the Y direction is obtained by subtracting 1/2 of the bonding pitch XP in the X direction of the semiconductor wafer 45 and the bonding pitch YP in the Y direction (ΔX>D0/2-XP/2), (Δ) Y>E0/2-YP/2). Therefore, the offset side length D1 in the X direction of the wafer holding stage 15 and the offset side length E1 in the Y direction are shorter than 1/2 of the die bond pitch XP in the X direction of the semiconductor wafer 45 and the die bond pitch YP in the Y direction ( D1<XP/2, E1<YP/2).

Therefore, as shown in FIGS. 2 and 3, at the time of die bonding, the surface 12 of each side of the wafer holding tool 10 in the X direction and the Y direction does not extend to the adjacent unbonded non-conductive paste (NCP) 42. Further, it is possible to suppress heating of the adjacent unbonded non-conductive paste (NCP) 42 at the time of die bonding.

Further, the center line 53 is a center line of a vertical load applied from the bonding head 30 in the Z direction via the heater 20, and the wafer holding stage 15 is disposed at a position passing through the Z-direction center line 53 of the center point of the substrate 11. The position of the front end face 16 of the wafer holding stage 15. In other words, the wafer holding stage 15 is disposed such that the Z-direction load is applied to the surface of the front end surface 16, so that the semiconductor wafer is not subjected to the eccentric load applied to the wafer holding stage 15 at the time of die bonding, and the semiconductor wafer is held by the wafer holding stage 15. The corner of the front end face 16 rotates centering. Therefore, the amounts of shift in the XY directions: ΔX and ΔY are smaller than 1/2 of the length D2 of the wafer holding stage 15 and the length E2 of the Y direction, respectively.

Next, a method of bonding the semiconductor wafer 45 to the substrate 40 using the wafer holding tool 10 described with reference to FIG. 1 will be described with reference to FIGS. 2 and 3.

First, the wafer holding tool 10 of the present embodiment described with reference to FIG. 1 is suction-fixed to the lower surface 22 of the heater 20 fixed to the die bonding head 30. At this time, the respective sides of the wafer holding tool 10 are aligned with the respective sides of the heater 20, and the offset sides of the wafer holding stage 15 in the XY direction are respectively the negative side in the X direction and the negative side in the Y direction. The adsorption is fixed to the lower surface 22 of the heater 20.

Next, as shown in FIGS. 2 and 3, a non-conductive paste (NCP) 42 is applied to each position of the surface 41 of the substrate 40 of the die-bonded semiconductor wafer 45 by a dispenser (not shown). The non-conductive paste (NCP) 42 is coated in an X shape as shown in FIG. 3, which intersects at the center of the position of the die-bonded semiconductor wafer 45, and has a length which is a diagonal length of the die-bonded semiconductor wafer 45. The coated non-conductive paste (NCP) 42 is convex from the surface 41 of the substrate 40 as shown in FIG.

After the non-conductive paste (NCP) 42 is applied onto the substrate 40, the substrate 40 is heated to about 70 ° C on a pre-heating stage (not shown), and then adsorbed and fixed to a die-plated platform (not shown). The die bonding platform maintains the temperature of the substrate 40 at about 70 °C. Next, the adsorption hole 17 of the front end surface 16 of the wafer holding stage 15 is vacuumed, and the semiconductor wafer 45 is suction-fixed to the front end surface 16, the heater 20 is turned on, and the semiconductor wafer 45 is heated to 300 to 350 °C. After the semiconductor wafer 45 is heated, as shown in FIG. 2, the die pad 30 is lowered, and the semiconductor wafer 45 adsorbed on the front end surface 16 of the wafer holding stage 15 is pressed against the non-conductive paste (NCP) 42. Thus, through the heater The solder of the bump (not shown) of the semiconductor wafer 45 which is melted by the heating of 20 is melted and bonded to the electrode of the substrate 40. Further, when the semiconductor wafer 45 is pressed to the non-conductive paste 42, the non-conductive paste (NCP) 42 covers the entire surface of the semiconductor wafer 45 on the side of the substrate 40, and a part thereof is pushed in such a manner as to be slightly exposed to the periphery of the semiconductor wafer 45. open. Then, it is hardened by heat from the semiconductor wafer 45, and as shown in FIG. 2, becomes a hardened resin 43 which fills a gap between the substrate 40 and the semiconductor wafer 45.

The die bond of the semiconductor wafer 45 is sequentially performed toward the offset sides of the XY of the wafer holding stage 15 as shown by the hollow arrow 91 and the hollow arrow 92 shown in FIG. Hereinafter, the step of the die bonding will be described with reference to Fig. 3 . As shown in FIG. 3, first, the semiconductor wafer 451 is bonded to the upper right corner position (the positive side in the X direction and the positive side in the Y direction) of the substrate 40. The non-conductive paste (NCP) 42 is hardened between the semiconductor wafer 451 and the substrate 40 and around the semiconductor wafer 451 to become the cured resin 431. After the die bonding of the semiconductor wafer 451 is completed, the substrate 40 is moved by the amount of the Y-direction grain pitch YP toward the positive side in the Y direction by a die-plating platform (not shown). Then, the position of the bonding head 30 is shifted with respect to the substrate 40 by the Y-direction viscous pitch YP toward the negative side in the Y direction as in the hollow arrow 92 of FIG. Then, the die 30 is lowered and the semiconductor wafer 452 is bonded at the next die position. Then, the movement of the die bond crystal of the semiconductor wafer and the die pad platform (not shown) are alternately repeated, whereby the semiconductor wafer 453 and the semiconductor wafer 454 are sequentially bonded. After the die bonding of the semiconductor wafer 454 is completed, the die-bonding platform (not shown) is moved in the X-direction positive side by the X-direction die-pitch pitch XP, and the die-bonding platform is moved to the Y-direction negative side by 4 pieces of the die-bonding pitch (4× YP). That is, the die head 30 is moved to the negative side in the X direction by XP as shown by the hollow arrow 91 of FIG. 3 with respect to the substrate 40. And moving the amount of 4-bonding pitch (4 × YP) to the positive side in the Y direction. Next, the die bonding head 30 is lowered to bond the semiconductor 455 shown in FIG. As shown in FIG. 3, as shown by the hollow arrow 91 and the hollow arrow 92, the die head 30 is sequentially moved toward the offset side (the negative side in the X direction and the positive side in the Y direction) while being bonded to the substrate 40. Wafer 45.

As shown in FIGS. 2 and 3, the offset side length D1 in the X direction and the offset side length E1 in the Y direction of the wafer holding stage 15 are larger than the X-direction gap pitch XP of the semiconductor wafer 45 and the Y-direction gap pitch YP. 1/2 short. Therefore, at the time of die bonding, the surface 12 on each offset side in the X direction and the Y direction of the wafer holding tool 10 does not extend to the adjacent unbonded non-conductive paste (NCP) 42 so that the adhesion can be suppressed. Adjacent unbonded non-conductive paste (NCP) 42 is heated. Further, as described above, the die bonding head 30 is moved toward the offset side (the negative side in the X direction and the positive side in the Y direction) while the die pad 30 is moved to the semiconductor wafer 451 to the semiconductor wafer 456. The non-conductive paste (NCP) 42 disposed at the unbonded position is sequentially bonded to the adjacent semiconductor wafer 451 to semiconductor wafer 456 in a state where the offset side of the surface 12 of the wafer holding tool 10 is not covered. Therefore, by using the wafer holding tool 10 of the present embodiment, the Zigzag pitch XP in the X direction and the YP pitch in the Y direction of the semiconductor wafer 45 are larger than the size of the heater 20 or the wafer holding tool 10. When the sizes D0 and E0 of the substrate 11 are narrow, the temperature of the non-conductive paste (NCP) 42 applied to the unbonded crystals can be suppressed from rising, so that the semiconductor wafer 45 can be sequentially bonded at the adjacent positions. A large number of semiconductor wafers 45 can be bonded to the substrate 40 in a short time. In addition, as shown in FIGS. 2 and 3, the wafer holding stage 15 The reverse shift side length D3 in the X direction and the reverse shift side length E3 in the Y direction are longer than 1/2 of the die bond pitch XP in the X direction of the semiconductor wafer 45 and the die bond pitch YP in the Y direction, and The surface 12 of the substrate 11 covers the adjacent semiconductor wafer 451 to the semiconductor wafer 455 which have been completed, but the non-conductive paste 42 of this portion has been thermally hardened to become the hardened resin 431 to the hardened resin 435, so that even the substrate 11 is received. There is no problem with surface 12 heating.

The embodiment described above achieves the effect that the semiconductor wafer 45 can be sequentially crystal-molded by a narrow die-bonding pitch by a simple method of shifting the wafer holding stage 15 with respect to the substrate 11.

In the embodiment described above, the wafer holding tool 10 is formed in a quadrangular shape, and the wafer holding table 15 is also formed in a quadrangular shape. However, the shape is not limited to four sides, and may be circular or other shapes such as an elliptical shape.

10‧‧‧ wafer holding tool

11‧‧‧Base

12‧‧‧ surface

13‧‧‧heater connection surface

15‧‧‧ wafer holding station

16‧‧‧ front end

20‧‧‧heater

22‧‧‧ Lower surface

30‧‧‧ Sticky crystal head

53, 63‧‧‧ center line

D0‧‧‧base length in the X direction

D1‧‧‧The length of the offset side of the wafer holding table in the X direction

D2‧‧‧ wafer holder length in the X direction

D3‧‧‧Deviation side length of the wafer holding table in the X direction

H0‧‧‧The overall thickness of the wafer holding tool

H1, H2‧‧‧ thickness

△X‧‧‧ offset

X, Y, Z‧‧ Direction

Claims (3)

A wafer holding tool, which is a wafer holding tool for flip chip bonding, and includes: a base portion; and a wafer holding table protruding from a surface of the base portion and holding a semiconductor wafer on a front end surface thereof, the wafer holding tool being characterized The wafer holding stage is offset from the base portion, and the offset of the wafer holding stage is longer than a length obtained by subtracting 1/2 of the die gap of the semiconductor wafer from 1/2 of the length of the base portion. . The wafer holding tool according to claim 1, wherein the wafer holding stage has a shift amount shorter than 1/2 of a width of the wafer holding stage. A flip chip method for bonding a plurality of semiconductor wafers on a substrate, comprising: a step of setting a wafer holding tool on a flip chip device, the wafer holding tool comprising a base portion and a wafer holding table, the wafer The holding stage is offset from the base portion, and protrudes from the surface of the base portion so as to hold the semiconductor wafer on the front end surface, and the offset amount of the wafer holding table is smaller than 1/2 of the length of the base portion. The length of the 1/2 of the die-bonding pitch of the semiconductor wafer is long; and the die bonding step alternately repeats the bonding of the semiconductor wafer to the offset side of the wafer holding stage and the wafer holding tool relative to the substrate Moving the amount of the die-bonding pitch of the semiconductor wafer relative to the position to thereby pass the plurality of semiconductors The wafer is bonded to the substrate.