JP2013162022A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can successfully and electrically connect semiconductor chips respectively having bump electrodes arranged in different layouts, and which can prevent an underfill material from adhering to the bump electrodes which function as external connection terminals of a chip stack.SOLUTION: A semiconductor device manufacturing method comprises: preparing a first semiconductor chip 11 which includes first bump electrodes 19 arranged on one surface and another flat surface 11b, and a second semiconductor chip 13 which includes second bump electrodes 27 on one surface 13a and third bump electrodes 28 arranged on another surface in a layout different from that of the second bump electrodes 27; and forming a sacrificial adhesive layer 14 for covering the one surface 13a of the second semiconductor chip 13 and the second bump electrodes 27 before forming an underfill material.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In Patent Document 1, after a plurality of semiconductor chips having bump electrodes are stacked to form a chip stack, an underfill material is filled between the chips of the chip stack, and the chip stack is mounted on a wiring board. A method for manufacturing a (Chip on Chip) type semiconductor device is disclosed.

  Patent Document 2 discloses a technique for pressing the bump surface of the interposer with a pressing jig having a heat-resistant rubber sheet attached to the lower surface to connect the interposer to the wiring board.

JP 2010-251347 A JP 2007-027337 A

  By the way, when manufacturing a CoC type semiconductor device by stacking semiconductor chips having different bump electrode arrangement positions using the method of manufacturing a semiconductor device described in Patent Document 1, there are the following two problems.

  The first problem is that a good load is applied directly under the bump electrode pressed by the bonding tool, but a sufficient load cannot be applied to other parts, resulting in poor bonding between the bump electrodes. May occur.

  The second problem is that when the underfill material is filled between the semiconductor chips, the underfill material rides on the semiconductor chip arranged in the uppermost layer, and the bump electrode (chip laminated body) of the semiconductor chip arranged in the uppermost layer. The bump electrodes functioning as external connection terminals of the circuit board are covered with the underfill material, which may cause a poor electrical connection between the wiring board and the chip stack.

  The technique described in Patent Document 2 can be used to solve the first problem, but it is difficult to solve the second problem.

  According to one aspect of the present invention, the first bump electrode disposed on one surface, the first semiconductor chip having a flat other surface, the second bump electrode disposed on one surface, and the other surface on the other surface A step of preparing a second semiconductor chip having a third bump electrode arranged in a layout different from that of the second bump electrode, and a first surface in contact with one surface of the second semiconductor chip Forming a sacrificial adhesive layer covering one surface of the second bump electrode and the second semiconductor chip such that the second surface located on the opposite side is a flat surface; and the first bump electrode And the third bump electrode are electrically connected to form a chip stack including the first and second semiconductor chips stacked and mounted; and after forming the chip stack, 1 semiconductor chip and the second semiconductor chip A step of filling an underfill material between, after filling the underfill material, a method of manufacturing a semiconductor device which comprises a step of removing the sacrificial adhesive layer is provided.

  According to the method for manufacturing a semiconductor device of the present invention, the second bump is so formed that the second surface located on the side opposite to the first surface contacting the one surface of the second semiconductor chip is a flat surface. By forming the sacrificial adhesive layer that covers the electrode and one surface of the second semiconductor chip, for example, the second surface of the sacrificial adhesive layer is adsorbed by a bonding tool and is attached to the first semiconductor chip disposed below. When the second semiconductor chip is pressed to electrically connect the first bump electrode and the third bump electrode, a sufficient pressure is applied to the entire one surface side of the second semiconductor chip via the sacrificial adhesive layer. Therefore, the first bump electrode and the third bump electrode can be electrically connected satisfactorily.

  Further, a second semiconductor chip is arranged on the stage so that the upper surface of the stage and the second surface (flat surface) of the sacrificial adhesive layer are in contact with each other, and the second semiconductor chip is bonded to the second semiconductor chip by a bonding tool When the first semiconductor chip is pressed, the sacrificial adhesive layer suppresses deformation of the second semiconductor chip (deformation due to the difference between the layouts of the second and third bump electrodes). Since sufficient pressure can be applied to the other surface side, the first bump electrode and the third bump electrode can be electrically connected well.

  Also, after forming the chip stack, before filling the underfill material between the first semiconductor chip and the second semiconductor chip, the sacrificial adhesion covering the one surface of the second semiconductor chip and the second bump electrode By forming the layer and removing the sacrificial adhesive layer after forming the underfill material, the underfill material does not adhere to the second bump electrode.

  Thereby, after removing the sacrificial adhesive layer, when the chip laminated body on which the underfill material is formed is mounted on the wiring board, the fourth bump electrode of the chip laminated body (bump electrode functioning as an external connection terminal of the chip laminated body) ) And the connection pads of the wiring board can be improved.

It is sectional drawing (the 1) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing (the 2) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing (the 3) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing (the 4) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing (the 5) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing (the 6) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing (the 7) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing (the 8) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing (the 9) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing (the 10) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing (the 11) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing (the 12) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing (the 13) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing (the 14) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing (the 15) which shows the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing (the 1) which shows the manufacturing process of the 3rd semiconductor chip in which the sacrificial contact bonding layer was formed. It is sectional drawing (the 2) which shows the manufacturing process of the 3rd semiconductor chip in which the sacrificial contact bonding layer was formed. It is sectional drawing (the 3) which shows the manufacturing process of the 3rd semiconductor chip in which the sacrificial contact bonding layer was formed. It is sectional drawing (the 4) which shows the manufacturing process of the 3rd semiconductor chip in which the sacrificial contact bonding layer was formed. It is sectional drawing (the 5) which shows the manufacturing process of the 3rd semiconductor chip in which the sacrificial contact bonding layer was formed. It is sectional drawing (the 6) which shows the manufacturing process of the 3rd semiconductor chip in which the sacrificial contact bonding layer was formed. It is sectional drawing (the 7) which shows the manufacturing process of the 3rd semiconductor chip in which the sacrificial contact bonding layer was formed. It is sectional drawing (the 8) which shows the manufacturing process of the 3rd semiconductor chip in which the sacrificial contact bonding layer was formed. It is sectional drawing (the 1) which shows the manufacturing process of the semiconductor device which concerns on the modification of embodiment of this invention. It is sectional drawing (the 2) which shows the manufacturing process of the semiconductor device which concerns on the modification of embodiment of this invention. It is sectional drawing (the 3) which shows the manufacturing process of the semiconductor device which concerns on the modification of embodiment of this invention. It is sectional drawing which shows the modification of a chip laminated body.

  Embodiments to which the present invention is applied will be described below in detail with reference to the drawings. The drawings used in the following description are for explaining the configuration of the embodiment of the present invention, and the size, thickness, dimensions, and the like of each part shown in the drawings are different from the dimensional relationship of an actual semiconductor device. There is a case.

(Embodiment)
1 to 15 are cross-sectional views showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.
With reference to FIGS. 1-15, the manufacturing method of the semiconductor device 10 (refer FIG. 15) of this Embodiment is demonstrated. In the present embodiment, a CoC type semiconductor device is taken as an example of the semiconductor device 10 and the following description is given.

  First, in the process shown in FIG. 1, the separated first semiconductor chip 11, the separated third semiconductor chip 12, and the sacrificial adhesive layer 14 are formed and separated. A second semiconductor chip 13 is prepared.

Here, the configuration of the first to third semiconductor chips 11, 13, 12 and the sacrificial adhesive layer 14 will be described with reference to FIG.
The first semiconductor chip 11 is a thinned semiconductor chip. The first semiconductor chip 11 is connected to the wiring substrate 92 when the chip stacked body 65 composed of the first to third semiconductor chips 11, 13, 12 mounted in a stacked manner is mounted on the wiring substrate 92 in the step shown in FIG. This is a semiconductor chip arranged at a position farthest from the substrate 92.
As the first semiconductor chip 11, for example, a semiconductor chip for memory can be used. Hereinafter, a case where a semiconductor chip for memory is used as the first semiconductor chip 11 will be described as an example.

The first semiconductor chip 11 includes a thinned semiconductor substrate 16, a circuit element layer 17, and a first bump electrode 19 (surface bump electrode).
The semiconductor substrate 16 is a rectangular substrate, and for example, a single crystal silicon substrate can be used. The circuit element layer 17 is provided on the surface 16 a of the semiconductor substrate 16. A circuit element for memory (not shown) is formed in the circuit element layer 17.

A plurality of first bump electrodes 19 are arranged on one surface 11 a of the first semiconductor chip 11 (the surface 17 a of the circuit element layer 17). The first bump electrode 19 is electrically connected to a memory circuit element (not shown).
The other surface 11b of the first semiconductor chip 11 (the back surface 16b of the semiconductor substrate 16) is a flat surface.

The third semiconductor chip 12 is a thinned semiconductor chip (for example, a thickness of 50 μm or less). As the third semiconductor chip 12, for example, a memory semiconductor chip can be used. Hereinafter, a case where a memory semiconductor chip is used as the third semiconductor chip 12 will be described as an example.
The third semiconductor chip 12 excludes the first bump electrode 19 provided on the first semiconductor chip 11 from the constituent elements, and also includes a fourth bump electrode 22 (surface bump electrode) and a fifth bump electrode 23 ( The back semiconductor device is configured in the same manner as the first semiconductor chip 11 except that the back surface bump electrode) and the through electrode 24 are provided.

  A plurality of fourth bump electrodes 22 are arranged on one surface 12a of the third semiconductor chip 12 (the surface 17a of the circuit element layer 17). The fourth bump electrode 22 is arranged in the same layout as the fifth bump electrode 23. That is, the fourth bump electrode 22 is disposed so as to face the fifth bump electrode 23.

A plurality of fifth bump electrodes 23 are provided on the other surface 12 b of the third semiconductor chip 12 (the back surface 16 b of the semiconductor substrate 16). The fifth bump electrode 23 is arranged in the same layout as the first bump electrode 19 provided on the first semiconductor substrate 11. Thus, the fifth bump electrode 23 is disposed so as to face the first bump electrode 19.
That is, the first, fourth, and fifth bump electrodes 19, 22, and 23 are bump electrodes that are arranged in the same layout.

The through electrode 24 passes through the semiconductor substrate 16 and the circuit element layer 17 located between the fourth bump electrode 22 and the fifth bump electrode 23. The through electrode 24 is electrically connected to a memory circuit element (not shown) provided in the circuit element layer 17.
The through electrode 24 has one end connected to the fourth bump electrode 22 and the other end connected to the fifth bump electrode 23. Thereby, the through electrode 24 electrically connects the fourth bump electrode 22 and the fifth bump electrode 23.

  The second semiconductor chip 13 is a thinned semiconductor chip (for example, a thickness of 50 μm or less). For example, an interface semiconductor chip can be used as the second semiconductor chip 13. Hereinafter, a case where an interface semiconductor chip is used as the second semiconductor chip 13 will be described as an example.

  The second semiconductor chip 13 excludes the first bump electrode 19 and the circuit element layer 17 provided on the first semiconductor chip 11 from the constituent elements, and the circuit element layer 26 and the second bump electrode 27 (surface bumps). Electrode), a third bump electrode 28 (back bump electrode), and a through electrode 29 are provided, and the configuration is the same as that of the first semiconductor chip 11.

The circuit element layer 26 is provided on the surface 16 a of the semiconductor substrate 16. An interface circuit element (not shown) is formed in the circuit element layer 26.
A plurality of second bump electrodes 27 are arranged on one surface 13a of the second semiconductor chip 13 (the surface 26a of the circuit element layer 26). As shown in FIG. 12 described later, the second bump electrode 27 is a bump electrode that functions as an external connection terminal of the chip stack 65 and is connected to the connection pad 96 of the wiring substrate 92.

  The second bump electrode 27 is a bump electrode arranged in a layout different from that of the third bump electrode 28. In FIG. 1, as an example, the second bump electrode 27, which has a smaller number than the third bump electrode 28 and is electrically connected to a part of the third bump electrode 28 through the through electrode 29, is illustrated. Show.

  A plurality of third bump electrodes 28 are provided on the other surface 13 b of the second semiconductor chip 13 (the back surface 16 b of the semiconductor substrate 16). The third bump electrode 28 is a bump electrode arranged in the same layout as the fourth bump electrode 22. That is, the third bump electrode 28 is disposed so as to face the fourth bump electrode 22.

The through electrode 29 passes through the semiconductor substrate 16 and the circuit element layer 26 located between the second bump electrode 27 and the third bump electrode 28. The through electrode 29 is electrically connected to an interface circuit element provided in the circuit element layer 26.
The through electrode 29 has one end connected to the second bump electrode 27 and the other end connected to the third bump electrode 28. Thereby, the through electrode 29 electrically connects the second bump electrode 27 and the third bump electrode 28.

The sacrificial adhesive layer 14 has a thickness for embedding the second bump electrodes 27 and is provided so as to cover the plurality of second bump electrodes 27 and the one surface 13 a of the second semiconductor chip 13.
The material of the sacrificial adhesive layer 14 may be any material that can protect the plurality of second bump electrodes 27 and the one surface 13 a of the second semiconductor chip 13. Specifically, as the material of the sacrificial adhesive layer 14, for example, an ultraviolet curable acrylic adhesive can be used.
When the height of the second bump electrode 27 is 20 μm, the thickness of the sacrificial adhesive layer 14 can be set to 50 μm, for example.

  In the step of forming the sacrificial adhesive layer 14, the second surface 14 b of the sacrificial adhesive layer 14 located on the side opposite to the first surface 14 a of the sacrificial adhesive layer 14 that contacts the one surface 13 a of the second semiconductor chip 13 is formed. Form on a flat surface.

Since the first semiconductor chip 11 is not formed with the back bump electrode and the through electrode, the first semiconductor chip 11 is made thicker than the second and third semiconductor chips 13 and 12. Also good.
Specifically, when the thickness of the second and third semiconductor chips 13 and 12 is 50 μm, the thickness of the first semiconductor chip 11 can be set to 100 μm, for example.

As described above, when the chip stack 65 is mounted on the wiring board 92 (see FIG. 12), the first semiconductor is disposed at the position farthest from the wiring board 92 and the back bump electrode and the through electrode are not formed. By increasing the thickness of the chip 11, chip cracks due to stress applied to the first semiconductor chip 11 can be reduced by heating after mounting the chip stack 65.
After the step shown in FIG. 1, the process continues to the step shown in FIG.

  16 to 23 are cross-sectional views showing a manufacturing process of the third semiconductor chip on which the sacrificial adhesive layer is formed. 16, the same components as those of the second semiconductor chip 13 and the sacrificial adhesive layer 14 shown in FIG.

  Here, with reference to FIGS. 16 to 23, a method of manufacturing the second semiconductor chip 13 on which the sacrificial adhesive layer 14 prepared in the process shown in FIG. 1 is formed will be described.

First, in the process shown in FIG. 16, a semiconductor substrate 36 (for example, a single crystal silicon wafer) having a plurality of chip formation regions A partitioned by dicing lines B is prepared.
The semiconductor substrate 36 becomes a semiconductor substrate 16 constituting the second semiconductor chip 13 shown in FIG. 1 by cutting along the dicing line B after being thinned. That is, the semiconductor substrate 36 is a substrate that serves as a base material for the plurality of semiconductor substrates 16. The surface 36 a of the semiconductor substrate 36 coincides with the surface 16 a of the semiconductor substrate 16.

Next, the circuit element layer 26 is formed on the surface 36a of the semiconductor substrate 36 by a known technique, and then the second bump electrode 27 is formed on the surface 26a of the circuit element layer 26 by a known technique.
At this time, the second bump electrode 27 has a different layout from the first and third to fifth bump electrodes 19, 28, 22, 23 and the third bump electrode 28 having the same layout. Form.

  Next, in the process shown in FIG. 17, after the structure shown in FIG. 16 is turned upside down, the surface 26 a of the circuit element layer 26 and the upper surface 42 a of the support substrate 42 are opposed to each other through the adhesive member 41. The semiconductor substrate 36 on which the circuit element layer 26 and the second bump electrode 27 are formed is attached to the support substrate 42.

As the adhesive member 41, a first adhesive layer 44 that is in contact with the surface 26 a of the circuit element layer 26 and has a thickness for embedding the plurality of second bump electrodes 27, the first adhesive layer 44, and the support substrate 42. And a member in which a second adhesive layer 45 that is in contact with the upper surface 42a of the support substrate 42 is laminated is used.
The first adhesive layer 44 is an adhesive layer that becomes a base material of the plurality of sacrificial adhesive layers 14. As a material of the first adhesive layer 44, for example, an ultraviolet curable acrylic adhesive can be used.

  Further, the thickness M of the first adhesive layer 44 is preferably larger than the height value of the second bump electrode 27. Specifically, when the height of the second bump electrode 27 is 20 μm, the thickness M of the first adhesive layer 44 can be set to 50 μm, for example.

  Thus, by making the thickness M of the first adhesive layer 44 larger than the height value of the second bump electrode 27, it becomes possible to embed a plurality of second bump electrodes 27, and the second 2nd of the 1st adhesion layer 44 located on the opposite side to the 1st surface 44a (the 1st surface 14a of sacrificial adhesion layer 14) of the 1st adhesion layer 44 which contacts one side 13a of semiconductor chip 13 of this The surface 44b (the second surface 14b of the sacrificial adhesive layer 14 to which the bonding tool 61 shown in FIG. 4 described later is adsorbed) can be formed on a flat surface.

  As the material of the second adhesive layer 45, for example, a material whose adhesive strength is reduced by application of specific energy, for example, an adhesive whose adhesive strength is reduced by heat or light can be used. Alternatively, as the material of the second adhesive layer 45, a material that is vaporized by laser light irradiation, such as LTHC (manufactured by Sumitomo 3M Limited), may be used.

  By using the adhesive member 41 configured as described above, the semiconductor substrate 36 on which the circuit element layer 26 and the second bump electrode 27 are formed is attached to the support substrate 42, thereby damaging the second bump electrode 27. Can be suppressed.

Next, in the step shown in FIG. 18, the semiconductor substrate 36 is thinned by grinding and / or polishing the semiconductor substrate 36 from the back surface 36b side of the semiconductor substrate 36 shown in FIG. At this time, the thickness of the thinned semiconductor substrate 36 is set to be equal to the thickness of the semiconductor substrate 16 constituting the second semiconductor chip 13 shown in FIG.
As a result, the semiconductor substrate 16 constituting the second semiconductor chip 13 shown in FIG. 1 is formed in each chip formation region A. In this step, the plurality of semiconductor substrates 16 are connected and are not separated.

  Next, in the process shown in FIG. 19, the semiconductor substrate 36 and the circuit element layer 26 which are thinned by a well-known technique are penetrated, and the through-electrode 29 having one end connected to the second bump electrode 27 and the semiconductor substrate 36. The third bump electrode 28 is formed on the back surface 36 b (the back surface 16 b of the semiconductor substrate 16) and a part of which is connected to the other end of the through electrode 29.

As a result, a third semiconductor chip mother board 48 in which a structure corresponding to the second semiconductor chip 13 is formed in the plurality of chip formation regions A is formed. At this stage, the plurality of second semiconductor chips 13 are connected and are not separated.
In the step shown in FIG. 19, the third bump electrode 28 is formed to have the same layout as the first, second, fourth, and fifth bump electrodes 19, 27, 22, and 23.

  Next, in the process shown in FIG. 20, a dicing tape 49 having a dicing tape main body 51 and an adhesive layer 52 laminated on one surface 51a of the dicing tape main body 51 is prepared, and then the adhesive layer 52 includes a plurality of third layers. A dicing tape 49 is attached to the back surface 36b of the semiconductor substrate 36 so as to embed the bump electrodes 28.

Next, in the step shown in FIG. 21, after the structure shown in FIG. 20 is turned upside down, the second adhesive layer 45 and the support substrate 42 are removed, so that the first adhesive layer 44 is exposed.
Specifically, for example, when the second adhesive layer 45 is formed of an adhesive whose adhesive strength is reduced by light, the second adhesive layer 45 is formed on the second adhesive layer 45 via the support substrate 42 (light transmissive substrate). When the adhesive force of the second adhesive layer 45 is reduced by irradiating light, the second adhesive layer 45 and the support substrate 42 are peeled off from the first adhesive layer 44.

  Thereby, a plurality of second semiconductor chips 13 on which the sacrificial adhesive layer 14 is formed are disposed on the dicing tape 49. At this stage, the second semiconductor chip 13 and the sacrificial adhesive layer 14 are not separated.

  As described in the process shown in FIG. 17, the second surface 44b of the first adhesive layer 44 (the second surface 14b of the sacrificial adhesive layer 14 to which a bonding tool 61 shown in FIG. It is a flat surface.

  As described above, the first semiconductor chip 13 has one surface 13a and a plurality of bumps 19, 28, 22, 23 arranged in the same layout as the first and third to fifth bump electrodes 19, 28, 22, 23. By forming the sacrificial adhesive layer 14 in which the second bump electrode 27 is embedded and the second surface 14b adsorbed by the bonding tool 61 is a flat surface, in the process shown in FIG. By adsorbing the second surface 14b of the sacrificial adhesive layer 14 and pressing the second semiconductor chip 13 against the third semiconductor chip 12 disposed below, the fourth bump electrode 22 and the third bump When thermocompression bonding with the electrode 28, it becomes possible to press the entire surface 13 a side of the second semiconductor chip 13 with sufficient pressure through the sacrificial adhesive layer 14.

As a result, the third bump electrode 28 can be pressed against the fourth bump electrode 22 with sufficient pressure, so that the fourth bump electrode 22 and the third bump electrode 28 can be satisfactorily bonded. .
Therefore, since the electrical connection reliability between the fourth bump electrode 22 and the third bump electrode 28 is improved, the yield of the chip stack 65 (see FIG. 4) can be improved.

  Next, in the process shown in FIG. 22, the first adhesive layer 44 and the third semiconductor 13 are separated by cutting the structure disposed on the dicing tape 49 shown in FIG. 21 along the dicing line B. Tidy up. Thereby, a plurality of third semiconductors 13 on which the sacrificial adhesive layer 14 is formed are arranged on the dicing tape 49.

  As described above, the first adhesion which is one of the constituent elements of the adhesion member 41 (a member necessary for thinning the semiconductor substrate 36) for adhering the surface 26a of the circuit element layer 26 and the support substrate 42. By using the layer 44 as a base material of the sacrificial adhesive layer 14, it is not necessary to separately prepare an adhesive layer as a base material of the first adhesive layer 44. Therefore, the sacrificial adhesive layer 14 can be formed on the third semiconductor 13 without increasing the manufacturing cost.

23, the dicing tape 49 is removed from the plurality of third semiconductors 13 on which the sacrificial adhesive layer 14 is formed.
As a result, a plurality of third semiconductors 13 on which the sacrificial adhesive layer 14 is formed are manufactured.

2, the first semiconductor chip 11 is placed on the stage 56 so that the upper surface 56a of the stage 56 of the bonding apparatus and the other surface 11b (flat surface) of the first semiconductor chip 11 are in contact with each other. After that, the first semiconductor chip 11 is sucked by a suction hole 57 provided on the stage 56 and connected to a vacuum device (not shown).
As described above, when the first semiconductor chip 11 is attracted by the stage 56, the other surface 11b of the first semiconductor chip 11 which is a flat surface is attracted, so that the first semiconductor chip 11 is in a good state. Can be adsorbed.

At this stage, the one surface 11a of the first semiconductor chip 11 on which the plurality of first bump electrodes 19 are formed is the upper surface side.
Although not shown, the stage 56 has a heater, and the first semiconductor chip 11 is heated by this heater so as to reach a predetermined temperature (for example, 100 ° C.).

Next, in the process shown in FIG. 3, the suction surface 61a of the bonding tool 61 is brought into contact with the one surface 12a side of the third semiconductor chip 12 (specifically, the plurality of fourth bump electrodes 22).
Thereafter, the one surface 12a side of the third semiconductor chip 12 is attracted to the suction surface 61a of the bonding tool 61 through the suction hole 62 connected to a vacuum device (not shown) and exposed from the suction surface 61a. Although not shown, the bonding tool 61 has a heater, and the third semiconductor chip 12 is heated by this heater so as to reach a predetermined temperature (for example, 300 ° C.).

Next, the third semiconductor chip 12 is disposed on the first semiconductor chip 11 by moving the bonding tool 61 so that the first bump electrode 19 and the fifth bump electrode 23 face each other.
Thereafter, the first bump electrode 19 and the fifth bump electrode 23 are thermocompression bonded by pressing the third semiconductor chip 12 against the first semiconductor chip 11 by the bonding tool 61. As a result, the third semiconductor chip 12 is flip-chip mounted on the first semiconductor chip 11.

As described above, the first, fourth, and fifth bump electrodes 19, 22, and 23 are arranged in the same layout.
Therefore, when the third semiconductor chip 12 is pressed by the bonding tool 61, the fifth bump electrode 23 can be pressed with sufficient pressure against the plurality of first bump electrodes 19. The first bump electrode 19 and the fifth bump electrode 23 can be bonded satisfactorily.

Next, in the step shown in FIG. 4, the second surface 14 b of the sacrificial adhesive layer 14 formed on the second semiconductor chip 13 is sucked to the suction surface 61 a of the bonding tool 61. Next, the second semiconductor in which the sacrificial adhesive layer 14 is formed on the third semiconductor chip 12 by moving the bonding tool 61 so that the fourth bump electrode 22 and the third bump electrode 28 face each other. The chip 13 is disposed.
At this time, the second semiconductor chip 13 is heated to a predetermined temperature (for example, 300 ° C.) by a heater (not shown) of the bonding tool 61.

  Thereafter, the second semiconductor chip 13 is pressed against the third semiconductor chip 12 by the bonding tool 61, and the fourth bump electrode 22 and the third bump electrode 28 are thermocompression-bonded. The second semiconductor chip 13 is flip-chip mounted on the semiconductor chip 12.

  As a result, a chip stacked body 65 is formed which includes the first to third semiconductor chips 11, 13, 12 that are stacked and mounted, and the first to third semiconductor chips 11, 13, 12 are electrically connected. Is done. At this stage, the sacrificial adhesive layer 14 is formed on the second semiconductor chip 13 constituting the chip stack 65.

  Next, in the step shown in FIG. 5, the chip stack 65 on which the sacrificial adhesive layer 14 is formed is taken out from the bonding apparatus 67 shown in FIG. 4.

Next, in the step shown in FIG. 6, the structure shown in FIG. 5 is formed on the coating sheet 72 so that the coating sheet 72 arranged on the stage 71 and the other surface 11b of the first semiconductor chip 11 come into contact with each other. Place.
Next, by supplying the underfill material 76 to one of the four side walls of the chip stacked body 65 via the dispenser 74, the first semiconductor chip 11 and the third semiconductor chip are caused by a capillary phenomenon. An underfill material 76 (for example, thermosetting resin) is caused to flow in the gap between the first semiconductor chip 12 and the third semiconductor chip 12 and the second semiconductor chip 13.

  Next, in the process shown in FIG. 7, the gap between the first semiconductor chip 11 and the third semiconductor chip 12 and the gap between the third semiconductor chip 12 and the second semiconductor chip 13 are made of the underfill material 76. At the filling stage, the supply of the underfill material 76 is stopped. Thereafter, the underfill material 76 is heated to a predetermined temperature to be completely cured.

  As a result, the gap between the first semiconductor chip 11 and the third semiconductor chip 12 and the gap between the third semiconductor chip 12 and the second semiconductor chip 13 are sealed and completely cured. A first sealing resin 78 made of 76 is formed.

  In this way, after forming the sacrificial adhesive layer 14 that covers the second bump electrode 27 that functions as the external connection terminal of the chip stack 65, the underfill material 76 is supplied to the side wall of the chip stack 65, thereby It is possible to prevent the underfill material 76 from adhering to the bump electrode 27. Thereby, when the chip stack 65 is mounted on the wiring board 92 in the step shown in FIG. 12 to be described later, the electrical connection reliability between the chip stack 65 and the wiring board 92 can be improved.

  Next, in the step shown in FIG. 8, the chip laminated body 65 on which the first sealing resin 78 is formed is picked up from the coating sheet 72 shown in FIG.

  Next, in the process shown in FIG. 9, the structure shown in FIG. 8 is arranged on the stage 81 so that the upper surface 81a of the stage 81 having the suction holes 82 and the other surface 11b of the first semiconductor chip 11 come into contact with each other. To do. Thereafter, the adhesive tape 85 is attached to the second surface 14 b of the sacrificial adhesive layer 14. Next, the outer peripheral surface 86 a of the roller 86 is brought into contact with the adhesive tape 85.

Next, in the step shown in FIG. 10, the sacrificial adhesive layer 14 is peeled off from the second semiconductor chip 13 (chip stack 65) by moving the roller 86 in the C direction.
As a result, the one surface 13a of the second semiconductor chip 13 and the plurality of second bump electrodes 27 are exposed, and a structure including the first sealing resin 78 and the chip stack 65 is formed.

  As described above, before the underfill material 76 is introduced into the gap between the first semiconductor chip 11 and the third semiconductor chip 12 and the gap between the third semiconductor chip 12 and the second semiconductor chip 13, The sacrificial adhesive layer 14 covering the one surface 13a of the second semiconductor chip 13 and the plurality of second bump electrodes 27 is formed on the stacked body 65, and sacrificed after the first sealing resin 78 made of the underfill material 76 is formed. By removing the adhesive layer 14, one surface 13a of the second semiconductor chip 13 and a plurality of second bump electrodes 27 (bumps electrically connected to connection pads 96 of a wiring board 92 shown in FIG. It is possible to prevent the underfill material 76 (first sealing resin 78) from adhering to the electrode).

  As a result, when the chip stack 65 is mounted on the connection pad 96 of the wiring substrate 92 via the wire bump 103 in the process shown in FIG. 12 to be described later, the electrical connection between the second bump electrode 27 and the connection pad 96 is achieved. Connection reliability can be improved.

  Further, even when the underfill material 76 rides on the sacrificial adhesive layer 14, it can be easily removed, and in this case as well, the electrical connection reliability between the second bump electrode 27 and the connection pad 96 is improved. Can be made.

  Furthermore, by storing the chip stack 65 with the sacrificial adhesive layer 14 still formed, it is possible to prevent foreign matter from adhering to the second bump electrode 27. Therefore, it is preferable to remove the sacrificial adhesive layer 14 immediately before mounting the chip stack 65 on the wiring board 92.

Next, in a step shown in FIG. 11, a wiring mother board 91 in which a plurality of wiring boards 92 are connected is formed by a known method.
Here, the configuration of the wiring mother board 91 and the wiring board 92 will be described with reference to FIG.
The wiring mother board 91 includes an insulating base 94, connection pads 96, lands 97, a wiring pattern 98, a first solder resist 99, and a second solder resist 101.

  The insulating base 94 has a plurality of wiring board forming areas E and dicing lines D that partition the plurality of wiring board forming areas E. The insulating base 94 is separated into pieces in the process shown in FIG. 15 to be described later, thereby forming a plurality of insulating bases 111 (one of the components of the wiring board 92).

  The connection pad 96 is provided on one surface 94a of the insulating base 94 corresponding to the wiring board formation region E. The connection pad 96 has a bump forming surface 96a on which the wire bump 103 is formed. The land 97 is provided on the other surface 94 b of the insulating base 94 corresponding to the wiring board formation region E. The land 97 has a terminal arrangement surface 97a on which an external connection terminal 109 shown in FIG.

The wiring pattern 98 is provided so as to penetrate the insulating base 94. The wiring pattern 98 has one end connected to the connection pad 96 and the other end connected to the land 97. Thereby, the wiring pattern 98 electrically connects the connection pad 96 and the land 97.
The first solder resist 99 is provided on one surface 94a of the insulating base 94 so as to expose the bump forming surface 96a. The second solder resist 101 is provided on the other surface 94b of the insulating base 94 so as to expose the terminal arrangement surface 97a.

  The wiring substrate 92 is provided in the wiring substrate formation region E, and the insulating base 111, the connection pads 96, the lands 97, the wiring pattern 98, and the first and second provided in the wiring substrate formation region E. Solder resists 99 and 101.

  In the step shown in FIG. 11, after forming the wiring mother board 91, the wire bumps 103 are formed on the bump forming surfaces 96 a of the plurality of connection pads 96 formed on the wiring mother board 91 using a wire bonding apparatus (not shown). Form.

  Specifically, the wire bump 103 (convex bump) is formed, for example, by melting the tip of a wire made of gold (Au) or copper (Cu) to form a ball at the tip, and then forming the ball. The wire is ultrasonically bonded to the bump forming surface 96a of the connection pad 96, and then the rear end of the wire is cut off.

Next, an insulating adhesive member 105 that covers the plurality of connection pads 96 and the wire bumps 103 formed in the wiring board formation region E is formed. The insulating adhesive member 105 is formed on all the wiring board formation regions E.
Specifically, for example, the insulating adhesive member 105 is formed by supplying NCP (Non Conductive Paste) which is a base material of the insulating adhesive member 105 from a dispenser (not shown).

  Next, in the step shown in FIG. 12, after the chip laminated body 65 shown in FIG. 10 is turned upside down, the chip laminated body 65 is used by the bonding tool 61 (not shown in FIG. 12) shown in FIG. The other surface 11b of the first semiconductor chip 11 constituting the chip is adsorbed, and the chip stack 65 is heated to a predetermined temperature (for example, 300 ° C.).

  Next, the bonding tool 61 that has attracted and heated the chip stack 65 is moved so that the second bump electrode 27 faces the wire bump 103. Next, the second bump electrode 27 and the wire bump 103 are thermocompression-bonded by pressing the chip stack 65 against the wiring substrate 92 with the bonding tool 61.

  As a result, the second bump electrode 27 and the connection pad 96 are electrically connected via the wire bump 103, and the chip laminated body 65 on which the first sealing resin 78 (underfill material 76) is formed is wired. The substrate 92 is flip-chip mounted.

In addition, when the chip stack 65 is pressed against the wiring board 92, the insulating adhesive member 105 flows between the chip stack 65 and the wiring board 92 in the lateral direction. Thereby, the insulating adhesive member 105 seals between the chip stack 65 and the wiring board 92.
Mounting of the chip stack 65 on which the first sealing resin 78 is formed is performed on all the wiring boards 92.

  Next, in the step shown in FIG. 13, the plurality of chip stacks 65 and the first sealing resin 78 mounted on the wiring motherboard 91 are collectively sealed, and the second upper surface 107 a is a flat surface. A sealing resin 107 is formed. As the second sealing resin 107, for example, a mold resin can be used.

  In this case, the second sealing resin 107 is formed by the following method. First, the structure shown in FIG. 12 is accommodated in a cavity provided in a molding die (not shown) composed of an upper die and a lower die. Thereafter, a thermosetting resin (base material of the second sealing resin 107) such as an epoxy resin that is heated and melted is injected into the cavity from a gate portion (not shown) provided in the molding die.

  As a result, the plurality of chip stacks 65 and the first sealing resin 78 mounted on the wiring motherboard 91 are covered with the thermosetting resin. Thereafter, the thermosetting resin is cured at a predetermined temperature (for example, 180 ° C.) to form the second sealing resin 107 made of the completely cured thermosetting resin.

  At this time, since the first sealing resin 78 is filled in the gaps between the first to third semiconductor chips 11, 13, and 12 constituting the chip stack 65 in advance, the second sealing resin In the step of forming 107, the generation of voids between the first to third semiconductor chips 11, 13, 12 can be suppressed.

Next, in the process shown in FIG. 14, the external connection terminal 109 is mounted on the terminal arrangement surface 97 a of the land 97 formed on the wiring board 92. For example, a solder ball can be used as the external connection terminal 109.
In this case, the external connection terminal 109 is mounted on the terminal arrangement surface 97a of the land 97 by, for example, a mount tool (not shown) provided with a suction hole capable of sucking and holding a plurality of solder balls.

  At this time, the external connection terminals 109 are mounted on the terminal arrangement surfaces 97 a of the lands 97 provided on all the wiring boards 92. Thereby, a structure in which the semiconductor device 10 is formed in the plurality of wiring board formation regions E is manufactured. At this stage, the plurality of semiconductor devices 10 are connected and are not separated.

  Next, in the process shown in FIG. 15, the structure shown in FIG. 14 is cut along the dicing line D shown in FIG. 14 by a dicing blade (not shown), thereby dividing the plurality of semiconductor devices 10 into individual pieces. To do. Thereby, a plurality of semiconductor devices 10 are manufactured.

  According to the manufacturing method of the semiconductor device of the present embodiment, the first and third to fifth bump electrodes 19, 28, 22, 23 arranged on the one surface 13 a of the second semiconductor chip 13 with the same layout. By forming the sacrificial adhesive layer 14 in which a plurality of second bump electrodes 27 arranged in a layout different from that of the second bump electrode 27 are embedded and the second surface 14b to which the bonding tool 61 adsorbs is formed as a flat surface, a bonding tool is formed. The second surface 14b of the sacrificial adhesive layer 14 is adsorbed by 61, and the second semiconductor chip 13 is pressed against the third semiconductor chip 12 disposed below, so that the fourth bump electrode 22 and the third bump When the bump electrode 28 is thermocompression bonded, the entire surface 13a side of the second semiconductor chip 13 can be pressed with sufficient pressure via the sacrificial adhesive layer 14.

As a result, the third bump electrode 28 can be pressed against the fourth bump electrode 22 with sufficient pressure, so that the fourth bump electrode 22 and the third bump electrode 28 can be satisfactorily bonded. .
Therefore, since the electrical connection reliability between the fourth bump electrode 22 and the third bump electrode 28 is improved, the yield of the chip stacked body 65 can be improved.

  Before introducing the underfill material 76 into the gap between the first semiconductor chip 11 and the third semiconductor chip 12 and the gap between the third semiconductor chip 12 and the second semiconductor chip 13, the chip stack The sacrificial adhesive layer 14 covering the one surface 13a of the second semiconductor chip 13 and the plurality of second bump electrodes 27 is formed on 65, and the sacrificial adhesive layer is formed after the first sealing resin 78 made of the underfill material 76 is formed. By removing 14, it is possible to suppress the underfill material 76 (first sealing resin 78) from adhering to the one surface 13 a of the second semiconductor chip 13 and the plurality of second bump electrodes 27.

  This improves the reliability of electrical connection between the second bump electrode 27 and the connection pad 96 when the chip stack 65 is mounted on the connection pad 96 of the wiring board 92 via the wire bump 103. it can.

  Further, even when the underfill material 76 rides on the sacrificial adhesive layer 14, it can be easily removed, and in this case as well, the electrical connection reliability between the second bump electrode 27 and the connection pad 96 is improved. Can be made.

  24 to 26 are cross-sectional views showing the manufacturing steps of the semiconductor device according to the modification of the embodiment of the present invention. 24-26, the same code | symbol is attached | subjected to the same structure part as the structure shown in FIGS. 3-5.

A method for manufacturing the semiconductor device 10 according to a modification of the present embodiment will be described mainly with reference to FIGS.
First, the structure shown in FIG. 2 is formed by performing the same process as the process shown in FIG. 1 described above.
24, the sacrificial adhesive layer 14 is placed on the stage 56 so that the upper surface 56a of the stage 56 of the bonding apparatus 67 and the second surface 14b (flat surface) of the sacrificial adhesive layer 14 are in contact with each other. The formed second semiconductor chip 13 is disposed.

Next, the second semiconductor chip 13 is adsorbed via the sacrificial adhesive layer 14 through an adsorption hole 57 provided on the stage 56 and connected to a vacuum device (not shown).
Thus, by adsorbing the second surface 14b, which is a flat surface of the sacrificial adhesive layer 14, the second semiconductor chip 13 on which the sacrificial adhesive layer 14 is formed can be adsorbed in a good state.

Further, the second semiconductor chip 13 is heated to a predetermined temperature (for example, 100 ° C.) by a heater (not shown) provided on the stage 56.
At this stage, the other surface 13b of the second semiconductor chip 13 on which the plurality of third bump electrodes 28 are formed is the upper surface side.

Next, the suction surface 61a of the bonding tool 61 is brought into contact with the other surface 12b side of the third semiconductor chip 12 (specifically, the plurality of fifth bump electrodes 23), and then the suction surface 61a of the bonding tool 61 is contacted. Then, the other surface 12b side of the third semiconductor chip 12 is adsorbed.
Thereafter, the third semiconductor chip 12 is heated to a predetermined temperature (for example, 300 ° C.) by a heater (not shown) of the bonding tool 61.

Next, by moving the bonding tool 61, the second bump electrode 22 and the third bump electrode 28 (bump electrodes arranged in the same layout as the fourth bump electrode 22) are opposed to each other. The third semiconductor chip 12 is arranged on the semiconductor chip 13.
Thereafter, the fourth bump electrode 22 and the third bump electrode 28 are thermocompression bonded by pressing the third semiconductor chip 12 against the second semiconductor chip 13 by the bonding tool 61. As a result, the third semiconductor chip 12 is flip-chip mounted on the second semiconductor chip 13.

  As described above, the fourth bump electrode 22, the fifth bump electrode 23, and the third bump electrode 28 are arranged in the same layout. For this reason, when the third semiconductor chip 12 is pressed by the bonding tool 61, the fourth bump electrode 22 can be pressed against the plurality of third bump electrodes 28 with sufficient pressure. The bonding failure between the fourth bump electrode 22 and the third bump electrode 28 can be reduced.

Next, in the step shown in FIG. 25, the other surface 11 b of the first semiconductor chip 11 that is a flat surface is sucked by the suction surface 61 a of the bonding tool 61. Next, the first semiconductor chip 11 is arranged on the third semiconductor chip 12 by moving the bonding tool 61 so that the fifth bump electrode 23 and the first bump electrode 19 face each other.
At this time, the first semiconductor chip 11 is heated to a predetermined temperature (for example, 300 ° C.) by a heater (not shown) of the bonding tool 61.

Thereafter, by pressing the first semiconductor chip 11 against the third semiconductor chip 12 by the bonding tool 61, the fifth bump electrode 23 and the first bump electrode 19 are thermocompression bonded. The first semiconductor chip 11 is flip-chip mounted on the third semiconductor chip 12.
As a result, a chip stack 65 composed of the first to third semiconductor chips 11, 13, 12 mounted in a stacked manner is formed.

In this way, the first and fifth bump electrodes 19 and 23 arranged in the same layout are arranged to face each other, and the bonding tool 61 presses the other surface 11b of the first semiconductor chip 11 which is a flat surface. As a result, the plurality of first bump electrodes 19 can be pressed against the fifth bump electrode 23 with sufficient pressure, so that the gap between the first bump electrode 19 and the fifth bump electrode 23 can be reduced. Bonding defects can be reduced.
At this stage, the sacrificial adhesive layer 14 is formed on the second semiconductor chip 13 constituting the chip stack 65.

Next, in the step shown in FIG. 26, the chip laminated body 65 on which the sacrificial adhesive layer 14 is formed is taken out from the bonding apparatus 67 shown in FIG. 25 and the chip laminated body 65 is turned upside down.
Thereafter, the processes shown in FIGS. 6 to 15 described above are performed, whereby a plurality of semiconductor devices 10 shown in FIG. 15 are manufactured.

  In the method for manufacturing the semiconductor device 10 according to the modification of the present embodiment, the first to third semiconductors are arranged in the reverse order to the method for forming the chip stacked body 65 shown in FIGS. The chips 11, 13, and 12 are stacked and mounted. The manufacturing method of the semiconductor device 10 according to the modification of the present embodiment to which the method for forming the chip stacked body 65 is applied is the semiconductor of the present embodiment. The same effect as the method for manufacturing the device 10 (see FIGS. 1 to 15) can be obtained.

  Specifically, the third semiconductor chip covers a plurality of second bump electrodes 27 arranged in a different layout from the one surface 13a of the second semiconductor chip 13 and the third bump electrode 28, and the second semiconductor chip 13 is covered with the second semiconductor chip 13. The sacrificial adhesive layer 14 having a flat surface 14b is formed, and then the upper surface 56a of the stage 56 of the bonding apparatus 67 and the second surface 14b of the sacrificial adhesive layer 14 are in contact with each other. The second semiconductor chip 13 having the sacrificial adhesive layer 14 formed thereon is placed, and then the third semiconductor chip 12 adsorbed by the bonding tool 61 is pressed against the second semiconductor chip 13. When the third semiconductor chip 12 is pressed by thermocompression bonding the fourth bump electrode 22 and the third bump electrode 28, the sacrificial adhesive layer 14 suppresses the deformation of the second semiconductor chip 13. The ability.

  As a result, a plurality of fourth bump electrodes 22 can be pressed against the third bump electrode 28 with sufficient pressure, so that the fourth bump electrode 22 and the third bump electrode 28 can be satisfactorily connected. Can be joined.

  In addition, after the chip stack 65 is formed, an underfill material is filled in the gap between the first semiconductor chip 11 and the third semiconductor chip 12 and the gap between the third semiconductor chip 12 and the second semiconductor chip 13. The sacrificial adhesive layer 14 that covers the one surface 13a of the second semiconductor chip 13 and the plurality of fourth bump electrodes is formed before the sacrificial adhesive layer 14 is formed. The underfill material 76 does not adhere to the one surface 13 a of the semiconductor chip 13 and the plurality of second bump electrodes 27.

  Thereby, after the sacrificial adhesive layer 14 is removed, when the chip laminated body 65 on which the underfill material 76 is formed is mounted on the wiring substrate 92, the second bump electrode 27 (the chip laminated body 65 of the chip laminated body 65) is mounted. The reliability of electrical connection between the bump electrodes functioning as external connection terminals) and the connection pads 96 of the wiring board 92 can be improved.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and within the scope of the present invention described in the claims, Various modifications and changes are possible.

  FIG. 27 is a cross-sectional view showing a modification of the chip stack. FIG. 27 illustrates a chip stack 115 in which the first sealing resin 78 (fully cured underfill material 76) and the sacrificial adhesive layer 14 are formed. In FIG. 27, the same components as those of the structure shown in FIG.

For example, as shown in FIG. 27, three or more (three as an example in FIG. 27) third semiconductor chips 12 are stacked and mounted between the first semiconductor chip 11 and the second semiconductor chip 13. Then, the chip stacked body 115 constituted by the above steps is formed, and then the semiconductor device may be manufactured by performing the processes shown in FIGS. 9 to 15 described above using the chip stacked body 115. .
In this case, the same effect as that of the method for manufacturing the semiconductor device 10 according to the embodiment of the present invention can be obtained.

  In the present embodiment, the case where the chip stacks 65 and 115 are configured by the first to third semiconductor chips 11, 13, and 12 has been described as an example. However, the present invention is not limited to the first semiconductor chip. 11 and the third semiconductor chip 12 can be applied to a chip laminated body.

  Furthermore, in the present embodiment, the case where the second bump electrode 27 is disposed at a position facing the third and fourth bump electrodes 28 and 22 constituting the chip stacks 65 and 115 has been described as an example. However, by connecting the rewiring and the second bump electrode 27, the position of the second bump electrode 27 may be disposed at a position that does not face the third and fourth bump electrodes 28 and 22.

In the present embodiment, a memory semiconductor chip is used as an example of the first and third semiconductor chips 11 and 12, and an interface semiconductor chip is used as an example of the second semiconductor chip 13. , 115 has been described as an example, but the present invention can be applied to the case where semiconductor chips having different bump electrode layouts (arrangement positions) are stacked to form a chip stack.
In other words, the present invention is also applicable to the case where the chip stacked bodies 65 and 115 are formed by stacking various other semiconductor chips (for example, a logic semiconductor chip or a memory semiconductor chip).

In the present embodiment, the case where the sacrificial adhesive layer 14 is formed by separating the first adhesive layer 44 constituting the dicing tape 49 is described as an example. A material having a heat resistance of about 300 to 350 ° C. and an elastic modulus of 8 MPa or more (for example, a TMAT material of Nissan Chemical Industries, etc.) so as to cover the one surface 13a and the plurality of second bump electrodes 27 The sacrificial adhesive layer 14 may be formed by applying and curing the film by spin coating or screen printing.
Also in this case, the same effect as the method for manufacturing the semiconductor device 10 of the present embodiment can be obtained.

  The present invention is applicable to a method for manufacturing a semiconductor device.

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor device, 11 ... 1st semiconductor chip, 11a, 12a, 13a, 51a, 94a ... One side, 11b, 12b, 13b, 94b ... Other side, 13 ... 2nd semiconductor chip, 13 ... 2nd semiconductor Chip, 14 ... Sacrificial adhesive layer, 14a, 44a ... First surface, 14b, 44b ... Second surface, 16, 36 ... Semiconductor substrate, 16a, 17a, 26a, 36a ... Front surface, 16b, 36b ... Back surface, 17 , 26 ... Circuit element layer, 19 ... First bump electrode, 22 ... Fourth bump electrode, 23 ... Fifth bump electrode, 24, 29 ... Through electrode, 27 ... Second bump electrode, 28 ... Third Bump electrodes, 41 ... adhesive member, 42 ... support substrate, 42a, 56a, 81a, 107a ... upper surface, 44 ... first adhesive layer, 45 ... second adhesive layer, 48 ... third semiconductor chip mother substrate, 49 ... Dicing tape DESCRIPTION OF SYMBOLS 51 ... Dicing tape main body, 52 ... Adhesive layer, 56, 71, 81 ... Stage, 57, 62 ... Suction hole, 61 ... Bonding tool, 61a ... Suction surface, 65, 115 ... Chip laminated body, 67 ... Bonding apparatus, 72 Application sheet, 74 Dispenser, 76 Underfill material, 78 First sealing resin, 85 Adhesive tape, 86 Roller, 86a Outer peripheral surface, 91 Wiring mother board, 92 Wiring board, 94 111 ... Insulating base material, 96 ... Connection pad, 96a ... Bump formation surface, 97 ... Land, 97a ... Terminal arrangement surface, 98 ... Wiring pattern, 99 ... First solder resist, 101 ... Second solder resist, 103 DESCRIPTION OF SYMBOLS ... Wire bump, 105 ... Insulating adhesive member, 107 ... 2nd sealing resin, 109 ... External connection terminal, A ... Chip formation area, B, D ... Dicing Inn, C ... direction, E ... wiring board formation regions, M ... thickness

Claims (10)

A first semiconductor chip having a first bump electrode disposed on one surface and a flat other surface, a second bump electrode disposed on one surface, and a layout different from the second bump electrode on the other surface. Preparing a second semiconductor chip having a third bump electrode disposed in
One surface of the second bump electrode and the second semiconductor chip such that the second surface located on the opposite side of the first surface contacting the one surface of the second semiconductor chip is a flat surface. Forming a sacrificial adhesive layer covering
Forming a chip stack including the first and second semiconductor chips stacked and mounted by electrically connecting the first bump electrode and the third bump electrode;
A step of filling an underfill material between the first semiconductor chip and the second semiconductor chip after forming the chip stack;
Removing the sacrificial adhesive layer after filling the underfill material;
A method for manufacturing a semiconductor device, comprising: In the step of forming the chip stack, the step of disposing the first semiconductor chip on the stage such that the upper surface of the stage and the other surface of the first semiconductor chip are in contact with each other;
Electrically connecting the first bump electrode and the third bump electrode with a bonding tool that adsorbs one surface side of the second semiconductor chip;
The method of manufacturing a semiconductor device according to claim 1, comprising: In the step of forming the chip stacked body, the step of disposing the second semiconductor chip on the stage so that the upper surface of the stage and the second surface of the sacrificial adhesive layer are in contact with each other;
Electrically connecting the first bump electrode and the third bump electrode with a bonding tool that adsorbs the other surface side of the first semiconductor chip;
The method of manufacturing a semiconductor device according to claim 1, comprising:   4. The method of manufacturing a semiconductor device according to claim 1, wherein the third bump electrode is formed in the same layout as the first bump electrode. 5.   5. The step of removing the sacrificial adhesive layer, wherein an adhesive tape is attached to the second surface of the sacrificial adhesive layer, and then the sacrificial adhesive layer is peeled off together with the adhesive tape. The manufacturing method of the semiconductor device of any one of these. Preparing a third semiconductor chip having a fourth bump electrode disposed on one surface and a fifth bump electrode disposed on the other surface;
In the step of forming the chip stacked body, the third semiconductor chip is disposed between the first semiconductor chip and the second semiconductor chip, and the first bump electrode and the fifth bump are disposed. Connecting an electrode, connecting the third bump electrode and the fourth bump electrode,
6. The semiconductor according to claim 1, wherein in the step of filling the underfill material, the underfill material is filled in a gap between the first to third semiconductor chips. Device manufacturing method. In the step of preparing the third semiconductor chip, a plurality of the third semiconductor chips are prepared,
The step of forming the chip stacked body includes stacking and mounting a plurality of the third semiconductor chips between the first semiconductor chip and the second semiconductor chip. 6. A method of manufacturing a semiconductor device according to claim 1. The fourth bump electrode is formed in the same layout as the third bump electrode;
The method for manufacturing a semiconductor device according to claim 1, wherein the fifth bump electrode is formed in the same layout as the first bump electrode.   In the step of forming the sacrificial adhesive layer, a dicing tape having first and second adhesive layers is provided on one surface of a second semiconductor chip mother substrate to which a plurality of the second semiconductor chips are connected. 1 adhesive layer is embedded so as to embed a plurality of the second bump electrodes, and then the second semiconductor chip and the first adhesive layer are separated into a plurality of pieces. 9. The method of manufacturing a semiconductor device according to claim 1, wherein the sacrificial adhesive layer made of the first adhesive layer is collectively formed on the second semiconductor chip. Preparing a wiring board having connection pads arranged on one side and lands arranged on the other side;
After the sacrificial adhesive layer is removed, by electrically connecting the connection pad and the second bump electrode, mounting the chip stack formed with the underfill material on the wiring board;
10. The method of manufacturing a semiconductor device according to claim 1, comprising:

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