JP2015220291A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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JP2015220291A
JP2015220291A JP2014101638A JP2014101638A JP2015220291A JP 2015220291 A JP2015220291 A JP 2015220291A JP 2014101638 A JP2014101638 A JP 2014101638A JP 2014101638 A JP2014101638 A JP 2014101638A JP 2015220291 A JP2015220291 A JP 2015220291A
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conductive
mounting substrate
conductive bump
bridge chip
curable resin
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赳史 児玉
Takefumi Kodama
赳史 児玉
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Socionext Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

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  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing a contact failure in using a bridge chip, and a method of manufacturing the same.SOLUTION: An ultraviolet curable resin 111 is provided on a mounting substrate 101. A bridge chip 121, which has conductive bumps 123 on a first main surface and wiring 122 electrically connecting the conductive bumps 123, is pressed against the ultraviolet curable resin 111 while a second main surface opposite to the first main surface faces the mounting substrate 101 side. The ultraviolet curable resin 111 is irradiated with ultraviolet rays to fix the bridge chip 121 to the mounting substrate 101. Semiconductor chips 141 and 151 connected to the conductive bumps 123 are mounted on the mounting substrate 101.

Description

本発明は、半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof.

シリコンインタポーザを用いて複数の半導体チップを互いに接続し、これらを１個の実装基板上に搭載する技術がある。しかし、シリコンインタポーザの形成には、コスト、時間がかかる。シリコンインタポーザを用いることによるデメリットを解消すべく、熱硬化樹脂を用いて実装基板上にブリッジチップを固定し、このブリッジチップを介して複数の半導体チップを互いに接続しようとする技術が提案されている。   There is a technique in which a plurality of semiconductor chips are connected to each other using a silicon interposer and are mounted on a single mounting substrate. However, formation of a silicon interposer requires cost and time. In order to eliminate the disadvantages of using a silicon interposer, a technique has been proposed in which a bridge chip is fixed on a mounting substrate using a thermosetting resin, and a plurality of semiconductor chips are connected to each other via the bridge chip. .

しかしながら、従来のブリッジチップを用いた半導体装置では、半導体チップと実装基板との間にコンタクト不良が生じたり、半導体チップとブリッジチップとの間にコンタクト不良が生じたりしやすい。   However, in a conventional semiconductor device using a bridge chip, a contact failure is likely to occur between the semiconductor chip and the mounting substrate, or a contact failure is likely to occur between the semiconductor chip and the bridge chip.

特許第４５８１７６８号公報Japanese Patent No. 4581768 特開２００１−２７４３１７号公報JP 2001-274317 A

本発明の目的は、ブリッジチップを用いる際のコンタクト不良を抑制することができる半導体装置及びその製造方法を提供することにある。   An object of the present invention is to provide a semiconductor device capable of suppressing contact failure when using a bridge chip and a manufacturing method thereof.

半導体装置の製造方法の一態様では、実装基板上に紫外線硬化樹脂を設け、前記紫外線硬化樹脂に、第１の主面上の第１の導電バンプ、第２の導電バンプ並びに前記第１の導電バンプ及び前記第２の導電バンプを電気的に接続する配線を有するブリッジチップを、前記第１の主面とは反対側の第２の主面を前記実装基板側に向けて押し付け、前記紫外線硬化樹脂に紫外線を照射して前記ブリッジチップを前記実装基板に固定し、前記第１の導電バンプに接続される第１の半導体チップ及び前記第２の導電バンプに接続される第２の半導体チップを前記実装基板上に搭載する。   In one aspect of the method for manufacturing a semiconductor device, an ultraviolet curable resin is provided on a mounting substrate, and the first conductive bump, the second conductive bump, and the first conductive on the first main surface are provided on the ultraviolet curable resin. A bridge chip having a wiring for electrically connecting the bump and the second conductive bump is pressed against the mounting substrate side with the second main surface opposite to the first main surface, and the ultraviolet curing is performed. A first semiconductor chip connected to the first conductive bump and a second semiconductor chip connected to the second conductive bump are fixed by irradiating the resin with ultraviolet rays to fix the bridge chip to the mounting substrate. Mounted on the mounting substrate.

半導体装置の一態様には、実装基板と、第１の主面上の第１の導電バンプ、第２の導電バンプ並びに前記第１の導電バンプ及び前記第２の導電バンプを電気的に接続する配線を有し、前記第１の主面とは反対側の第２の主面を前記実装基板側に向けて、紫外線硬化樹脂を用いて前記実装基板に固定されたブリッジチップと、前記実装基板上に搭載され、前記第１の導電バンプに接続された第１の半導体チップ及び前記第２の導電バンプに接続される第２の半導体チップと、が含まれている。   In one embodiment of the semiconductor device, the mounting substrate is electrically connected to the first conductive bump, the second conductive bump, the first conductive bump, and the second conductive bump on the first main surface. A bridge chip having wiring and fixed to the mounting substrate using an ultraviolet curable resin with a second main surface opposite to the first main surface facing the mounting substrate side; and the mounting substrate A first semiconductor chip mounted on the first conductive bump and connected to the first conductive bump; and a second semiconductor chip connected to the second conductive bump.

上記の半導体装置の製造方法等によれば、ブリッジチップの実装基板への固定に紫外線硬化樹脂が用いられているため、熱硬化樹脂を用いた場合に生じるようなコンタクト不良を抑制することができる。   According to the manufacturing method of the semiconductor device described above, since the ultraviolet curable resin is used for fixing the bridge chip to the mounting substrate, it is possible to suppress the contact failure that occurs when the thermosetting resin is used. .

参考例を示す断面図である。It is sectional drawing which shows a reference example. 第１の実施形態に係る半導体装置を示す断面図である。1 is a cross-sectional view showing a semiconductor device according to a first embodiment. 第１の実施形態に係る半導体装置の製造方法を工程順に示す断面図である。FIG. 6 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment in the order of steps. 図３Ａに引き続き、半導体装置の製造方法を工程順に示す断面図である。FIG. 3B is a cross-sectional view illustrating the manufacturing method of the semiconductor device in order of processes following FIG. 3A. 第２の実施形態に係る半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on 2nd Embodiment. 第２の実施形態に係る半導体装置の製造方法を工程順に示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment to process order. 図５Ａに引き続き、半導体装置の製造方法を工程順に示す断面図である。FIG. 5B is a cross-sectional view illustrating the manufacturing method of the semiconductor device in order of processes following FIG. 5A.

本願発明者は、従来の製造方法においてコンタクト不良が生じる原因について検討を行った。この結果、熱硬化樹脂を用いてブリッジチップを実装基板に固定する際に、実装基板に反りが生じたり、ブリッジチップに位置ずれが生じたりしていることが判明した。また、ブリッジチップのはんだバンプが実装基板上のはんだボールよりも著しく小さいため、これらの高さを揃えることが困難であることも判明した。そして、これら反りの発生等に付随してコンタクト不良が生じていることも判明した。   The inventor of the present application examined the cause of contact failure in the conventional manufacturing method. As a result, it was found that when the bridge chip is fixed to the mounting substrate using the thermosetting resin, the mounting substrate is warped or the bridge chip is displaced. It has also been found that since the solder bumps of the bridge chip are significantly smaller than the solder balls on the mounting substrate, it is difficult to align these heights. It has also been found that contact failure occurs accompanying the occurrence of these warpages.

ここで、熱硬化樹脂を用いる参考例について説明する。図１は熱硬化樹脂を用いる参考例を示す断面図である。この参考例では、図１（ａ）に示すように、複数の導電パッド５０２を備えた実装基板５０１を準備し、導電パッド５０２上にはんだボール５０３を設ける。また、複数のはんだバンプ５２３を備えたブリッジチップ５２１を準備する。そして、実装基板５０１の所定の位置に熱硬化樹脂５１１を塗布し、その上にブリッジチップ５２１を載置する。次いで、加熱により熱硬化樹脂５１１を硬化させる。この加熱の結果、図１（ｂ）に示すように、実装基板５０１に反りが生じてしまう。また、熱硬化樹脂５１１は、熱硬化が完了するまでの間は、流動性を備えているため、熱硬化の完了までの間にブリッジチップ５２１の位置がずれることもある。熱硬化の完了後には、複数の端子５４２及び複数の端子５４３を備えた半導体チップ５４１を、端子５４２がはんだバンプ５２３に接触し、端子５４３がはんだボール５０３に接触するように実装基板５０１に搭載する。しかしながら、上記のように、実装基板５０１に反りが生じたり、ブリッジチップ５２１に位置ずれが生じたりしているため、図１（ｃ）に示すように、一部の端子５４２がはんだバンプ５２３に接触できず、一部の端子５４３がはんだボール５０３に接触できないことがある。また、図１（ａ）に示す例では、はんだバンプ５２３の頂点の高さがはんだボール５０３の頂点の高さと一致させているが、従来の技術で高さを揃えることは容易でなく、高さのずれに付随するコンタクト不良も生じ得る。   Here, a reference example using a thermosetting resin will be described. FIG. 1 is a cross-sectional view showing a reference example using a thermosetting resin. In this reference example, as shown in FIG. 1A, a mounting substrate 501 having a plurality of conductive pads 502 is prepared, and solder balls 503 are provided on the conductive pads 502. Further, a bridge chip 521 provided with a plurality of solder bumps 523 is prepared. And the thermosetting resin 511 is apply | coated to the predetermined position of the mounting substrate 501, The bridge chip | tip 521 is mounted on it. Next, the thermosetting resin 511 is cured by heating. As a result of this heating, the mounting substrate 501 is warped as shown in FIG. Further, since the thermosetting resin 511 has fluidity until the thermosetting is completed, the position of the bridge chip 521 may be shifted until the thermosetting is completed. After completion of thermosetting, the semiconductor chip 541 including the plurality of terminals 542 and the plurality of terminals 543 is mounted on the mounting substrate 501 so that the terminals 542 are in contact with the solder bumps 523 and the terminals 543 are in contact with the solder balls 503. To do. However, as described above, since the mounting substrate 501 is warped or the bridge chip 521 is displaced, some of the terminals 542 are formed on the solder bumps 523 as shown in FIG. In some cases, some terminals 543 cannot contact the solder balls 503. Further, in the example shown in FIG. 1A, the height of the top of the solder bump 523 is matched with the height of the top of the solder ball 503. Contact failures associated with the gap can also occur.

本願発明者は、これらの知見に基づいて以下に示す諸態様に相当した。以下、実施形態について添付の図面を参照しながら具体的に説明する。   The inventors of the present application corresponded to various aspects shown below based on these findings. Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

（第１の実施形態）
先ず、第１の実施形態について説明する。図２は、第１の実施形態に係る半導体装置を示す断面図である。 (First embodiment)
First, the first embodiment will be described. FIG. 2 is a cross-sectional view showing the semiconductor device according to the first embodiment.

第１の実施形態に係る半導体装置１００では、実装基板１０１上に複数の導電パッド１０２及びソルダレジスト１０４が設けられている。ソルダレジスト１０４に各導電パッド１０２の一部を露出する開口部が設けられており、この開口部内に導電ボール１０３が設けられている。紫外線硬化樹脂（ＵＶ硬化樹脂）１１１によりブリッジチップ１２１が実装基板１０１に固定されている。ブリッジチップ１２１に、実装基板１０１側の第２の主面とは反対側の第１の主面上の複数の導電バンプ１２３、及び、導電バンプ１２３を電気的に接続する配線１２２が含まれている。例えば、導電パッド１０２はＣｕパッドであり、導電ボール１０３はＳｎ−Ａｇ−Ｃｕ系のはんだボール又はＳｎのはんだボールであり、導電バンプ１２３はＳｎ−Ａｇ系のはんだバンプである。但し、導電パッド１０２、導電ボール１０３及び導電バンプ１２３の材料はこれらに限定されない。   In the semiconductor device 100 according to the first embodiment, a plurality of conductive pads 102 and a solder resist 104 are provided on a mounting substrate 101. An opening for exposing a part of each conductive pad 102 is provided in the solder resist 104, and a conductive ball 103 is provided in the opening. The bridge chip 121 is fixed to the mounting substrate 101 by an ultraviolet curable resin (UV curable resin) 111. The bridge chip 121 includes a plurality of conductive bumps 123 on the first main surface opposite to the second main surface on the mounting substrate 101 side, and wirings 122 that electrically connect the conductive bumps 123. Yes. For example, the conductive pads 102 are Cu pads, the conductive balls 103 are Sn-Ag-Cu solder balls or Sn solder balls, and the conductive bumps 123 are Sn-Ag solder bumps. However, the materials of the conductive pad 102, the conductive ball 103, and the conductive bump 123 are not limited to these.

半導体装置１００には、半導体チップ１４１及び半導体チップ１５１が含まれている。半導体チップ１４１には、複数の導電ボール１０３の一部に接触する複数の端子１４３、及び、複数の導電バンプ１２３の一部に接触する複数の端子１４２が含まれている。半導体チップ１５１には、複数の導電ボール１０３の他の一部に接触する複数の端子１５３、及び、複数の導電バンプ１２３の他の一部に接触する複数の端子１５２が含まれている。半導体チップ１４１と実装基板１０１との間、及び、半導体チップ１５１と実装基板１０１との間等にアンダーフィル材１７１が充填されている。   The semiconductor device 100 includes a semiconductor chip 141 and a semiconductor chip 151. The semiconductor chip 141 includes a plurality of terminals 143 that contact a part of the plurality of conductive balls 103 and a plurality of terminals 142 that contact a part of the plurality of conductive bumps 123. The semiconductor chip 151 includes a plurality of terminals 153 that contact other parts of the plurality of conductive balls 103 and a plurality of terminals 152 that contact other parts of the plurality of conductive bumps 123. An underfill material 171 is filled between the semiconductor chip 141 and the mounting substrate 101 and between the semiconductor chip 151 and the mounting substrate 101.

なお、図２には、便宜上、端子１４２、端子１４３、端子１５２及び端子１５３を１個のみ図示し、これに対応するように、導電ボール１０３及び導電バンプ１２３を図示しているが、これら端子等は、図１に示す参考例の端子５４２及び端子５４３等のように、複数設けられている。端子１４２、端子１４３、端子１５２及び端子１５３は、例えば、Ｃｕピラー及びＣｕピラーを覆うＳｎ−Ａｇはんだ層を含む。但し、端子１４２、端子１４３、端子１５２及び端子１５３の構成はこれに限定されない。   In FIG. 2, for convenience, only one terminal 142, terminal 143, terminal 152, and terminal 153 are illustrated, and the conductive ball 103 and the conductive bump 123 are illustrated to correspond thereto. Are provided in a plurality, such as the terminal 542 and the terminal 543 in the reference example shown in FIG. The terminal 142, the terminal 143, the terminal 152, and the terminal 153 include, for example, a Cu pillar and a Sn—Ag solder layer that covers the Cu pillar. However, the structure of the terminal 142, the terminal 143, the terminal 152, and the terminal 153 is not limited to this.

第１の実施形態では、ブリッジチップ１２１の実装基板１０１への固定にＵＶ硬化樹脂１１１が用いられている。詳細は後述するが、ＵＶ硬化樹脂１１１の硬化には実装基板１０１が反るような加熱は必要とされないため、熱硬化樹脂を用いる場合に生じる実装基板１０１の反りを防止することができる。また、ＵＶ硬化樹脂１１１の硬化は速やかに行われるため、時間の経過と共に拡大する位置ずれを抑制することができる。   In the first embodiment, the UV curable resin 111 is used for fixing the bridge chip 121 to the mounting substrate 101. Although details will be described later, since the heating of the mounting substrate 101 is not required for curing the UV curable resin 111, it is possible to prevent the mounting substrate 101 from being warped when the thermosetting resin is used. Moreover, since the curing of the UV curable resin 111 is performed promptly, it is possible to suppress the displacement that expands with time.

次に、第１の実施形態に係る半導体装置の製造方法について説明する。図３Ａ乃至図３Ｂは、第１の実施形態に係る半導体装置の製造方法を工程順に示す断面図である。   Next, a method for manufacturing the semiconductor device according to the first embodiment will be described. 3A to 3B are cross-sectional views showing the method of manufacturing the semiconductor device according to the first embodiment in the order of steps.

第１の実施形態では、図３Ａ（ａ）に示すように、導電パッド１０２及びソルダレジスト１０４を備えた実装基板１０１を準備する。ソルダレジスト１０４に各導電パッド１０２の一部を露出する開口部を設け、この開口部内で導電パッド１０２上に導電ボール１０３を設ける。また、ソルダレジスト１０４には、ブリッジチップ１２１が設けられる位置に、実装基板１０１を露出する開口部を設け、この開口部内で実装基板１０１上にＵＶ硬化樹脂１１１を滴下する。ＵＶ硬化樹脂１１１としては、例えばエポキシ樹脂又はアクリル樹脂を含有するものを用いる。導電ボール１０３の直径は、例えば７０μｍ程度である。   In the first embodiment, as shown in FIG. 3A (a), a mounting substrate 101 including a conductive pad 102 and a solder resist 104 is prepared. An opening for exposing a part of each conductive pad 102 is provided in the solder resist 104, and a conductive ball 103 is provided on the conductive pad 102 in this opening. The solder resist 104 is provided with an opening that exposes the mounting substrate 101 at a position where the bridge chip 121 is provided, and the UV curable resin 111 is dropped onto the mounting substrate 101 in the opening. As the UV curable resin 111, for example, a resin containing an epoxy resin or an acrylic resin is used. The diameter of the conductive ball 103 is, for example, about 70 μm.

また、導電バンプ１２３及び配線１２２を備えたブリッジチップ１２１を準備する。ブリッジチップ１２１は、例えばシリコン基板を用いて形成することができる。そして、吸引孔１３２が形成されたアタッチメント１３１の下面に導電バンプ１２３を接触させ、吸引孔１３２を通じてのブリッジチップ１２１の吸引１３３を行う。アタッチメント１３１の下面は平坦であり、この平坦な面に導電バンプ１２３の頂点が接触する。アタッチメント１３１の材料には、紫外線を透過させるもの、例えばガラスを用いる。後述のＵＶ照射１６１の際に、紫外線がＵＶ硬化樹脂１１１に到達できるような開口部がアタッチメント１３１に形成されていれば、アタッチメント１３１に紫外線を遮る材料が用いられてもよい。   In addition, a bridge chip 121 including conductive bumps 123 and wirings 122 is prepared. The bridge chip 121 can be formed using, for example, a silicon substrate. Then, the conductive bump 123 is brought into contact with the lower surface of the attachment 131 in which the suction hole 132 is formed, and the suction 133 of the bridge chip 121 through the suction hole 132 is performed. The lower surface of the attachment 131 is flat, and the apex of the conductive bump 123 contacts this flat surface. As the material of the attachment 131, a material that transmits ultraviolet rays, for example, glass is used. A material that blocks ultraviolet rays may be used for the attachment 131 as long as an opening that allows ultraviolet rays to reach the UV curable resin 111 is formed in the attachment 131 during UV irradiation 161 described later.

次いで、図３Ａ（ｂ）に示すように、吸引１３３を継続しながら、アタッチメント１３１の下面を導電ボール１０３の頂点に接触させる。下面が平坦であるため、導電バンプ１２３の頂点の高さが導電ボール１０３の頂点の高さに揃う。つまり、導電バンプ１２３の頂点及び導電ボール１０３の頂点が実質的に同一平面上に存在するようになる。ＵＶ硬化樹脂１１１の滴下量は、アタッチメント１３１の下面を導電ボール１０３の頂点に接触させたときにブリッジチップ１２１がＵＶ硬化樹脂１１１に押し付けられ、ＵＶ硬化樹脂１１１の少なくとも一部がブリッジチップ１２１の側方にはみ出す程度としておく。従って、アタッチメント１３１の下面を導電ボール１０３の頂点に接触させた結果、ＵＶ硬化樹脂１１１の少なくとも一部がブリッジチップ１２１の側方にはみ出す。   Next, as shown in FIG. 3A (b), the lower surface of the attachment 131 is brought into contact with the apex of the conductive ball 103 while continuing the suction 133. Since the lower surface is flat, the height of the top of the conductive bump 123 is aligned with the height of the top of the conductive ball 103. That is, the apex of the conductive bump 123 and the apex of the conductive ball 103 are substantially on the same plane. The dripping amount of the UV curable resin 111 is such that the bridge chip 121 is pressed against the UV curable resin 111 when the lower surface of the attachment 131 is brought into contact with the apex of the conductive ball 103, and at least a part of the UV curable resin 111 is part of the bridge chip 121. Keep it to the side. Therefore, as a result of bringing the lower surface of the attachment 131 into contact with the apex of the conductive ball 103, at least a part of the UV curable resin 111 protrudes to the side of the bridge chip 121.

その後、図３Ａ（ｃ）に示すように、吸引１３３を継続しながら、紫外線の照射（ＵＶ照射１６１）を行う。この結果、ＵＶ硬化樹脂１１１のブリッジチップ１２１の側方にはみ出している部分が速やかに硬化する。   Thereafter, as shown in FIG. 3A (c), ultraviolet irradiation (UV irradiation 161) is performed while continuing the suction 133. As a result, the portion of the UV curable resin 111 that protrudes to the side of the bridge chip 121 is quickly cured.

続いて、図３Ｂ（ｄ）に示すように、吸引孔１３５が形成されたアタッチメント１３４の下面に、複数の端子１４２及び複数の端子１４３を備えた半導体チップ１４１を接触させ、吸引孔１３５を通じての半導体チップ１４１の吸引１３６を行う。アタッチメント１３４の材料としては、例えば、窒化アルミニウム及び酸化アルミニウム等のセラミックスを用いる。ガラスを用いてもよい。そして、吸引１３６を継続しながら、端子１４２を複数の導電バンプ１２３のうちの所定の一部に接触させ、端子１４３を複数の導電ボール１０３のうちの所定の一部に接触させ、ローカルリフローにより、端子１４２を当該導電バンプ１２３に接合し、端子１４３を当該導電ボール１０３に接合する。このローカルリフローでは、反りが生じるような熱は実装基板１０１に作用しない。   Subsequently, as shown in FIG. 3B (d), a semiconductor chip 141 having a plurality of terminals 142 and a plurality of terminals 143 is brought into contact with the lower surface of the attachment 134 in which the suction holes 135 are formed. Suction 136 of the semiconductor chip 141 is performed. As a material of the attachment 134, for example, ceramics such as aluminum nitride and aluminum oxide are used. Glass may be used. Then, while continuing the suction 136, the terminal 142 is brought into contact with a predetermined part of the plurality of conductive bumps 123, the terminal 143 is brought into contact with a predetermined part of the plurality of conductive balls 103, and the local reflow is performed. The terminal 142 is bonded to the conductive bump 123, and the terminal 143 is bonded to the conductive ball 103. In this local reflow, heat that causes warping does not act on the mounting substrate 101.

次いで、図３Ｂ（ｅ）に示すように、アタッチメント１３４の下面に、複数の端子１５２及び複数の端子１５３を備えた半導体チップ１５１を接触させ、吸引孔１３５を通じての半導体チップ１５１の吸引１３７を行う。そして、吸引１３７を継続しながら、端子１５２を複数の導電バンプ１２３のうちの所定の他の一部に接触させ、端子１５３を複数の導電ボール１０３のうちの所定の他の一部に接触させ、ローカルリフローにより、端子１５２を当該導電バンプ１２３に接合し、端子１５３を当該導電ボール１０３に接合する。このローカルリフローでも、反りが生じるような熱は実装基板１０１に作用しない。   Next, as shown in FIG. 3B (e), the semiconductor chip 151 having a plurality of terminals 152 and a plurality of terminals 153 is brought into contact with the lower surface of the attachment 134, and the semiconductor chip 151 is sucked 137 through the suction holes 135. . Then, while continuing the suction 137, the terminal 152 is brought into contact with a predetermined other part of the plurality of conductive bumps 123, and the terminal 153 is brought into contact with a predetermined other part of the plurality of conductive balls 103. Then, the terminal 152 is joined to the conductive bump 123 and the terminal 153 is joined to the conductive ball 103 by local reflow. Even in this local reflow, heat that causes warping does not act on the mounting substrate 101.

その後、図３Ｂ（ｆ）に示すように、半導体チップ１４１と実装基板１０１との間、及び、半導体チップ１５１と実装基板１０１との間等にアンダーフィル材１７１を充填し、加熱によりアンダーフィル材１７１を硬化させる。この加熱で実装基板１０１に反りが生じたとしても、既に、導電ボール１０３と端子１４３又は端子１５３との接合、及び導電バンプ１２３と端子１４２又は端子１５２との接合が完了しているため、熱硬化樹脂を用いた場合に生じるようなコンタクト不良は生じない。また、この加熱により、ＵＶ硬化樹脂１１１のうちでＵＶ照射１６１では硬化していなかった部分が硬化する。   Thereafter, as shown in FIG. 3B (f), an underfill material 171 is filled between the semiconductor chip 141 and the mounting substrate 101, between the semiconductor chip 151 and the mounting substrate 101, and the underfill material is heated. 171 is cured. Even if the mounting substrate 101 is warped by this heating, the bonding between the conductive ball 103 and the terminal 143 or the terminal 153 and the bonding between the conductive bump 123 and the terminal 142 or the terminal 152 are already completed. Contact failure that occurs when using a cured resin does not occur. Further, by this heating, a portion of the UV curable resin 111 that has not been cured by the UV irradiation 161 is cured.

このようにして半導体装置を製造することができる。   In this way, a semiconductor device can be manufactured.

第１の実施形態によれば、実装基板１０１の反りに伴うコンタクト不良を防止することができる。また、ＵＶ硬化樹脂１１１の硬化が速やかに行われるため、ブリッジチップ１２１の位置ずれを抑制することができる。ブリッジチップ１２１の位置ずれを抑制するという効果は、ＵＶ照射１６１中の吸引１３３の継続によっても得られる効果である。   According to the first embodiment, it is possible to prevent contact failure due to warpage of the mounting substrate 101. Moreover, since the curing of the UV curable resin 111 is performed promptly, the positional deviation of the bridge chip 121 can be suppressed. The effect of suppressing the positional deviation of the bridge tip 121 is an effect obtained even by continuing the suction 133 during the UV irradiation 161.

（第２の実施形態）
次に、第２の実施形態について説明する。図４は、第２の実施形態に係る半導体装置を示す断面図である。 (Second Embodiment)
Next, a second embodiment will be described. FIG. 4 is a cross-sectional view showing a semiconductor device according to the second embodiment.

第２の実施形態に係る半導体装置２００では、第１の実施形態におけるブリッジチップ１２１に代えて、紫外線を透過させるブリッジチップ２２１が含まれている。ブリッジチップ２２１は、例えばガラス基板を用いて形成される。ブリッジチップ２２１は紫外線硬化樹脂（ＵＶ硬化樹脂）２１１により実装基板１０１に固定されている。ブリッジチップ２２１に、第１の主面上の複数の導電バンプ２２３、及び、導電バンプ２２３を電気的に接続する配線２２２が含まれている。端子１４２は複数の導電バンプ２２３の一部に接触し、端子１５２は複数の導電バンプ２２３の他の一部に接触する。例えば、導電バンプ２２３はＳｎ−Ａｇ系のはんだバンプである。但し、導電バンプ２２３の材料はこれに限定されない。他の構成は第１の実施形態と同様である。   In the semiconductor device 200 according to the second embodiment, a bridge chip 221 that transmits ultraviolet rays is included instead of the bridge chip 121 in the first embodiment. The bridge chip 221 is formed using a glass substrate, for example. The bridge chip 221 is fixed to the mounting substrate 101 with an ultraviolet curable resin (UV curable resin) 211. The bridge chip 221 includes a plurality of conductive bumps 223 on the first main surface and wirings 222 that electrically connect the conductive bumps 223. The terminal 142 contacts a part of the plurality of conductive bumps 223, and the terminal 152 contacts another part of the plurality of conductive bumps 223. For example, the conductive bumps 223 are Sn-Ag solder bumps. However, the material of the conductive bump 223 is not limited to this. Other configurations are the same as those of the first embodiment.

第２の実施形態によっても第１の実施形態と同様の効果を得ることができる。また、第２の実施形態では、ブリッジチップ２２１が紫外線を透過させるため、詳細は後述するが、ＵＶ照射によるブリッジチップ２２１の実装基板１０１への固定をより強固なものとすることができる。   According to the second embodiment, the same effect as that of the first embodiment can be obtained. In the second embodiment, since the bridge chip 221 transmits ultraviolet rays, details will be described later, but the fixing of the bridge chip 221 to the mounting substrate 101 by UV irradiation can be made stronger.

次に、第２の実施形態に係る半導体装置の製造方法について説明する。図５Ａ乃至図５Ｂは、第２の実施形態に係る半導体装置の製造方法を工程順に示す断面図である。   Next, a method for manufacturing a semiconductor device according to the second embodiment will be described. FIG. 5A to FIG. 5B are cross-sectional views showing the method of manufacturing the semiconductor device according to the second embodiment in the order of steps.

第２の実施形態では、図５Ａ（ａ）に示すように、第１の実施形態と同様に、実装基板１０１を準備し、ソルダレジスト１０４に各導電パッド１０２の一部を露出する開口部を設け、この開口部内で導電パッド１０２上に導電ボール１０３を設ける。また、ソルダレジスト１０４には、ブリッジチップ２２１が設けられる位置に、実装基板１０１を露出する開口部を設け、この開口部内で実装基板１０１上にＵＶ硬化樹脂２１１を滴下する。ＵＶ硬化樹脂２１１としては、例えばエポキシ樹脂又はアクリル樹脂を含有するものを用いる。   In the second embodiment, as shown in FIG. 5A (a), as in the first embodiment, a mounting substrate 101 is prepared, and an opening for exposing a part of each conductive pad 102 to the solder resist 104 is formed. The conductive ball 103 is provided on the conductive pad 102 in the opening. The solder resist 104 is provided with an opening for exposing the mounting substrate 101 at a position where the bridge chip 221 is provided, and the UV curable resin 211 is dropped on the mounting substrate 101 in the opening. As the UV curable resin 211, for example, a resin containing an epoxy resin or an acrylic resin is used.

また、導電バンプ２２３及び配線２２２を備えた紫外線を透過させるブリッジチップ２２１を準備する。そして、アタッチメント１３１の下面に導電バンプ２２３を接触させ、吸引孔１３２を通じてのブリッジチップ２２１の吸引１３３を行う。   In addition, a bridge chip 221 that transmits ultraviolet rays and includes conductive bumps 223 and wirings 222 is prepared. Then, the conductive bump 223 is brought into contact with the lower surface of the attachment 131, and the suction 133 of the bridge chip 221 through the suction hole 132 is performed.

次いで、図５Ａ（ｂ）に示すように、吸引１３３を継続しながら、アタッチメント１３１の下面を導電ボール１０３の頂点に接触させる。下面が平坦であるため、導電バンプ２２３の頂点の高さが導電ボール１０３の頂点の高さに揃う。つまり、導電バンプ２２３の頂点及び導電ボール１０３の頂点が実質的に同一平面上に存在するようになる。ＵＶ硬化樹脂２１１の滴下量は、例えば、アタッチメント１３１の下面を導電ボール１０３の頂点に接触させたときに、少なくともブリッジチップ２２１がＵＶ硬化樹脂２１１に押し付けられる程度とし、より好ましくは、ＵＶ硬化樹脂２１１の一部がブリッジチップ２２１の側方にはみ出す程度としておく。従って、アタッチメント１３１の下面を導電ボール１０３の頂点に接触させた結果、ブリッジチップ２２１がＵＶ硬化樹脂２１１を押し付けられ、好ましくはＵＶ硬化樹脂２１１の一部がブリッジチップ２２１の側方にはみ出す。   Next, as illustrated in FIG. 5A (b), the lower surface of the attachment 131 is brought into contact with the apex of the conductive ball 103 while continuing the suction 133. Since the lower surface is flat, the height of the top of the conductive bump 223 is aligned with the height of the top of the conductive ball 103. That is, the vertex of the conductive bump 223 and the vertex of the conductive ball 103 are substantially on the same plane. The dripping amount of the UV curable resin 211 is set such that, for example, at least the bridge chip 221 is pressed against the UV curable resin 211 when the lower surface of the attachment 131 is brought into contact with the apex of the conductive ball 103, and more preferably the UV curable resin. A part of 211 protrudes to the side of the bridge chip 221. Therefore, as a result of bringing the lower surface of the attachment 131 into contact with the apex of the conductive ball 103, the bridge chip 221 is pressed against the UV curable resin 211, and preferably a part of the UV curable resin 211 protrudes to the side of the bridge chip 221.

その後、図５Ａ（ｃ）に示すように、吸引１３３を継続しながら、紫外線の照射（ＵＶ照射１６１）を行う。この結果、ＵＶ硬化樹脂２１１が速やかに硬化する。第１の実施形態ではブリッジチップ１２１により紫外線が遮られた部分ではＵＶ硬化樹脂１１１が硬化しないが、第２の実施形態ではブリッジチップ２２１が紫外線を透過させるため、ブリッジチップ２２１の直下でもブリッジチップ２２１が硬化する。   Thereafter, as shown in FIG. 5A (c), ultraviolet irradiation (UV irradiation 161) is performed while continuing the suction 133. As a result, the UV curable resin 211 is quickly cured. In the first embodiment, the UV curable resin 111 is not cured at the portion where the ultraviolet ray is blocked by the bridge chip 121, but in the second embodiment, the bridge chip 221 transmits the ultraviolet ray. 221 is cured.

続いて、図５Ｂ（ｄ）に示すように、アタッチメント１３４の下面に半導体チップ１４１を接触させ、吸引孔１３５を通じての半導体チップ１４１の吸引１３６を行う。そして、吸引１３６を継続しながら、端子１４２を複数の導電バンプ２２３のうちの所定の一部に接触させ、端子１４３を複数の導電ボール１０３のうちの所定の一部に接触させ、ローカルリフローにより、端子１４２を当該導電バンプ２２３に接合し、端子１４３を当該導電ボール１０３に接合する。このローカルリフローでは、反りが生じるような熱は実装基板１０１に作用しない。   Subsequently, as shown in FIG. 5B (d), the semiconductor chip 141 is brought into contact with the lower surface of the attachment 134, and the semiconductor chip 141 is sucked 136 through the suction holes 135. Then, while continuing the suction 136, the terminal 142 is brought into contact with a predetermined part of the plurality of conductive bumps 223, the terminal 143 is brought into contact with a predetermined part of the plurality of conductive balls 103, and local reflow is performed. The terminal 142 is bonded to the conductive bump 223 and the terminal 143 is bonded to the conductive ball 103. In this local reflow, heat that causes warping does not act on the mounting substrate 101.

次いで、図５Ｂ（ｅ）に示すように、アタッチメント１３４の下面に半導体チップ１５１を接触させ、吸引孔１３５を通じての半導体チップ１５１の吸引１３７を行う。そして、吸引１３７を継続しながら、端子１５２を複数の導電バンプ２２３のうちの所定の他の一部に接触させ、端子１５３を複数の導電ボール１０３のうちの所定の他の一部に接触させ、ローカルリフローにより、端子１５２を当該導電バンプ２２３に接合し、端子１５３を当該導電ボール１０３に接合する。このローカルリフローでも、反りが生じるような熱は実装基板１０１に作用しない。   Next, as shown in FIG. 5B (e), the semiconductor chip 151 is brought into contact with the lower surface of the attachment 134, and the semiconductor chip 151 is sucked 137 through the suction holes 135. Then, while continuing the suction 137, the terminal 152 is brought into contact with a predetermined other part of the plurality of conductive bumps 223, and the terminal 153 is brought into contact with a predetermined other part of the plurality of conductive balls 103. Then, the terminal 152 is bonded to the conductive bump 223 and the terminal 153 is bonded to the conductive ball 103 by local reflow. Even in this local reflow, heat that causes warping does not act on the mounting substrate 101.

その後、図５Ｂ（ｆ）に示すように、半導体チップ１４１と実装基板１０１との間、及び、半導体チップ１５１と実装基板１０１との間等にアンダーフィル材１７１を充填し、加熱によりアンダーフィル材１７１を硬化させる。この加熱で実装基板１０１に反りが生じたとしても、既に、導電ボール１０３と端子１４３又は端子１５３との接合、及び導電バンプ２２３と端子１４２又は端子１５２との接合が完了しているため、熱硬化樹脂を用いた場合に生じるようなコンタクト不良は生じない。   Thereafter, as shown in FIG. 5B (f), an underfill material 171 is filled between the semiconductor chip 141 and the mounting substrate 101, between the semiconductor chip 151 and the mounting substrate 101, and the underfill material is heated. 171 is cured. Even if the mounting substrate 101 is warped by this heating, the bonding between the conductive ball 103 and the terminal 143 or the terminal 153 and the bonding between the conductive bump 223 and the terminal 142 or the terminal 152 are already completed. Contact failure that occurs when using a cured resin does not occur.

このようにして半導体装置を製造することができる。   In this way, a semiconductor device can be manufactured.

第２の実施形態によっても、実装基板１０１の反りに伴うコンタクト不良を防止することができる。また、ＵＶ硬化樹脂２１１の硬化が速やかに行われるため、ブリッジチップ２２１の位置ずれを抑制することができる。ブリッジチップ２２１の位置ずれを抑制するという効果は、ＵＶ照射１６１中の吸引１３３の継続によっても得られる効果である。更に、ＵＶ照射１６１によりＵＶ硬化樹脂２１１のほぼ全体が硬化するため、ブリッジチップ２２１の実装基板１０１への固定がより強固なものとなる。   Also according to the second embodiment, it is possible to prevent contact failure due to warpage of the mounting substrate 101. Moreover, since the curing of the UV curable resin 211 is performed promptly, the positional deviation of the bridge chip 221 can be suppressed. The effect of suppressing the positional deviation of the bridge tip 221 is an effect obtained even by continuing the suction 133 during the UV irradiation 161. Furthermore, since almost all of the UV curable resin 211 is cured by the UV irradiation 161, the bridge chip 221 is more firmly fixed to the mounting substrate 101.

以下、本発明の諸態様を付記としてまとめて記載する。   Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

（付記１）
実装基板上に紫外線硬化樹脂を設ける工程と、
前記紫外線硬化樹脂に、第１の主面上の第１の導電バンプ、第２の導電バンプ並びに前記第１の導電バンプ及び前記第２の導電バンプを電気的に接続する配線を有するブリッジチップを、前記第１の主面とは反対側の第２の主面を前記実装基板側に向けて押し付ける工程と、
前記紫外線硬化樹脂に紫外線を照射して前記ブリッジチップを前記実装基板に固定する工程と、
前記第１の導電バンプに接続される第１の半導体チップ及び前記第２の導電バンプに接続される第２の半導体チップを前記実装基板上に搭載する工程と、
を有することを特徴とする半導体装置の製造方法。 (Appendix 1)
Providing a UV curable resin on the mounting substrate;
A bridge chip having a first conductive bump, a second conductive bump on the first main surface, and a wiring for electrically connecting the first conductive bump and the second conductive bump to the ultraviolet curable resin. Pressing the second main surface opposite to the first main surface toward the mounting substrate side;
Irradiating the ultraviolet curable resin with ultraviolet rays to fix the bridge chip to the mounting substrate;
Mounting a first semiconductor chip connected to the first conductive bump and a second semiconductor chip connected to the second conductive bump on the mounting substrate;
A method for manufacturing a semiconductor device, comprising:

（付記２）
前記実装基板上に前記第１の半導体チップに接続される第１の導電ボール及び前記第２の半導体チップに接続される第２の導電ボールを設けておき、
前記紫外線硬化樹脂に前記ブリッジチップを押し付ける工程は、アタッチメントを用いて、前記第１の導電バンプ及び前記第２の導電バンプの頂点の高さを前記第１の導電ボール及び前記第２の導電ボールの頂点の高さに揃える工程を有することを特徴とする付記１に記載の半導体装置の製造方法。 (Appendix 2)
A first conductive ball connected to the first semiconductor chip and a second conductive ball connected to the second semiconductor chip are provided on the mounting substrate;
In the step of pressing the bridge chip against the ultraviolet curable resin, the heights of the first conductive bump and the second conductive bump are set to the heights of the first conductive ball and the second conductive ball using an attachment. The method of manufacturing a semiconductor device according to appendix 1, further comprising a step of aligning the heights of the vertices.

（付記３）
前記アタッチメントは、紫外線を透過させることを特徴とする付記２に記載の半導体装置の製造方法。 (Appendix 3)
The method of manufacturing a semiconductor device according to appendix 2, wherein the attachment transmits ultraviolet rays.

（付記４）
前記アタッチメントは、前記第１の導電ボール及び前記第２の導電バンプの頂点及び前記第１の導電バンプ及び前記第２の導電ボールの頂点が接する平坦な面を有することを特徴とする付記２又は３に記載の半導体装置の製造方法。 (Appendix 4)
The attachment has a flat surface on which the apexes of the first conductive ball and the second conductive bump and the apexes of the first conductive bump and the second conductive ball are in contact with each other. 4. A method for manufacturing a semiconductor device according to 3.

（付記５）
前記紫外線硬化樹脂に前記ブリッジチップを押し付ける工程から前記ブリッジチップを前記実装基板に固定する工程までの間、前記ブリッジチップを前記アタッチメントに吸引し続けることを特徴とする付記２乃至４のいずれか１項に記載の半導体装置の製造方法。 (Appendix 5)
Any one of appendixes 2 to 4, wherein the bridge chip is continuously sucked to the attachment from the step of pressing the bridge chip against the ultraviolet curable resin to the step of fixing the bridge chip to the mounting substrate. A method for manufacturing the semiconductor device according to the item.

（付記６）
前記ブリッジチップは、紫外線を透過させることを特徴とする付記１乃至５のいずれか１項に記載の半導体装置の製造方法。 (Appendix 6)
6. The method of manufacturing a semiconductor device according to any one of appendices 1 to 5, wherein the bridge chip transmits ultraviolet rays.

（付記７）
実装基板と、
第１の主面上の第１の導電バンプ、第２の導電バンプ並びに前記第１の導電バンプ及び前記第２の導電バンプを電気的に接続する配線を有し、前記第１の主面とは反対側の第２の主面を前記実装基板側に向けて、紫外線硬化樹脂を用いて前記実装基板に固定されたブリッジチップと、
前記実装基板上に搭載され、前記第１の導電バンプに接続された第１の半導体チップ及び前記第２の導電バンプに接続される第２の半導体チップと、
を有することを特徴とする半導体装置。 (Appendix 7)
A mounting board;
A first conductive bump on the first main surface; a second conductive bump; and a wiring for electrically connecting the first conductive bump and the second conductive bump; Is a bridge chip fixed to the mounting substrate using an ultraviolet curable resin with the second main surface on the opposite side facing the mounting substrate side,
A first semiconductor chip mounted on the mounting substrate and connected to the first conductive bump and a second semiconductor chip connected to the second conductive bump;
A semiconductor device comprising:

（付記８）
前記ブリッジチップは紫外線を透過させることを特徴とする付記７に記載の半導体装置。 (Appendix 8)
The semiconductor device according to appendix 7, wherein the bridge chip transmits ultraviolet rays.

（付記９）
前記実装基板上に設けられ前記第１の半導体チップに接続された第１の導電ボール及び前記第２の半導体チップに接続される第２の導電ボールを有し、
前記第１の導電バンプ及び前記第２の導電バンプの頂点及び前記第１の導電ボール及び前記第２の導電ボールの頂点の高さが揃えられたことを特徴とする付記７又は８に記載の半導体装置。 (Appendix 9)
A first conductive ball provided on the mounting substrate and connected to the first semiconductor chip; and a second conductive ball connected to the second semiconductor chip;
Item 9. The appendix 7 or 8, wherein heights of the first conductive bumps and the second conductive bumps and heights of the first conductive balls and the second conductive balls are aligned. Semiconductor device.

１００、２００：半導体装置
１０１：実装基板
１０３：導電ボール
１１１、２１１：紫外線硬化樹脂
１２１、２２１：ブリッジチップ
１４１、１５１：半導体チップ 100, 200: Semiconductor device 101: Mounting substrate 103: Conductive ball 111, 211: UV curable resin 121, 221: Bridge chip 141, 151: Semiconductor chip

Claims (7)

実装基板上に紫外線硬化樹脂を設ける工程と、
前記紫外線硬化樹脂に、第１の主面上の第１の導電バンプ、第２の導電バンプ並びに前記第１の導電バンプ及び前記第２の導電バンプを電気的に接続する配線を有するブリッジチップを、前記第１の主面とは反対側の第２の主面を前記実装基板側に向けて押し付ける工程と、
前記紫外線硬化樹脂に紫外線を照射して前記ブリッジチップを前記実装基板に固定する工程と、
前記第１の導電バンプに接続される第１の半導体チップ及び前記第２の導電バンプに接続される第２の半導体チップを前記実装基板上に搭載する工程と、
を有することを特徴とする半導体装置の製造方法。 Providing a UV curable resin on the mounting substrate;
A bridge chip having a first conductive bump, a second conductive bump on the first main surface, and a wiring for electrically connecting the first conductive bump and the second conductive bump to the ultraviolet curable resin. Pressing the second main surface opposite to the first main surface toward the mounting substrate side;
Irradiating the ultraviolet curable resin with ultraviolet rays to fix the bridge chip to the mounting substrate;
Mounting a first semiconductor chip connected to the first conductive bump and a second semiconductor chip connected to the second conductive bump on the mounting substrate;
A method for manufacturing a semiconductor device, comprising: 前記実装基板上に前記第１の半導体チップに接続される第１の導電ボール及び前記第２の半導体チップに接続される第２の導電ボールを設けておき、
前記紫外線硬化樹脂に前記ブリッジチップを押し付ける工程は、アタッチメントを用いて、前記第１の導電バンプ及び前記第２の導電バンプの頂点の高さを前記第１の導電ボール及び前記第２の導電ボールの頂点の高さに揃える工程を有することを特徴とする請求項１に記載の半導体装置の製造方法。 A first conductive ball connected to the first semiconductor chip and a second conductive ball connected to the second semiconductor chip are provided on the mounting substrate;
In the step of pressing the bridge chip against the ultraviolet curable resin, the heights of the first conductive bump and the second conductive bump are set to the heights of the first conductive ball and the second conductive ball using an attachment. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of aligning the heights of the tops of the semiconductor devices. 前記アタッチメントは、紫外線を透過させることを特徴とする請求項２に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 2, wherein the attachment transmits ultraviolet rays. 前記アタッチメントは、前記第１の導電ボール及び前記第２の導電バンプの頂点及び前記第１の導電バンプ及び前記第２の導電ボールの頂点が接する平坦な面を有することを特徴とする請求項２又は３に記載の半導体装置の製造方法。   3. The attachment has a flat surface where the apexes of the first conductive ball and the second conductive bump and the apexes of the first conductive bump and the second conductive ball are in contact with each other. Or a method of manufacturing the semiconductor device according to 3. 前記紫外線硬化樹脂に前記ブリッジチップを押し付ける工程から前記ブリッジチップを前記実装基板に固定する工程までの間、前記ブリッジチップを前記アタッチメントに吸引し続けることを特徴とする請求項２乃至４のいずれか１項に記載の半導体装置の製造方法。   The bridge chip is continuously sucked into the attachment from the step of pressing the bridge chip against the ultraviolet curable resin to the step of fixing the bridge chip to the mounting substrate. 2. A method for manufacturing a semiconductor device according to item 1. 前記ブリッジチップは、紫外線を透過させることを特徴とする請求項１乃至５のいずれか１項に記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 1, wherein the bridge chip transmits ultraviolet light. 実装基板と、
第１の主面上の第１の導電バンプ、第２の導電バンプ並びに前記第１の導電バンプ及び前記第２の導電バンプを電気的に接続する配線を有し、前記第１の主面とは反対側の第２の主面を前記実装基板側に向けて、紫外線硬化樹脂を用いて前記実装基板に固定されたブリッジチップと、
前記実装基板上に搭載され、前記第１の導電バンプに接続された第１の半導体チップ及び前記第２の導電バンプに接続される第２の半導体チップと、
を有することを特徴とする半導体装置。 A mounting board;
A first conductive bump on the first main surface; a second conductive bump; and a wiring for electrically connecting the first conductive bump and the second conductive bump; Is a bridge chip fixed to the mounting substrate using an ultraviolet curable resin with the second main surface on the opposite side facing the mounting substrate side,
A first semiconductor chip mounted on the mounting substrate and connected to the first conductive bump and a second semiconductor chip connected to the second conductive bump;
A semiconductor device comprising:
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