JP2011071381A - 積層型半導体装置およびその製造方法 - Google Patents

積層型半導体装置およびその製造方法 Download PDF

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Publication number
JP2011071381A
JP2011071381A JP2009221980A JP2009221980A JP2011071381A JP 2011071381 A JP2011071381 A JP 2011071381A JP 2009221980 A JP2009221980 A JP 2009221980A JP 2009221980 A JP2009221980 A JP 2009221980A JP 2011071381 A JP2011071381 A JP 2011071381A
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Prior art keywords
semiconductor chip
chip
connection region
region
stacked
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Abandoned
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JP2009221980A
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English (en)
Inventor
Kazuma Suzuki
一真 鈴木
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Toshiba Corp
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Toshiba Corp
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Priority to JP2009221980A priority Critical patent/JP2011071381A/ja
Priority to US12/718,022 priority patent/US20110074015A1/en
Publication of JP2011071381A publication Critical patent/JP2011071381A/ja
Abandoned legal-status Critical Current

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Abstract

【課題】モールド樹脂の剥離を防止しつつ、アンダーフィル樹脂層中のボイド発生の抑止および積層する半導体チップ間のギャップの測定精度の低下を防止することのできる積層型半導体装置およびその製造方法を提供する。
【解決手段】マイクロバンプ３による接続により上段側半導体チップ２が積層され、上段側半導体チップ２との間のギャップにアンダーフィル樹脂６が充填され、モールド樹脂７により封止される下段側半導体チップ１は、ボンディングパッド４の開口部を除く周辺領域のチップ表面にポリイミド膜５が形成されている。
【選択図】 図１

Description

本発明は、積層型半導体装置およびその製造方法に関する。
デジタル機器の高機能化、高性能化の要求に応えるために、論理回路とメモリ回路間のデータ転送の向上やメモリ容量の増加が必要とされる。そこで、１つのパッケージの中に複数の半導体チップを積層するＣｏＣ（Ｃｈｉｐ ｏｎ Ｃｈｉｐ）方式の積層型半導体装置が実用化されている。中でも、積層する半導体チップ間を直径３０μｍ程度のマイクロバンプでフリップチップ接合すると、数千個程度の多点接続が可能となり、バス幅の拡大や伝送速度の向上の面で優位となる。
マイクロバンプなどのバンプを用いてフリップチップ接合する場合、外部接続用のボンディングパッドを有する下段側半導体チップと、上段側半導体チップのそれぞれにバンプを形成した後、下段側半導体チップに設けたバンプと上段側半導体チップに設けたバンプとを接続する。その後、上下の半導体チップ間のギャップにアンダーフィル樹脂を充填し、下段側半導体チップのボンディングパッドにワイヤボンディングを行い、最後に積層した半導体チップ全体をモールド樹脂で封止することが行われている（例えば、特許文献１参照。）。
ただし、モールド樹脂で封止した場合、半導体チップとモールド樹脂の密着性が低いため、半導体チップとモールド樹脂の熱膨張率の違いによる熱応力が加わると、チップコーナーなどでモールド樹脂が剥離することがある。
そこで、従来、半導体チップ表面にポリイミド膜を形成し、モールド樹脂との密着性を向上させることが行われている（例えば、特許文献２参照。）。
しかし、マイクロバンプでフリップチップ接合する場合に、下段側半導体チップの全面にポリイミド膜を形成すると、もともと狭い上下チップ間のギャップがさらに狭くなり、アンダーフィル樹脂を注入するとき、マイクロバンプ領域にアンダーフィル樹脂を均等に充填することが困難になる。アンダーフィル樹脂の充填が不均等になると、アンダーフィル樹脂層中にボイドが発生し、パッケージ組み立て中の熱処理などによりマイクロバンプが破壊される、という問題が発生する。
また、下段側半導体チップの全面にポリイミド膜を形成すると、上下の半導体チップ間のギャップを正確に測定することが困難になる、という問題もあった。
特開２００８−１９２８１５号公報 （第４ページ、図１） 特開平８−１８６１０９号公報 （第３ページ、図１）
そこで、本発明の目的は、モールド樹脂の剥離を防止しつつ、アンダーフィル樹脂層中のボイド発生の抑止および積層する半導体チップ間のギャップの測定精度の低下を防止することのできる積層型半導体装置およびその製造方法を提供することにある。
本発明の一態様によれば、第１の複数のマイクロバンプが形成された第１の接続領域および複数のボンディングパッドが形成された周辺領域を有する第１の半導体チップと、前記第１の接続領域に対向する面に第２の複数のマイクロバンプが形成された第２の接続領域を有し、前記第１の複数のマイクロバンプと前記第２の複数のマイクロバンプが接続されて、前記第１の半導体チップ上に積層された第２の半導体チップと、前記第１の半導体チップと前記第２の半導体チップのギャップに充填されたアンダーフィル樹脂と、前記第１の半導体チップおよび前記第２の半導体チップを封止するモールド樹脂とを備え、前記第１の半導体チップの前記周辺領域のうちの前記ボンディングパッドの開口部を除く領域のチップ表面に、前記モールド樹脂との密着性が良好な膜が形成されていることを特徴とする積層型半導体装置が提供される。
また、本発明の別の一態様によれば、第１の接続領域に第１の複数のマイクロバンプを形成し、周辺領域に複数のボンディングパッドを形成し、前記周辺領域の前記ボンディングパッドの開口部を除く領域のチップ表面に前記モールド樹脂との密着性が良好な膜を形成して第１の半導体チップを製造する工程と、第２の接続領域に第２の複数のマイクロバンプを形成して第２の半導体チップを製造する工程と、前記第１の接続領域と前記第２の接続領域を対面させ、前記第１の複数のマイクロバンプと前記第２の複数のマイクロバンプを接続して、前記第１の半導体チップの上に前記第２の半導体チップを積層する工程と、前記第１の半導体チップと前記第２の半導体チップのギャップにアンダーフィル樹脂を充填する工程と、前記第１の半導体チップおよび前記第２の半導体チップをモールド樹脂で封止する工程とを備えることを特徴とする積層型半導体装置の製造方法が提供される。
本発明によれば、モールド樹脂の剥離を防止しつつ、アンダーフィル樹脂層中のボイド発生の抑止および積層する半導体チップ間のギャップの測定精度の低下を防止することができる。
本発明の実施例１に係る積層型半導体装置の構成の例を示す模式的断面図。 本発明の実施例１に係る積層型半導体装置の下段側半導体チップの構成の例を示す模式的平面図。 本発明の実施例１に係る積層型半導体装置の上段側半導体チップの構成の例を示す模式的平面図。 本発明の実施例１に係る積層型半導体装置の製造方法の例を示すフロー図。 本発明の実施例１に係る積層型半導体装置の製造工程を説明するための模式的断面図。 本発明の実施例１に係る積層型半導体装置の製造工程を説明するための模式的断面図。 本発明の実施例１に係る積層型半導体装置の製造工程を説明するための模式的断面図。 本発明の実施例２に係る積層型半導体装置の下段側半導体チップの構成の例を示す模式的平面図。 本発明の実施例２に係る積層型半導体装置におけるアンダーフィル樹脂充填の様子を示す模式的断面図。 本発明の実施例２に係る積層型半導体装置の構成の例を示す模式的断面図。
以下、本発明の実施例について図面を参照して説明する。なお、図中、同一または相当部分には同一の符号を付して、その説明は繰り返さない。
図１は、本発明の実施例１に係る積層型半導体装置の構成の例を示す模式的断面図である。
本実施例の積層型半導体装置は、下段側半導体チップ１の上にマイクロバンプ３を介して上段側半導体チップ２が積層される構造をとる。ここで、下段側半導体チップ１および上段側半導体チップ２の構成の例を図２、図３にそれぞれ示す。
図２は、下段側半導体チップ１の構成の例を示す模式的平面図である。
下段側半導体チップ１は、複数のマイクロバンプ３Ａが形成された接続領域１１と、複数のボンディングパッド４が形成された周辺領域１２と、を有する。
ここで、本実施例の下段側半導体チップ１に特徴的なことは、接続領域１１と周辺領域１２のボンディングパッド４の開口部と、を除く領域のチップ表面に、ポリイミド膜５が形成されていることである。
図３は、上段側半導体チップ２の構成の例を示す模式的平面図である。
上段側半導体チップ２は、下段側半導体チップ１に積層されたときに下段側半導体チップ１の接続領域１１に対向する面に、複数のマイクロバンプ３Ｂが形成された接続領域２１を有する。
下段側半導体チップ１上に上段側半導体チップ２が積層されるとき、下段側半導体チップ１の接続領域１１と上段側半導体チップ２の接続領域２１は対向され、下段側半導体チップ１のマイクロバンプ３Ａと上段側半導体チップ２のマイクロバンプ３Ｂが接続される。この接続により、マイクロバンプ３Ａとマイクロバンプ３Ｂは一体化され、図１に示すマイクロバンプ３が形成される。
図１に戻って、下段側半導体チップ１の上にマイクロバンプ３を介して上段側半導体チップ２が積層された本実施例の積層型半導体装置は、下段側半導体チップ１と上段側半導体チップ２のギャップに充填されたアンダーフィル樹脂６と、下段側半導体チップ１および上段側半導体チップ２を封止するモールド樹脂７と、を備える。
ここで、本実施例の下段側半導体チップ１の周辺領域１２のチップ表面には、上述したように、接続領域１１とボンディングパッド４の開口部と、を除く領域に、ポリイミド膜５が形成されている。したがって、本実施例では、下段側半導体チップ１のチップ表面が、直接、モールド樹脂７と接触することはない。
なお、図１に示す例では、下段側半導体チップ１は配線基板１０１に接続され、下段側半導体チップ１のボンディングパッド４は、配線基板１０１の接続パッド１０２とボンディングワイヤ１０３により接続され、配線基板１０１には外部接続端子１０４が形成されているものとする。
次に、本実施例の積層型半導体装置の製造方法について、図４のフロー図および図５〜図７の模式的断面図を用いて説明する。
図４は、本発明の実施例１に係る積層型半導体装置の製造方法の例を示すフロー図である。
本実施例の積層型半導体装置の製造にあたっては、先ず、下段側半導体チップ１の製造を行う。下段側半導体チップ１の製造においては、接続領域１１と周辺領域１２のボンディングパッド４の開口部とを除く領域のチップ表面に、膜厚が３μｍ程度のポリイミド膜５を形成し、周辺領域１２に複数のボンディングパッド４を形成し、接続領域１１に複数のマイクロバンプ３Ａを形成する（工程Ｓ０１）。
このとき、ポリイミド膜５は、例えば、感光性のポリイミドをチップ全面に塗布し、露光・現像後に、接続領域１１および周辺領域１２のボンディングパッド４の開口部のポリイミドをエッチングで除去する方法などにより、形成される。
次に、上段側半導体チップ２の製造を行う。上段側半導体チップ２の製造においては、接続領域２１に複数のマイクロバンプ３Ｂを形成する（工程Ｓ０２）。
なお、工程Ｓ０１と工程Ｓ０２は、別々の製造ラインを用いて、並行に進めることも可能であり、また、工程Ｓ０２を工程Ｓ０１よりも先に実行し、上段側半導体チップ２を先に製造してもよい。
続いて、配線基板１０１に下段側半導体チップ１を接続した後、図５（ａ）に示すように、下段側半導体チップ１の接続領域１１と上段側半導体チップ２の接続領域２１を対向させて、図５（ｂ）に示すように、マイクロバンプ３Ａとマイクロバンプ３Ｂを接続して、下段側半導体チップ１の上に上段側半導体チップ２を積層する（工程Ｓ０３）。
このマイクロバンプ同士の接続により、マイクロバンプ３Ａとマイクロバンプ３Ｂは一体化され、図５（ｂ）に示すマイクロバンプ３が形成される。
次に、図６に示すように、下段側半導体チップ１と上段側半導体チップ２のギャップにアンダーフィル樹脂６を充填する（工程Ｓ０４）。
次に、図７に示すように、下段側半導体チップ１のボンディングパッド４と配線基板１０１の接続パッド１０２をボンディングワイヤ１０３により接続した後、下段側半導体チップ１と上段側半導体チップ２をモールド樹脂７で封止する（工程Ｓ０５）。
これにより、下段側半導体チップ１の上に上段側半導体チップ２を積層する工程は終了する。
このような本実施例によれば、下段側半導体チップ１の周辺領域１２のボンディングパッド４の開口部領を除く領域にのみポリイミド膜５が形成されているので、モールド樹脂７は、下段側半導体チップ１のチップ表面と接触せず、ポリイミド膜５と接触する。モールド樹脂７とポリイミド膜５との密着性は良好なため、下段側半導体チップ１とモールド樹脂７との間の熱応力を緩和することができ、下段側半導体チップ１のチップコーナーなどでモールド樹脂７が剥離することを防止することができる。
また、下段側半導体チップ１のマイクロバンプ３Ａが形成される接続領域１１にも、ポリイミド膜５が形成されないので、アンダーフィル樹脂６を注入するギャップ間隔が狭くならず、アンダーフィル樹脂６の充填が不均等になることを防止することができる。これにより、アンダーフィル樹脂層中のボイドの発生を抑止することができる。
また、接続領域１１にポリイミド膜５が形成されないことにより、ギャップ間隔の測定精度の低下を防止することができる。
実施例１で示した積層型半導体装置の下段側半導体チップ１と上段側半導体チップ２の間のギャップが狭い場合、アンダーフィル樹脂６の流動性が高いほど、アンダーフィル樹脂層中に発生するボイドを少なくすることができる。しかし、アンダーフィル樹脂６の流動性を高めると、下段側半導体チップ１の周辺領域１２へアンダーフィル樹脂６が流出するおそれが大きくなる。そこで、本実施例では、アンダーフィル樹脂６の流動性を高くしても、下段側半導体チップ１の周辺領域１２へアンダーフィル樹脂６が流出することがない積層型半導体装置の例を示す。
図８は、本発明の実施例２に係る積層型半導体装置の下段側半導体チップの構成の例を示す模式的平面図である。
本実施例の下段側半導体チップ１Ａが、実施例１の下段側半導体チップ１と異なる点は、マイクロバンプ３Ａが形成される接続領域１１の外側に、アンダーフィル樹脂６の流出を防止するために、銀（Ａｇ）や錫（Ｓｎ）、あるいはその合金（Ａｇ−Ｓｎ系半田）などの金属を材料とするダム８を設けた点である。また、本実施例では、ダム８の外側にポリイミド膜５が形成される。
図９に、本実施例の下段側半導体チップ１Ａの上に上段側半導体チップ２を積層し、その間のギャップにアンダーフィル樹脂６を充填したときの様子を示す。
図９に示すように、流動性の高いアンダーフィル樹脂６を使用しても、ダム８により、アンダーフィル樹脂６の周辺への流出が防止される。
図１０は、モールド樹脂７による封止工程終了後の、本実施例の積層型半導体装置の模式的断面図である。
本実施例においても、下段側半導体チップ１のチップ表面が直接モールド樹脂７と接触することがないので、下段側半導体チップ１のチップコーナーなどでモールド樹脂７が剥離することを防止することができる。とともに、実施例１と同様、アンダーフィル樹脂層中のボイドの発生を抑止することができ、ギャップ間隔の測定精度の低下を防止することができる。
また、本実施例によれば、アンダーフィル樹脂６の流動性が高くても、下段側半導体チップ１の周辺領域１２へアンダーフィル樹脂６が流出することを防止することができる。
なお、上述の各実施例では、モールド樹脂との密着性が良好な膜の材料としてポリイミドを用いる例を示したが、この膜の材料はポリイミドに限定されるものではなく、例えば、ベンゾシクロブテン（ＢＣＢ）やポリベンゾオキサゾール（ＰＢＯ）、フェノール系樹脂などを用いてもよい。
１、１Ａ 下段側半導体チップ
２ 上段側半導体チップ
３、３Ａ、３Ｂ マイクロバンプ
４ ボンディングパッド
５ ポリイミド膜
６ アンダーフィル樹脂
７ モールド樹脂
８ ダム
１１、２１ 接続領域
１２ 周辺領域

Claims (5)

  1. 第１の複数のマイクロバンプが形成された第１の接続領域および複数のボンディングパッドが形成された周辺領域を有する第１の半導体チップと、
    前記第１の接続領域に対向する面に第２の複数のマイクロバンプが形成された第２の接続領域を有し、前記第１の複数のマイクロバンプと前記第２の複数のマイクロバンプが接続されて、前記第１の半導体チップ上に積層された第２の半導体チップと、
    前記第１の半導体チップと前記第２の半導体チップのギャップに充填されたアンダーフィル樹脂と、
    前記第１の半導体チップおよび前記第２の半導体チップを封止するモールド樹脂と
    を備え、
    前記第１の半導体チップの前記周辺領域のうちの前記ボンディングパッドの開口部を除く領域のチップ表面に、前記モールド樹脂との密着性が良好な膜が形成されている
    ことを特徴とする積層型半導体装置。
  2. 前記第１の半導体チップの前記第１の接続領域の外側に、前記アンダーフィル樹脂の流出を防止するダムが設けられている
    ことを特徴とする請求項１に記載の積層型半導体装置。
  3. 前記モールド樹脂との密着性が良好な膜が、前記ダムが形成される領域よりも外側の領域に形成されている
    ことを特徴とする請求項２に記載の積層型半導体装置。
  4. 第１の接続領域に第１の複数のマイクロバンプを形成し、周辺領域に複数のボンディングパッドを形成し、前記ボンディングパッドの開口部を除く前記周辺領域のチップ表面に前記モールド樹脂との密着性が良好な膜を形成して第１の半導体チップを製造する工程と、
    第２の接続領域に第２の複数のマイクロバンプを形成して第２の半導体チップを製造する工程と、
    前記第１の接続領域と前記第２の接続領域を対面させ、前記第１の複数のマイクロバンプと前記第２の複数のマイクロバンプを接続して、前記第１の半導体チップの上に前記第２の半導体チップを積層する工程と、
    前記第１の半導体チップと前記第２の半導体チップのギャップにアンダーフィル樹脂を充填する工程と、
    前記第１の半導体チップおよび前記第２の半導体チップをモールド樹脂で封止する工程と
    を備えることを特徴とする積層型半導体装置の製造方法。
  5. 前記第１の半導体チップの前記第１の接続領域の外側に、前記アンダーフィル樹脂の流出を防止するダムを設ける
    ことを特徴とする請求項４に記載の積層型半導体装置の製造方法。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014027210A (ja) * 2012-07-30 2014-02-06 Fujitsu Semiconductor Ltd 半導体装置および半導体装置の製造方法
KR101613009B1 (ko) 2013-05-13 2016-04-15 인텔 코포레이션 패키지 어셈블리, 집적 회로 패키지 어셈블리의 제조 방법 및 컴퓨팅 디바이스
US11063127B2 (en) 2018-11-05 2021-07-13 Rohm Co., Ltd. Semiconductor element and semiconductor device provided with the same

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8502372B2 (en) 2010-08-26 2013-08-06 Lsi Corporation Low-cost 3D face-to-face out assembly
JP2012059738A (ja) * 2010-09-03 2012-03-22 Toshiba Corp 半導体装置
JP2014049733A (ja) * 2012-09-04 2014-03-17 Fujitsu Semiconductor Ltd 半導体装置及び半導体装置の製造方法
JP6125209B2 (ja) * 2012-11-19 2017-05-10 株式会社ジェイデバイス 半導体装置及びその製造方法
US9497861B2 (en) 2012-12-06 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for package with interposers
KR102053349B1 (ko) 2013-05-16 2019-12-06 삼성전자주식회사 반도체 패키지
GB2514547A (en) * 2013-05-23 2014-12-03 Melexis Technologies Nv Packaging of semiconductor devices
US10020236B2 (en) * 2014-03-14 2018-07-10 Taiwan Semiconductar Manufacturing Campany Dam for three-dimensional integrated circuit
TW201806104A (zh) * 2016-08-10 2018-02-16 南茂科技股份有限公司 半導體封裝
US11676929B2 (en) 2016-10-21 2023-06-13 Sony Semiconductor Solutions Corporation Electronic substrate and electronic apparatus
US10910289B2 (en) * 2016-10-21 2021-02-02 Sony Semiconductor Solutions Corporation Electronic substrate and electronic apparatus
US11282717B2 (en) 2018-03-30 2022-03-22 Intel Corporation Micro-electronic package with substrate protrusion to facilitate dispense of underfill between a narrow die-to-die gap
US10529637B1 (en) 2018-10-31 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method of forming same
FR3126258B1 (fr) * 2021-08-20 2024-10-04 Stmicroelectronics Crolles 2 Sas Structure d'interconnexion d’un circuit intégré

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4832996A (en) * 1988-02-24 1989-05-23 Motorola, Inc. Semiconductor die for plastic encapsulation having an adhesion promoter
WO2005048348A1 (en) * 2003-11-10 2005-05-26 Henkel Corporation Electronic packaging materials for use with low-k dielectric-containing semiconductor devices

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