CN103650135B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN103650135B
CN103650135B CN201280033924.0A CN201280033924A CN103650135B CN 103650135 B CN103650135 B CN 103650135B CN 201280033924 A CN201280033924 A CN 201280033924A CN 103650135 B CN103650135 B CN 103650135B
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semiconductor chip
electrode
extended type
chip
extension
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CN103650135A (zh
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岩濑铁平
萩原清己
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

半导体装置(1)具备：第1半导体芯片(2)，其在表面形成第1电极(21)；和扩展型半导体芯片(3)，其具有第2半导体芯片(31)以及从该第2半导体芯片的至少1个侧面起形成于外方的树脂扩展部(33)，且在表面形成第2电极(35)。第1半导体芯片和扩展型半导体芯片使第1电极以及第2电极的形成面彼此对置来相互连接第1电极和第2电极。扩展型半导体芯片中的第2电极当中的与第1电极连接第2电极仅形成于树脂扩展部上。

Description

半导体装置
技术领域
本发明涉及扩展型半导体芯片以及半导体装置，特别涉及具有倒装安装的扩展型半导体芯片的半导体装置。
背景技术
在数字电视以及数字录像机等的系统中，伴随高功能化而处置的数据量飞跃性增加。为此，在搭载于系统的半导体存储器装置中，要求容量的增加和高的数据传输速率。
作为搭载这样的半导体存储器装置的半导体装置，有将安装存储器控制器的逻辑电路和存储器电路集成在1个芯片中的系统级芯片(System on Chip：SoC)、和安装有存储器控制器的逻辑电路芯片和存储器电路芯片进行层叠并收容到1个封装中的系统级封装(System in Package：SiP)。
当前，使用制造成本比较低的SiP的系统有增加的倾向。在采用SiP构造的半导体装置中，在电连接被层叠的逻辑电路芯片与存储器电路芯片间的方法中，有使用如下技术的方法：使逻辑电路芯片的元件形成面与存储器芯片的元件形成面对置，并介由由软钎焊材料等构成的金属突起(隆起焊盘)来直接连接各个电极彼此的叠层芯片(Chip on Chip：CoC)技术。由此，谋取数据传输速率的提升(例如参照专利文献1)。
现有技术文献
专利文献
专利文献1：JP特开2010-141080号公报
发明的概要
发明要解决的课题
随着半导体装置的小型化的进展，包含于逻辑电路芯片的有源元件(特别是晶体管)越来越微细化。晶体管的电气特性易于受到半导体芯片的封装时产生的热应力的影响，例如在CoC连接半导体芯片的情况下，软钎焊材料等的接合材熔融，之后，由于凝固时产生的半导体芯片的元件形成面的残留应力而使得晶体管的源极漏极电流较大地变动。另外，在用于半导体芯片的多层布线层中的绝缘材料中，应对晶体管的微细化而是使用被称作Low-k材料的低介电常数材料。Low-k材料一般机械强度较低，由于封装时对半导体芯片的元件形成面的应力，而会在由Low-k材料构成的绝缘层产生裂纹，或者在与接近的其它的布线材料的界面或其附近产生剥离。
发明内容
本发明目的在于解决所述的问题，能防止在半导体芯片的封装时产生的热应力给包含于该半导体芯片的有源元件等的电气特性带来的影响以及构成材料的物理损伤。
用于解决课题的手段
为了达到所述目的，本发明构成为：在至少1个半导体芯片中的1个侧面上设置从半导体芯片的侧面起形成于外方的扩展部，在该扩展部上形成构成与外部电连接的电极。
具体地，本发明所涉及的第1半导体装置具备：第1半导体芯片，其在表面形成第1电极；和扩展型半导体芯片，其具有第2半导体芯片以及从该第2半导体芯片的至少1个侧面起形成于外方的扩展部，且在表面形成第2电极，第1半导体芯片和扩展型半导体芯片使第1电极以及第2电极的形成面彼此对置来相互连接第1电极第2电极，扩展型半导体芯片中的第2电极当中的与第1电极连接的第2电极仅形成于扩展部上。
根据本发明的第1半导体装置，扩展型半导体芯片中的第2电极当中的与第1电极连接的第2电极仅形成于扩展部上。由此，在构成扩展型半导体芯片的第2半导体芯片的元件形成面上不存在与第1半导体芯片电连接的第2电极。因此，能避免封装时产生的热应力的影响。
在本发明的第1半导体装置中，也可以第2半导体芯片为多个半导体芯片，扩展型半导体芯片的扩展部形成于第2半导体芯片中的相互相邻的侧面彼此间。
另外，在本发明的第1半导体装置中，也可以扩展型半导体芯片的扩展部形成于第2半导体芯片的周围。
在本发明的第1半导体装置中，也可以在扩展型半导体芯片形成布线，该布线连接形成于扩展部的表面的第2电极和形成于第2半导体芯片的元件形成面上的第3电极。
在本发明的第1半导体装置中，也可以在扩展部，在与第1半导体芯片对置的区域形成贯通孔，在第1半导体芯片与扩展型半导体芯片间包括贯通孔在内填充了密封用树脂材料。
本发明所涉及的第2半导体装置具备：布线基板，其在表面形成第1电极；和扩展型半导体芯片，其具有半导体芯片以及从该半导体芯片的至少1个侧面起形成于外方的扩展部，且在表面形成第2电极，布线基板和扩展型半导体芯片使第1电极以及第2电极的形成面彼此对置来相互连接第1电极和第2电极，扩展型半导体芯片中的第2电极当中的与第1电极连接的第2电极仅形成于扩展部上。
根据本发明的第2半导体装置，扩展型半导体芯片中的第2电极当中的与第1电极连接的第2电极仅形成于扩展部上。由此，在构成扩展型半导体芯片的第2半导体芯片的元件形成面上不存在与布线基板电连接的第2电极。因此，能避免在封装时产生的热应力的影响。
在本发明的第2半导体装置中，也可以半导体芯片为多个半导体芯片，扩展型半导体芯片的扩展部形成于半导体芯片中的相互相邻的侧面彼此间。
本发明所涉及的扩展型半导体芯片具备：多个半导体芯片；扩展部，其形成于半导体芯片中的相互相邻的侧面彼此间；和电极，其形成于扩展部上，且与外部进行电连接。
根据本发明的扩展型半导体芯片，具备形成于扩展部上、且与外部电连接的电极。由此，在半导体芯片的元件形成面上不存在与外部电连接的电极。因此，能避免在封装时产生的热应力的影响。
发明的效果
根据本发明所涉及的扩展型半导体芯片以及使用其的半导体装置，能防止在半导体芯片封装时产生的热应力给包含于该半导体芯片的有源元件等的电气特性带来的影响以及构成材料的物理损伤。
附图说明
图1(a)～图1(c)表示本发明的第1实施方式所涉及的扩展型半导体芯片以及半导体装置，图1(a)是立体图，图1(b)是俯视图，图1(c)是图1(b)的Ic-Ic线的截面图。
图2(a)～图2(c)表示比较例所涉及的半导体装置，图2(a)是立体图，图2(b)是俯视图，图2(c)是图2(b)的IIc-IIc线的截面图。
图3是表示第1实施方式的第1变形例所涉及的扩展型半导体芯片以及半导体装置的变形例的俯视图。
图4是表示第1实施方式的第2变形例所涉及的扩展型半导体芯片以及半导体装置的变形例的俯视图。
图5(a)以及图5(b)表示第1实施方式的第3变形例所涉及的半导体装置，图5(a)是俯视图，图5(b)是图5(a)的Vb-Vb线的截面图。
图6(a)以及图6(b)表示第1实施方式的第4变形例所涉及的扩展型半导体芯片以及半导体装置，图6(a)是俯视图，图6(b)是图6(a)的VIb-VIb线的截面图。
图7(a)～图7(c)表示本发明的第2实施方式所涉及的扩展型半导体芯片以及半导体装置，图7(a)是立体图，图7(b)是俯视图，图7(c)是图7(b)的VIIc-VIIc线的截面图。
具体实施方式
(第1实施方式)
参照图1(a)～图1(c)来说明本发明的第1实施方式。
如图1(a)～图1(c)所示，第1实施方式所涉及的半导体装置1例如以硅(Si)为基材，由具有晶体管以及多层布线层的第1半导体芯片2、和在上表面(元件形成面)保持第1半导体芯片2且包含多个半导体芯片31、32的扩展型半导体芯片3构成。在各半导体芯片2、31以及32中的多层布线层中，作为绝缘层例如使用Low-k材料。
在第1半导体芯片2中的与扩展型半导体芯片3的对置面且元件形成面形成由铜(Cu)、铝(Al)或镍(Ni)等金属构成的外部连接用的多个第1电极(连接盘)21。
扩展型半导体芯片3例如以硅(Si)为基材，具有分别形成晶体管以及多层布线层的第2半导体芯片31以及第3半导体芯片32。在第2半导体芯片31以及第3半导体芯片32中的相互相邻的侧面彼此间，形成填充环氧树脂材料等而成的树脂扩展部33。通过该树脂扩展部33，第2半导体芯片31以及第3半导体芯片32一体形成。另外，树脂扩展部33并不一定非得需要由树脂材料形成，也可以使陶瓷材料等绝缘体介于其间并用粘合材料来粘接。
在第2半导体芯片31上形成由Cu、Al或Ni等金属构成的多个第1芯片电极311。同样地，在第3半导体芯片32上形成由Cu、Al或Ni等金属构成的多个第2芯片电极321。在一体成形的第2半导体芯片31、第3半导体芯片32以及树脂扩展部33的上表面形成由聚酰亚胺等绝缘体构成的再布线层34。在再布线层34的内部形成由Cu或Al等构成的多个布线341。另外，在再布线层34上形成由Cu、Al或Ni等金属构成的外部连接用的多个第2电极(连接盘)35。各布线341的一端与第1芯片电极311以及第2芯片电极321的任一者电连接，另外，其另一端与再布线层34上的第2电极35的任一者电连接。
第1半导体芯片2中的多个第1电极21、和扩展型半导体芯片3中的多个第2电极35相互对置配置。在各个相互对置的第1电极21和第2电极35间使由软钎焊材料或金等构成的金属突起(隆起焊盘)4介于其间而电连接。
在此，作为第1实施方式的特征，形成于扩展型半导体芯片3的上表面的多个第2电极35其全部都形成在树脂扩展部33的正上方。另外，在再布线层34上的不与第1半导体芯片2对置的区域，即使在半导体芯片31、32的元件形成面的上侧的区域形成例如检查用的电极(未图示)等也没关系。
如图1(b)所示，在第1实施方式中，多个第1电极21在第1半导体芯片2的大致中央部，进行Y方向的排列数大于X方向的排列数的矩阵状配置。因此，扩展型半导体芯片3的树脂扩展部33在第2半导体芯片31与第3半导体芯片32间以Y方向的长度长于X方向的长度的方式形成，以使得能对应于第1半导体芯片2的各第1电极21的配置来分别配置扩展型半导体芯片3的各第2电极35。
在本申请说明书中，所谓芯片的中央部，表示第1电极21的配置区域相对于第1半导体芯片2的外形的相对位置关系。具体地，在将从半导体芯片的中心到一角部为止的距离设为D的情况下，定义为从半导体芯片的中心起D/2以下的范围。
在图1(a)以及图1(b)中，示意地以2行10列来表示了第1电极21的排列，但在实际的半导体装置中，考虑更多的配置。具体地，在X方向为约10行左右，且在Y方向为约100列左右。另外，想定将第1电极21彼此的间隔设为40μm～50μm左右的排列。
下面，说明能通过前述那样构成的半导体装置1来避免封装第1半导体芯片2和扩展型半导体芯片3时产生的热应力给各半导体芯片的晶体管的电气特性带来的影响以及在包含于各半导体芯片2、3的多层布线层中的由Low-k材料构成的绝缘层产生的裂纹或剥离等物理损伤的理由。在此，将图2所示的半导体装置5设为比较例。另外，对与图1所示的构成部件相同的构成部件赋予相同的符号。构成图2所示的比较例所涉及的半导体发光装置5的第2半导体芯片31是单体的芯片，不具有树脂扩展部。因此，第2半导体芯片31的第1芯片电极311、与第1半导体芯片2的第1电极21通过金属突起4直接连接。
在CoC连接的代表性的方法即软钎焊连接法中，使预先在电极上载置软钎焊材料的半导体芯片彼此对置并粘合，通过加热使软钎焊材料熔融，之后，冷却软钎焊材料来使其固化，由此进行连接。在图2所示的比较例的情况下，相对于熔融的软钎焊材料的凝固以及冷却时的收缩，由于各半导体芯片2、31以刚性高且线膨胀系数低的硅(Si)为基材，因此不能吸收应力引起的变形。由此，各半导体芯片2、31的各元件形成面会有应力残留下来。形成于元件形成面的晶体管易于受到该应力的影响，由于残留应力而导致源极-漏极电流较大地变动。另外，形成于元件形成面的由Low-k材料构成的绝缘层有可能由于残留应力的影响而产生裂纹，或进一步在界面或其附近剥落。
与此相对，如图1(c)所示，第1实施方式所涉及的半导体装置1在扩展型半导体芯片3，仅在介由金属突起4与第1半导体芯片2接合的区域形成刚性低且线膨胀系数与软钎焊材料等金属突起4比较接近的树脂扩展部33。由此，第1半导体芯片2的元件形成面中的残留应力变小。另外，在构成扩展型半导体芯片3的第2半导体芯片31以及第3半导体芯片32的各元件形成面上，由于不存在金属突起4自身，因此能避免金属突起4引起的残留应力的影响。
如第1实施方式那样，在包含多个半导体芯片(第2半导体芯片31以及第3半导体芯片32)的扩展型半导体芯片3上搭载第1半导体芯片2的构成，在例如第1半导体芯片2的连接盘偏向元件形成面的特定部分而配置的情况下，也能将第2半导体芯片31以及第3半导体芯片32的连接盘引出到树脂扩展部33上，与第1半导体芯片2的连接盘对应地来配置连接盘。例如，在第1半导体芯片2是在元件形成面的中央部分集中形成连接盘的存储器芯片的情况下，能将多个半导体芯片的连接盘聚合在树脂扩展部33上，使存储器芯片的连接盘与树脂扩展部33的连接盘对置来搭载。由此，由于不再需要准备配合下侧的多个芯片的连接盘的配置的具有特殊的连接盘配置的存储器芯片，因此能使用通用存储器。
在第1实施方式中，如前述那样，进行矩形状配置，以使得第1半导体芯片2的第1电极21与扩展型半导体芯片3的第2电极35相互连接的位置位于第1半导体芯片2的大致中央部，且Y方向的排列数多于X方向的排列数。由此，使扩展型半导体芯片3由2个半导体芯片31、32构成，并使树脂扩展部33形成为在各半导体芯片31、32彼此间在Y方向上变长。但树脂扩展部33的平面形状并不限于图1(b)的形状，而能对应于第1半导体芯片2的第1电极21的配置位置进行各种变更。
下面，参照图3～图6来说明第1实施方式的变形例。
(第1实施方式的第1变形例)
图3表示第1实施方式的第1变形例所涉及的半导体装置的平面构成。如图3所示，第1变形例所涉及的半导体装置1配置为：第1半导体芯片2的多个第1电极21在该第1半导体芯片2的大致中央部，配置成在Y方向上呈长矩阵状，且X方向的间隔比较大。在如此地配置多个第1电极21的情况下，使扩展型半导体芯片3由第2半导体芯片31、第3半导体芯片32以及第4半导体芯片36这3个芯片。因此，例如，配置成：在第2半导体芯片31与第3半导体芯片32间夹着第4半导体芯片36。
进而，在第2半导体芯片31与第4半导体芯片36间、以及第3半导体芯片32与第4半导体芯片36间分别一体形成树脂扩展部33，并在各树脂扩展部33上与各第1电极21对置地分别形成扩展型半导体芯片3的第2电极(未图示)。
(第1实施方式的第2变形例)
图4表示第1实施方式的第2变形例所涉及的半导体装置的平面构成。如图4所示，第2变形例所涉及的半导体装置1中，第1半导体芯片2的多个第1电极21在该第1半导体芯片2的大致中央部集中地配置成平面十字状。在如此配置多个第1电极21的情况下，能使扩展型半导体芯片3由第2半导体芯片31、第3半导体芯片32、第4半导体芯片36以及第5半导体芯片37这4个芯片构成。因此，例如将各半导体芯片31、32、36以及37配置为2行2列，在其对置的侧面彼此间配置树脂扩展部33。
作为一例，在第2半导体芯片31与第3半导体芯片32间、第3半导体芯片32与第5半导体芯片37间、第5半导体芯片37与第4半导体芯片36间、以及第4半导体芯片36与第2半导体芯片31间分别一体形成树脂扩展部33，并在树脂扩展部33上与各第1电极21对置地分别形成扩展型半导体芯片3的第2电极(未图示)。
(第1实施方式的第3变形例)
图5(a)以及图5(b)表示第1实施方式的第3变形例所涉及的半导体装置的平面构成以及断面构成。如图5(a)所示，在第3变形例所涉及的半导体装置1中，第1半导体芯片2的多个第1电极21在该第1半导体芯片2的对置的2个侧部的附近一列一列地配置。在如此配置多个第1电极21的情况下，仅在第2半导体芯片31形成扩展型半导体芯片3。进而，在第2半导体芯片31的4个侧面的全部即第2半导体芯片31的周围设置树脂扩展部33，与第2半导体芯片31一体形成。进而，在树脂扩展部33上与各第1电极21对置地分别形成扩展型半导体芯片3的第2电极35。
(第1实施方式的第4变形例)
图6(a)以及图6(b)表示第1实施方式的第4变形例所涉及的半导体装置的平面构成以及断面构成。如图6(a)以及图6(b)所示，第4变形例所涉及的半导体装置1作为一例，与图4所示的第2变形例所涉及的半导体装置1同样地，都使扩展型半导体芯片3由4个半导体芯片31、32、36以及37构成。
第4变形例与第2变形例的相异点在于，在构成扩展型半导体芯片3的树脂扩展部33设置了与第1半导体芯片2对置且在未形成金属突起4的区域贯通树脂扩展部33的贯通孔33a。
具体地，如图6(a)所示，在形成为平面十字状的树脂扩展部33中的第1半导体芯片2的多个第1电极21的外侧且第1半导体芯片2的轮廓线(全侧面)的内侧的区域，设置了在表背方向上贯通树脂扩展部33以及再布线层34的多个贯通孔33a。
在通过金属突起4连接了第1半导体芯片2和扩展型半导体芯片3后，进一步在第1半导体芯片2与扩展型半导体芯片3间注入密封用树脂材料即底部填充材料6。此时，在金属突起4的高度较小的情况下，在从第1半导体芯片2的侧面注入底部填充材料6这样的现有一般方法中，底部填充材料6的填充性变得不充分。由此，在金属突起4的周边有可能产生空隙。
但是，在第4变形例中，在进行基于金属突起4的连接后，从扩展型半导体芯片3的背面通过预先设置的多个贯通孔33a将底部填充材料6直接注入到更靠近金属突起4的位置。由此，对于各金属突起4的周边区域，能提高底部填充材料6的填充性。
另外，设于树脂扩展部33以及再布线层34的贯通孔33a的个数，根据各半导体芯片2、3的大小以及个数来进行適宜调整即可。另外，设置贯通孔33a的第4变形例也能应用于第1实施方式、其第1变形例以及第3变形例所涉及的半导体装置1中。
(第2实施方式)
下面，参照图7(a)～图7(c)来说明本发明的第2实施方式。
如图7(a)～图7(c)所示第2实施方式所涉及的半导体装置7例如以硅(Si)为基材，由包含分别具有晶体管以及多层布线层的第1半导体芯片81以及第2半导体芯片82的扩展型半导体芯片8、和在上表面保持扩展型半导体芯片的以环氧树脂材料等为基材的树脂基板(布线基板)9构成。在各半导体芯片81以及82中的多层布线层，作为绝缘层例如使用Low-k材料。
在扩展型半导体芯片8中的第1半导体芯片81以及第2半导体芯片82的相互相邻的侧面彼此间填充由环氧树脂材料等构成的树脂扩展部83。通过该树脂扩展部83来一体形成第1半导体芯片81以及第2半导体芯片82。
在第1半导体芯片81中的与树脂基板9的对置面且元件形成面形成由铜(Cu)、铝(Al)或镍(Ni)等金属构成的多个第1芯片电极811。同样地，在第2半导体芯片82的元件形成面形成由Cu、Al或Ni等金属构成的多个第2芯片电极821。在一体成形的第1半导体芯片81、第2半导体芯片82以及树脂扩展部83上形成由聚酰亚胺等绝缘体构成的再布线层84。在再布线层84的内部形成由Cu或Al等构成的多个布线841。另外，在再布线层84上形成由Cu、Al或Ni等金属构成的外部连接用的多个第1电极(连接盘)85。各布线841的一端与第1芯片电极811以及第2芯片电极821任一者电连接，另外，其另一端与再布线层84上的第1电极85的任一者电连接。
另外，在树脂基板9上，在与扩展型半导体芯片8的第1电极85对置的位置形成多个第2电极(连接盘)91。在各个相互对置的第1电极85和第2电极91间使由软钎焊材料或金等构成的金属突起(隆起焊盘)4介于其间来电连接。
在此，作为第2实施方式的特征，形成于扩展型半导体芯片8的元件形成面侧的多个第1电极85其全部都形成于树脂扩展部83的正上方。另外，在再布线层84上不与树脂基板9的第2电极91对置的区域，在半导体芯片31、32的元件形成面的上侧的区域形成例如检查用的电极(未图示)等也没关系。
如图7(b)所示，在第2实施方式中，多个第2电极91在树脂基板9的大致中央部配置为：Y方向的排列数大于X方向的排列数的矩阵状。因此，扩展型半导体芯片8的树脂扩展部83能在第1半导体芯片81与第2半导体芯片82间形成为Y方向的长度长于X方向的长度，以使得能对应于树脂基板9的各第2电极91的配置来分别配置扩展型半导体芯片8的各第1电极85。
在图7(a)以及图7(b)中，示意地以2行10列来表示了第2电极91的排列，但在实际的半导体装置中，要考虑更多的配置。具体地，在X方向为约10行左右，且在Y方向为约100列左右。另外，想定将第1电极21彼此的间隔设为40μm～50μm左右的排列。
但是，树脂扩展部83的平面形状并不限于图7(b)的形状，能根据树脂基板9的第2电极91的配置位置进行各种变更。
根据第2实施方式所涉及的半导体装置7，能避免扩展型半导体芯片8的封装时产生的热应力对各半导体芯片81、82的晶体管的电气特性带来的影响以及在由Low-k材料构成的绝缘层产生的裂纹或剥离等物理损伤。
即，与第1实施方式相同，在构成扩展型半导体芯片8的第1半导体芯片81以及第2半导体芯片82的各元件形成面上，由于不存在被称作隆起焊盘的金属突起4自身，因此树脂基板9的收缩、金属突起4的凝固以及冷却收缩等的影响不会传递到元件形成面。因此，能避免这些树脂基板9以及金属突起4的残留应力带来的影响。
产业上的利用可能性
本发明所涉及的扩展型半导体芯片以及半导体装置能防止在半导体芯片的封装时产生的热应力给有源元件等的电气特性带来的影响以及构成材料的物理损伤，特别在具有倒装安装的扩展型半导体芯片的半导体装置等中有用。
符号的说明
1 半导体装置
2 第1半导体芯片
21 第1电极
3 扩展型半导体芯片
31 第2半导体芯片
32 第3半导体芯片
311 第1芯片电极
321 第2芯片电极
33 树脂扩展部
33a 贯通孔
34 再布线层
341 布线
35 第2电极
36 第3半导体芯片
37 第4半导体芯片
4 金属突起
5 半导体装置
6 底部填充材料
7 半导体装置
8 扩展型半导体芯片
81 第1半导体芯片
82 第2半导体芯片
811 第1芯片电极
821 第2芯片电极
83 树脂扩展部
84 再布线层
841 布线
85 第1电极
9 树脂基板
91 第2电极

Claims (7)

1.一种半导体装置，具备：
第1半导体芯片，在其元件形成面形成第1电极；和
扩展型半导体芯片，具有第2半导体芯片以及从该第2半导体芯片的至少1个侧面起形成于外方的扩展部，且在其元件形成面形成第2电极，
所述第1半导体芯片和所述扩展型半导体芯片使所述第1半导体芯片的元件形成面与所述扩展型半导体芯片的元件形成面彼此对置来相互连接所述第1电极和所述第2电极，
所述扩展型半导体芯片中的所述第2电极当中的与所述第1电极连接的第2电极仅形成于所述扩展部上。
2.根据权利要求1所述的半导体装置，其中，
所述第2半导体芯片是多个半导体芯片，
所述扩展型半导体芯片的所述扩展部形成于所述第2半导体芯片中的相互相邻的侧面彼此间。
3.根据权利要求1所述的半导体装置，其中，
所述扩展型半导体芯片的所述扩展部形成于所述第2半导体芯片的周围。
4.根据权利要求1～3中任一项所述的半导体装置，其中，
在所述扩展型半导体芯片形成布线，该布线连接形成于所述扩展部的表面的所述第2电极和形成于所述第2半导体芯片的元件形成面上的第3电极。
5.根据权利要求1～3中任一项所述的半导体装置，其中，
在所述扩展部，在与所述第1半导体芯片对置的区域形成贯通孔，
在所述第1半导体芯片与所述扩展型半导体芯片间，包括所述贯通孔在内填充了密封用树脂材料。
6.一种半导体装置，具备：
布线基板，其在表面形成第1电极；和
扩展型半导体芯片，其具有半导体芯片以及从该半导体芯片的至少1个侧面起形成于外方的扩展部，且在表面形成第2电极，
所述布线基板和所述扩展型半导体芯片使所述第1电极以及第2电极的形成面彼此对置来相互连接所述第1电极和所述第2电极，
所述扩展型半导体芯片中的所述半导体芯片的与所述布线基板对置的表面从所述扩展部露出，
所述扩展型半导体芯片中的所述第2电极当中的与所述第1电极连接的第2电极仅形成于所述扩展部上。
7.根据权利要求6所述的半导体装置，其中，
所述半导体芯片为多个半导体芯片，
所述扩展型半导体芯片的所述扩展部形成于所述半导体芯片中的相互相邻的侧面彼此间。
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