CN206259351U - 电子设备 - Google Patents
电子设备 Download PDFInfo
- Publication number
- CN206259351U CN206259351U CN201621496811.6U CN201621496811U CN206259351U CN 206259351 U CN206259351 U CN 206259351U CN 201621496811 U CN201621496811 U CN 201621496811U CN 206259351 U CN206259351 U CN 206259351U
- Authority
- CN
- China
- Prior art keywords
- chip
- network
- carrier substrate
- back side
- electrical connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
- H01L2224/1712—Layout
- H01L2224/1713—Square or rectangular array
- H01L2224/17134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/17136—Covering only the central area of the surface to be connected, i.e. central arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
- H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/17181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73207—Bump and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73257—Bump and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06506—Wire or wire-like electrical connections between devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15182—Fan-in arrangement of the internal vias
- H01L2924/15184—Fan-in arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
本公开涉及一种电子设备,具体为一种具有堆叠电子芯片的电子设备,包含:载体基板(2);至少第一电子芯片(4)和第二芯片(15);其中第一芯片(4)安装在载体基板(2)上,经由插入的电连接元件(14)将第一芯片的正面电连接网络(8)与载体基板的电连接网络(3)进行连接;第二芯片(15)安装在第一芯片上,经由插入的电连接元件(21)将第二芯片的正面电连接网络(19)与第一芯片的背面电连接网络(11)进行连接;并且电连接线(22)将第一芯片的背面电连接网络与载体基板的电连接网络进行连接。
Description
技术领域
本实用新型涉及电子设备,具体为包含堆叠电子芯片的电子设备领域。
背景技术
目前,在电子设备领域中,电子设备包含载体基板、安装在该载体基板顶部的第一电子芯片和安装在该第一芯片顶部的第二电子芯片,第二芯片与载体基板之间的电连接通过使用俗称为TSV的电连接通孔的第一芯片来实现。
然而,制造这类通孔耗时、困难,因而成本高,因为需要多种操作,特别是需要对第一芯片的半导体基板进行钻孔和减薄,结合该半导体基板正面上的集成电路和包含正面电连接网络的层的生产。
实用新型内容
提出一种电子设备,包含:载体基板,设置有电连接网络;至少第一电子芯片,其在第一侧上设置有集成电路和包含正面电连接网络并具有正面的层,并且在与第一侧相反的第二侧上设置有包含背面电连接网络并具有背面的层,以及至少第二电子芯片,其在第一侧上设置有集成电路和包含正面电连接网络并具有正面的层。
第一芯片安装在载体基板的某一位置上,使得其正面面对载体基板的一个面,并且经由插入的电连接元件,将第一芯片的正面电连接网络与载体基板的电连接网络进行连接。
第二芯片安装在第一芯片的某一位置上,使得其正面面对第一芯片的背面,并且经由插入的电连接元件,将第二芯片的正面电连接网络与第一芯片的背面电连接网络进行连接。
电连接线将第一芯片的背面电连接网络的背面焊盘与载体基板的电连接网络的焊盘进行连接,第一芯片的焊盘布置在第一芯片的背面的没有被第二芯片覆盖的区域上,载体基板的焊盘布置在载体基板没有被第一芯片覆盖的区域上。
因此,第一芯片的背面电连接网络形成了用于在外周重新分配第二芯片正面焊盘的方法,由此允许对第二芯片更高密度的电连接,这并不取决于第一芯片的内部结构。
载体基板的没有被第一芯片覆盖的所述区域可围绕第一芯片的整个外周延伸。
第一芯片的没有被第二芯片覆盖的所述区域可围绕第二芯片的整个外周延伸。
电连接线可远离第一芯片的外周伸出一段距离。
电连接线嵌入在封装块中。
外部电连接元件可布置在载体基板的与支承第一芯片的面相对的一个面上,并连接至载体基板的电连接网络。
附图说明
下文将通过非限制性示例实施例来描述该电子设备,其截面示出在图1中。
具体实施方式
附图中所示的电子设备1包含设置有集成电连接网络3的载体基板2,例如包含多个彼此连接的集成金属电连接层级的多层基板。
电子设备1包含第一电子芯片4,在其第一侧上设置有半导体基板5,集成电路6和包含正面电连接网络8并具有正面9的正面层7。
第一电子芯片4还在与第一侧相反的第二侧上设置有包含背面电连接网络11并具有背面12的层10。该背面电连接网络11例如可以在金属层级中制造。
第一芯片4安装在载体基板2的某一位置上,使得其正面9朝向载体基板2的面13,并且经由多个插入的电连接元件14。这些电连接元件14将载体基板2的电连接网络3的焊盘与第一芯片4的正面电连接网络8的正面焊盘进行连接。这些电连接元件14可以例如包含金属球,本领域技术人员称为“倒装焊球”(或“倒装焊”),或铜柱。
电子设备1包含第一电子芯片15,在其第一侧上设置有半导体基板16,集成电路17和包含正面电连接网络19并具有正面20的正面层18。
第二芯片15安装在第一芯片4的某一位置上,使得其正面20朝向第一芯片4的背面12,并且经由多个插入的电连接元件21。这些电连接元件21将第一芯片4的背面电连接网络11的背面焊盘与第二芯片15的正面电连接网络19的正面焊盘进行连接。这些电连接元件21可以例如包含金属球,本领域技术人员称为“倒装焊球”(或“倒装焊”),或铜柱。
第一芯片4没有覆盖载体基板2的整个表面13。有利地,第一芯片4留下载体基板2的面13的围绕该第一芯片4的整个外周延伸的区域没有被覆盖。
第二芯片15没有覆盖第一芯片4的整个背面12。有利地,第二芯片15留下第一芯片4的背面13的围绕该第二芯片15的整个外周延伸的区域没有被覆盖,第二芯片15的表面区域小于第一芯片4的表面区域。
电子设备1包含多个电连接线22,其远离第一芯片4的外周伸出一段距离,并且一方面连接第一芯片4的背面电连接网络11的背面焊盘11a,另一方面连接载体基板2的电连接网络3的焊盘3a,第一芯片的焊盘布置在第一芯片4的背面12的没有被第二芯片15覆盖的区域上,载体基板2的焊盘布置在载体基板2的没有被第一芯片4覆盖的区域上。电连接线22可按行或多个错开的行布置。
需要注意电连接网络3在第一芯片4的下方延伸以便连接至连接元件14,并且在所述未被覆盖的区域内超出第一芯片4的外周延伸,以便连接至电连接线22。
还需要注意第一芯片4的背面电连接网络11在第二芯片15的下方延伸以便连接至连接元件21,并且在所述未被覆盖的区域内超出第二芯片15的外周延伸以便连接至电连接线22。
有益地,电连接线22可在第二芯片15被放置就位之前或之后通过通常在微电子领域中使用的焊线机放置就位。
电子设备1包含布置在载体基板2的面13上的封装块23,并且在其内部嵌入有芯片4和15以及电连接线22,这样电子设备1便具有平行六面体的形状。
在一个变形实施例中,封装块23为水珠状,其中嵌入有电连接线22,该水珠阻塞了载体基板2与第一芯片4之间的空间外周以及第一芯片4与第二芯片15之间的空间外周。
电子设备1包含多个外部电连接元件24,如金属球,其布置在载体基板2的与其面13相对的面25上,并且连接至电连接网络3。该多个外部电连接元件24被本领域技术人员称为“球栅阵列”(BGA)。
因此,电连接网络11和电连接线可以允许第二芯片15电连接至外部电连接球和/或连接至第一芯片4,用于交换信号和/或电力。
根据一个具体的应用,第一芯片4和第二芯片15可以是需要高度互连密度的芯片(电连接元件14和21),这就不需要在芯片的正面通过外周的焊盘来焊线。由于第二芯片15的尺寸小于第一芯片4,因此第一芯片4的背面可包含一个或多个背面电互连层级11,形成第二芯片15的电连接元件21的外周扇出,允许第二芯片15通过电线电连接至第一芯片4和基板2,并因此使得成本低于硅通孔(TSV)。
根据一个变形实施例,多个第二芯片15可以安装在第一芯片4背面的顶部上,经由连接至第一芯片4的背面电连接网络11的相应电连接元件21。有利地,第一芯片4的背面电连接网络11还可用来将多个第二芯片15彼此电连接。
Claims (6)
1.一种电子设备,其特征在于,包含:
载体基板(2),设置有电连接网络(3);
至少第一电子芯片(4),其在第一侧上设置有集成电路和包含正面电连接网络(8)并具有正面(9)的层,并且在与所述第一侧相反的第二侧上设置有包含背面电连接网络(11)并具有背面(12)的层,以及
至少第二电子芯片(15),其在第一侧上设置有集成电路和包含正面电连接网络(19)并具有正面(20)的层;
设备,在该设备中:
第一芯片(4)安装在所述载体基板(2)的某一位置,使得其正面面对所述载体基板的一个面,并且经由插入的电连接元件(14),将所述第一芯片的正面电连接网络(8)与所述载体基板的电连接网络(3)进行连接;
第二芯片(15)安装在所述第一芯片的某一位置,使得其正面面对所述第一芯片的背面,并且经由插入的电连接元件(21),将所述第二芯片的正面电连接网络(19)与所述第一芯片的背面电连接网络(11)进行连接;并且
电连接线(22)将所述第一芯片的背面电连接网络的背面焊盘(11a)与所述载体基板的电连接网络的焊盘(3a)进行连接,第一芯片的焊盘布置在第一芯片的背面的没有被第二芯片覆盖的区域上,所述载体基板的焊盘布置在所述载体基板的没有被第一芯片覆盖的区域上。
2.根据权利要求1所述的设备,其特征在于,所述载体基板的没有被第一芯片覆盖的所述区域围绕所述第一芯片的整个外周延伸。
3.根据权利要求1或2所述的设备,其特征在于,所述第一芯片的没有被所述第二芯片覆盖的所述区域围绕所述第二芯片的整个外周延伸。
4.根据权利要求1或2所述的设备,其特征在于,所述电连接线(22)远离第一芯片的外周伸出一段距离。
5.根据权利要求1或2所述的设备,其特征在于,包含所述电连接线嵌入在其中的封装块(23)。
6.根据权利要求1或2所述的设备,其特征在于,包含外部电连接元件(24),位于所述载体基板的与支承所述第一芯片的面相对的一个面上,并连接至所述载体基板(2)的电连接网络。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1654746A FR3051974A1 (fr) | 2016-05-26 | 2016-05-26 | Dispositif electronique a puces electroniques empilees |
FR1654746 | 2016-05-26 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN206259351U true CN206259351U (zh) | 2017-06-16 |
Family
ID=56322232
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201621496811.6U Expired - Fee Related CN206259351U (zh) | 2016-05-26 | 2016-11-29 | 电子设备 |
CN201611272842.8A Pending CN107437540A (zh) | 2016-05-26 | 2016-11-29 | 具有堆叠电子芯片的电子设备 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201611272842.8A Pending CN107437540A (zh) | 2016-05-26 | 2016-11-29 | 具有堆叠电子芯片的电子设备 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20170345796A1 (zh) |
CN (2) | CN206259351U (zh) |
FR (1) | FR3051974A1 (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10978426B2 (en) * | 2018-12-31 | 2021-04-13 | Micron Technology, Inc. | Semiconductor packages with pass-through clock traces and associated systems and methods |
US11456289B2 (en) | 2019-12-27 | 2022-09-27 | Micron Technology, Inc. | Face-to-face semiconductor device with fan-out porch |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001223326A (ja) * | 2000-02-09 | 2001-08-17 | Hitachi Ltd | 半導体装置 |
DE102004038989A1 (de) * | 2004-08-10 | 2005-12-29 | Infineon Technologies Ag | Halbleitermodul mit einem internen Halbleiterchipstapel und Verfahren zur Herstellung desselben |
US7696629B2 (en) * | 2007-04-30 | 2010-04-13 | Chipmos Technology Inc. | Chip-stacked package structure |
US8471376B1 (en) * | 2009-05-06 | 2013-06-25 | Marvell International Ltd. | Integrated circuit packaging configurations |
EP2309536A1 (fr) * | 2009-10-08 | 2011-04-13 | STmicroelectronics SA | Assemblage de puces ou tranches semiconductrices par diffusion du matériau des plots de connexion dans un diélectrique claqué |
-
2016
- 2016-05-26 FR FR1654746A patent/FR3051974A1/fr active Pending
- 2016-11-29 CN CN201621496811.6U patent/CN206259351U/zh not_active Expired - Fee Related
- 2016-11-29 CN CN201611272842.8A patent/CN107437540A/zh active Pending
- 2016-12-27 US US15/391,211 patent/US20170345796A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
FR3051974A1 (fr) | 2017-12-01 |
CN107437540A (zh) | 2017-12-05 |
US20170345796A1 (en) | 2017-11-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9653427B2 (en) | Integrated circuit package with probe pad structure | |
US7687899B1 (en) | Dual laminate package structure with embedded elements | |
US7598617B2 (en) | Stack package utilizing through vias and re-distribution lines | |
US8729690B2 (en) | Assembly having stacked die mounted on substrate | |
US8174105B2 (en) | Stacked semiconductor package having discrete components | |
US7829990B1 (en) | Stackable semiconductor package including laminate interposer | |
CN105742262B (zh) | 半导体封装及其制造方法 | |
JP2013175772A (ja) | シリコン貫通ビアのブリッジする相互接続 | |
CN104064551A (zh) | 一种芯片堆叠封装结构和电子设备 | |
KR101522770B1 (ko) | 패키지 정렬 구조물 및 패키지 정렬 구조물의 형성 방법 | |
CN103258818A (zh) | 用于细小间距pop结构的系统和方法 | |
US7652361B1 (en) | Land patterns for a semiconductor stacking structure and method therefor | |
CN108807361B (zh) | 一种芯片堆栈立体封装结构 | |
KR101123804B1 (ko) | 반도체 칩 및 이를 갖는 적층 반도체 패키지 | |
KR101227078B1 (ko) | 반도체 패키지 및 그 형성방법 | |
CN206259351U (zh) | 电子设备 | |
CN101118901B (zh) | 堆叠式芯片封装结构及其制程 | |
US10497655B2 (en) | Methods, circuits and systems for a package structure having wireless lateral connections | |
US20080164620A1 (en) | Multi-chip package and method of fabricating the same | |
KR20090022771A (ko) | 스택 패키지 | |
KR20090114492A (ko) | 반도체 장치 및 그 제조 방법 | |
JP2010153491A5 (ja) | 電子装置及びその製造方法、並びに半導体装置 | |
US20120286409A1 (en) | Utilizing a jumper chip in packages with long bonding wires | |
CN215220719U (zh) | 一种双面封装结构 | |
KR102549402B1 (ko) | 반도체 패키지 및 이의 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170616 Termination date: 20171129 |