TWI413232B - 多晶片封裝結構 - Google Patents

多晶片封裝結構 Download PDF

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Publication number
TWI413232B
TWI413232B TW097146817A TW97146817A TWI413232B TW I413232 B TWI413232 B TW I413232B TW 097146817 A TW097146817 A TW 097146817A TW 97146817 A TW97146817 A TW 97146817A TW I413232 B TWI413232 B TW I413232B
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wafer
package substrate
chip
electrically connected
package
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TW097146817A
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TW201023332A (en
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Chih Wei Wu
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Powertech Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Description

多晶片封裝結構
本發明是有關一種多晶片封裝結構，特別是一種封裝基板具有貫孔的多晶片封裝結構。
請參照圖1為一示意圖顯示習知之多晶片封裝結構；因應晶片設計之需求，會將第一晶片7及第二晶片8分別設置於封裝基板6之上、下表面，然而上述的晶片組在進行封裝時，就需要分別對第一晶片7及第二晶片8進行封裝，以分別形成包覆第一晶片7的第一封裝體71、及包覆第二晶片8的第二封裝體81，因而使得封裝效率降低。
因此，目前需要可一次包覆位於封裝基板6之上下表面的晶片之封裝技術，以增加封裝之效率。
本發明之目的為提供一種多晶片封裝結構，其可一次包覆位於封裝基板之上下表面的晶片，以增加封裝之效率。
依據本發明一實施例之一種多晶片封裝結構，包括一封裝基板、一第一晶片、一第二晶片、一封裝材料。封裝基板具有一上表面、一下表面、以及一貫穿上、下表面之貫孔。第一晶片設置於封裝基板之上表面，並電性連接至封裝基板。第二晶片設置於封裝基板之下表面，並電性連接至封裝基板，其中貫孔係設置於第一晶片及第二晶片之區域外。封裝材料係包覆第一晶片及第二晶片並填滿貫孔。
以下藉由具體實施例配合所附的圖式詳加說明，當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。
請參照圖2a為一示意圖顯示依據本發明一實施例之多晶片封裝結構，包括：一封裝基板1、一第一晶片2、一第二晶片3、一封裝材料4及複數個銲球14。封裝基板1具有一上表面11及一下表面12，以及一貫穿該上、下表面之貫孔13。第一晶片2設置於上表面11，並電性連接至封裝基板1；第二晶片3設置於下表面12，並電性連接至封裝基板1。封裝材料4係包覆第一晶片2及第二晶片3並填滿貫孔13。複數個銲球14係設置於封裝基板1之下表面12。
請參照圖2a及圖2b，其中圖2b為一示意圖顯示依據本發明另一實施例之多晶片封裝結構。第一晶片2與第二晶片3與封裝基板1之電性連接方式可為打線方式或是覆晶方式。詳言之，首先如圖2a所示，第一晶片2與第二晶片3與封裝基板1係以打線方式電性連接至封裝基板1。第一晶片2具有複數個第一導電接點21以複數個第一引線22電性連接至封裝基板1之複數個第一焊墊111。第二晶片3具有複數個第二導電接點31以複數個第二引線32電性連接至封裝基板1之複數個第二焊墊121。
再者，如圖2b所示，第一晶片2與第二晶片3係以覆晶方式電性連接至封裝基板1。第一晶片2之複數個第一導電接點21電性連接至封裝基板1之複數個第一導電凸塊112。第二晶片3之複數個第二導電接點31電性連接至封裝基板1之複數個第二導電凸塊122。
應註明的是貫孔13係設置於第一晶片2及第二晶片3於封裝基板1之區域外，但貫孔13之大小、形狀並無限制，舉例而言，貫孔13之形狀可為圓形、方形等，其數量可為一、二或以上。
請參照圖2a，如前所述，貫孔13係設置於第一晶片2及第二晶片3於封裝基板1之區域外，因此貫孔13之位置可位於第一晶片2與第一焊墊111之間，或是位於第一焊墊111之外。同理，貫孔13之位置可位於第二晶片3與第二焊墊121之間，或是位於第二焊墊121之外。
請參照圖3，圖3為一示意圖顯示一種多晶片封裝結構之形成，在壓模製程中，封裝材料4可藉由模具5以進行包覆第一晶片2及第二晶片3並填滿貫孔13。其中，貫孔13係貫穿封裝基板1之上、下表面。第一晶片2設置於上表面11，並電性連接至封裝基板1；第二晶片3設置於下表面12，並電性連接至封裝基板1。封裝材料4以箭頭方向流入模具5之內，並藉由流經貫孔13以一次達成包覆第一晶片2及第二晶片3。
綜合上述，本發明提供一種多晶片封裝結構，其可一次形成包覆位於封裝基板之上下表面的晶片，以增加封裝之效率。
以上所述之實施例僅是為說明本發明之技術思想及特點，其目的在使熟習此項技藝之人士能夠瞭解本發明之內容並據以實施，當不能以之限定本發明之專利範圍，即大凡依本發明所揭示之精神所作之均等變化或修飾，仍應涵蓋在本發明之專利範圍內。
1．．．封裝基板
11．．．上表面
111．．．第一焊墊
112．．．第一導電凸塊
12．．．下表面
121．．．第二焊墊
122．．．第二導電凸塊
13．．．貫孔
14．．．銲球
2．．．第一晶片
21．．．第一導電接點
22．．．第一引線
3．．．第二晶片
31．．．第二導電接點
32．．．第二引線
4．．．封裝材料
5．．．模具
6．．．封裝基板
7．．．第一晶片
71．．．第一封裝體
8．．．第二晶片
81．．．第二封裝體
圖1為一示意圖顯示習知之多晶片封裝結構。
圖2a為一示意圖顯示依據本發明一實施例之多晶片封裝結構。
圖2b為一示意圖顯示依據本發明另一實施例之多晶片封裝結構。
圖3為一示意圖顯示一種多晶片封裝結構之形成。
1．．．封裝基板
11．．．上表面
111．．．第一焊墊
12．．．下表面
121．．．第二焊墊
13．．．貫孔
14．．．銲球
2．．．第一晶片
21．．．第一導電接點
22．．．第一引線
3．．．第二晶片
31．．．第二導電接點
32．．．第二引線
4．．．封裝材料

Claims (6)

  1. 一種多晶片封裝結構，包含：一封裝基板，具有一上表面、一下表面以及一貫穿該上、下表面之貫孔；一第一晶片，設置於該上表面，並電性連接至該封裝基板；一第二晶片，設置於該下表面，並電性連接至該封裝基板，其中該貫孔係設置於該第一晶片及該第二晶片之區域外；以及一封裝材料，係包覆該第一晶片及該第二晶片並填滿該貫孔。
  2. 如請求項1所述之多晶片封裝結構，其中該第一晶片係以複數個第一引線電性連接該封裝基板。
  3. 如請求項1所述之多晶片封裝結構，其中該第一晶片係以複數個第一導電凸塊電性連接該封裝基板。
  4. 如請求項1所述之多晶片封裝結構，其中該第二晶片係以複數個第二引線電性連接至該封裝基板。
  5. 如請求項1所述之多晶片封裝結構，其中該第二晶片係以複數個第二導電凸塊電性連接該封裝基板。
  6. 如請求項1所述之多晶片封裝結構，其中該封裝基板更包含複數個銲球，設置於該下表面。
TW097146817A 2008-12-02 2008-12-02 多晶片封裝結構 TWI413232B (zh)

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US9385006B2 (en) 2012-06-21 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming an embedded SOP fan-out package

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030015782A1 (en) * 2001-06-29 2003-01-23 Choi Hee Kook Double-sided circuit board and multi-chip package including such a circuit board and method for manufacture
US20080150100A1 (en) * 2006-12-22 2008-06-26 Powertech Technology Inc. Ic package encapsulating a chip under asymmetric single-side leads

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030015782A1 (en) * 2001-06-29 2003-01-23 Choi Hee Kook Double-sided circuit board and multi-chip package including such a circuit board and method for manufacture
US20080150100A1 (en) * 2006-12-22 2008-06-26 Powertech Technology Inc. Ic package encapsulating a chip under asymmetric single-side leads

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