WO2013073082A1 - 拡張型半導体チップ及び半導体装置 - Google Patents

拡張型半導体チップ及び半導体装置 Download PDF

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Publication number
WO2013073082A1
WO2013073082A1 PCT/JP2012/005307 JP2012005307W WO2013073082A1 WO 2013073082 A1 WO2013073082 A1 WO 2013073082A1 JP 2012005307 W JP2012005307 W JP 2012005307W WO 2013073082 A1 WO2013073082 A1 WO 2013073082A1
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semiconductor chip
electrode
extended
semiconductor
chip
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PCT/JP2012/005307
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English (en)
French (fr)
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鉄平 岩瀬
萩原　清己
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パナソニック株式会社
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Priority to CN201280033924.0A priority Critical patent/CN103650135B/zh
Priority to JP2013544090A priority patent/JP5973461B2/ja
Publication of WO2013073082A1 publication Critical patent/WO2013073082A1/ja
Priority to US14/150,856 priority patent/US9136219B2/en

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Definitions

  • the present invention relates to an expandable semiconductor chip and a semiconductor device, and more particularly to a semiconductor device having an expandable semiconductor chip to be face-down mounted.
  • SoC system-on-chip
  • SiP system-in-package
  • a transistor included in the logic circuit chip are increasingly miniaturized.
  • the electrical characteristics of a transistor are easily affected by thermal stress generated during packaging of a semiconductor chip.
  • a bonding material such as a solder material is melted and then solidified.
  • the source / drain current of the transistor largely fluctuates due to the generated residual stress on the element formation surface of the semiconductor chip.
  • a low dielectric constant material called a low-k material is used corresponding to the miniaturization of the transistor.
  • the low-k material generally has low mechanical strength, and the stress on the element formation surface of the semiconductor chip during packaging causes a crack in the insulating layer made of the low-k material, or with other adjacent wiring materials. Separation occurs at or near the interface.
  • the present invention solves the above-described problems, and can prevent the thermal stress generated during packaging of the semiconductor chip from affecting the electrical characteristics of the active elements included in the semiconductor chip and the physical damage of the constituent materials.
  • the purpose is to do.
  • an extension portion formed outwardly from a side surface of a semiconductor chip is provided on at least one side surface of at least one semiconductor chip, and an external electrical connection is provided on the extension portion.
  • the electrode is formed so as to have a general connection.
  • a first semiconductor device includes a first semiconductor chip having a first electrode formed on a surface thereof, a second semiconductor chip, and at least one side surface of the second semiconductor chip.
  • An extended semiconductor chip having an extended portion formed outward and having a second electrode formed on a surface thereof.
  • the first semiconductor chip and the extended semiconductor chip include a first electrode and a second semiconductor chip.
  • the first electrode and the second electrode are connected to each other with the electrode forming surfaces facing each other, and the second electrode connected to the first electrode among the second electrodes in the extended semiconductor chip. Is formed only on the extension.
  • the second electrode connected to the first electrode is formed only on the extended portion. Therefore, there is no second electrode that is electrically connected to the first semiconductor chip on the element formation surface of the second semiconductor chip constituting the extended semiconductor chip. Therefore, it is possible to avoid the influence of thermal stress that occurs during packaging.
  • the second semiconductor chip is a plurality of semiconductor chips, and the extended portion of the extended semiconductor chip is formed between the side surfaces adjacent to each other in the second semiconductor chip. Also good.
  • the extended portion of the extended semiconductor chip may be formed around the second semiconductor chip.
  • the extended semiconductor chip includes a second electrode formed on the surface of the extended portion, and a third electrode formed on the element formation surface of the second semiconductor chip. A wiring connecting the two may be formed.
  • a through hole is formed in the extended portion in a region facing the first semiconductor chip, and a through hole is provided between the first semiconductor chip and the extended semiconductor chip.
  • the sealing resin material may be filled including the holes.
  • a second semiconductor device includes a wiring board having a first electrode formed on a surface thereof, a semiconductor chip and an extended portion formed outward from at least one side surface of the semiconductor chip, And an extended semiconductor chip on which the second electrode is formed, and the wiring substrate and the extended semiconductor chip are arranged so that the formation surfaces of the first electrode and the second electrode are opposed to each other.
  • the second electrode connected to the second electrode and connected to the first electrode among the second electrodes in the extended semiconductor chip is formed only on the extended portion.
  • the second electrode connected to the first electrode is formed only on the extended portion. Therefore, there is no second electrode that is electrically connected to the wiring board on the element formation surface of the second semiconductor chip constituting the expansion type semiconductor chip. Therefore, it is possible to avoid the influence of thermal stress that occurs during packaging.
  • the semiconductor chip may be a plurality of semiconductor chips, and the extended portion of the extended semiconductor chip may be formed between adjacent side surfaces of the semiconductor chip.
  • An extended semiconductor chip according to the present invention is formed on a plurality of semiconductor chips, an extended portion formed between adjacent side surfaces of the semiconductor chip, and the extended portion, and is electrically connected to the outside. And an electrode.
  • the extended semiconductor chip includes an electrode formed on the extended portion and electrically connected to the outside. For this reason, there is no electrode for electrical connection with the outside on the element formation surface of the semiconductor chip. Therefore, it is possible to avoid the influence of thermal stress that occurs during packaging.
  • the influence of the thermal stress generated during packaging of the semiconductor chip on the electrical characteristics of the active elements included in the semiconductor chip and the physical properties of the constituent materials Damage can be prevented.
  • FIG. 1 (a) to 1 (c) show an expandable semiconductor chip and a semiconductor device according to the first embodiment of the present invention
  • FIG. 1 (a) is a perspective view
  • FIG. 1 (b) is a plan view
  • FIG. 1C is a cross-sectional view taken along the line Ic-Ic in FIG. 2A to 2C show a semiconductor device according to a comparative example
  • FIG. 2A is a perspective view
  • FIG. 2B is a plan view
  • FIG. FIG. 2B is a cross-sectional view taken along line IIc-IIc in FIG.
  • FIG. 3 is a plan view showing a modified example of the extended semiconductor chip and the semiconductor device according to the first modified example of the first embodiment.
  • FIG. 1C is a cross-sectional view taken along the line Ic-Ic in FIG. 2A to 2C show a semiconductor device according to a comparative example
  • FIG. 2A is a perspective view
  • FIG. 2B is a plan view
  • FIG. 4 is a plan view showing a modified example of the extended semiconductor chip and the semiconductor device according to the second modified example of the first embodiment.
  • 5A and 5B show a semiconductor device according to a third modification of the first embodiment
  • FIG. 5A is a plan view
  • FIG. 5B is a plan view of FIG. Is a cross-sectional view taken along line Vb-Vb.
  • 6A and 6B show an extended semiconductor chip and a semiconductor device according to a fourth modification of the first embodiment
  • FIG. 6A is a plan view
  • FIG. FIG. 7 is a cross-sectional view taken along the line VIb-VIb in FIG. 7 (a) to 7 (c) show an expandable semiconductor chip and a semiconductor device according to the second embodiment of the present invention
  • FIG. 7 (a) is a perspective view
  • FIG. 7 (b) is a plan view
  • FIG. 7C is a cross-sectional view taken along the line VIIc-VIIc in FIG. 7B.
  • the semiconductor device 1 includes, for example, a first semiconductor chip having silicon (Si) as a base material, a transistor, and a multilayer wiring layer. 2 and an extended semiconductor chip 3 that holds the first semiconductor chip 2 on the upper surface (element formation surface) and includes a plurality of semiconductor chips 31 and 32.
  • a low-k material is used for the multilayer wiring layer in each of the semiconductor chips 2, 31 and 32 as an insulating layer.
  • the first semiconductor chip 2 is a surface facing the expandable semiconductor chip 3 and the element forming surface is made of a metal such as copper (Cu), aluminum (Al), or nickel (Ni), and has a plurality of external connections.
  • a first electrode (pad) 21 is formed.
  • the extended semiconductor chip 3 includes, for example, a second semiconductor chip 31 and a third semiconductor chip 32 which are made of silicon (Si) as a base material, and each has a transistor and a multilayer wiring layer formed thereon. Between the side surfaces adjacent to each other in the second semiconductor chip 31 and the third semiconductor chip 32, a resin expansion portion 33 filled with an epoxy resin material or the like is formed. By the resin expansion portion 33, the second semiconductor chip 31 and the third semiconductor chip 32 are integrally formed.
  • the resin expansion part 33 does not necessarily need to be formed with a resin material, and may be fixed with an adhesive with an insulator such as a ceramic material interposed.
  • a plurality of first chip electrodes 311 made of a metal such as Cu, Al, or Ni are formed on the second semiconductor chip 31.
  • a plurality of second chip electrodes 321 made of a metal such as Cu, Al, or Ni are formed on the third semiconductor chip 32.
  • a rewiring layer 34 made of an insulator such as polyimide is formed on the upper surfaces of the second semiconductor chip 31, the third semiconductor chip 32, and the resin extension portion 33 that are integrally formed.
  • a plurality of wirings 341 made of Cu, Al, or the like are formed inside the rewiring layer 34.
  • a plurality of second electrodes (pads) 35 made of a metal such as Cu, Al, or Ni and used for external connection are formed on the rewiring layer 34.
  • One end of each wiring 341 is electrically connected to one of the first chip electrode 311 and the second chip electrode 321, and the other end is electrically connected to one of the second electrodes 35 on the rewiring layer 34. It is connected.
  • the plurality of first electrodes 21 in the first semiconductor chip 2 and the plurality of second electrodes 35 in the extended semiconductor chip 3 are arranged to face each other.
  • the first electrode 21 and the second electrode 35 facing each other are electrically connected with a metal protrusion (bump) 4 made of a solder material or gold interposed therebetween.
  • bump metal protrusion
  • all of the plurality of second electrodes 35 formed on the upper surface of the extended semiconductor chip 3 are formed immediately above the resin extended portion 33. Note that, in a region on the rewiring layer 34 that does not face the first semiconductor chip 2, for example, an inspection electrode (not shown) or the like is formed in a region above the element formation surface of the semiconductor chips 31 and 32. It does not matter.
  • the plurality of first electrodes 21 has an arrangement number in the Y direction at a substantially central portion of the first semiconductor chip 2 rather than the arrangement number in the X direction. It is arranged in a large matrix. Accordingly, the resin expansion portion 33 of the expandable semiconductor chip 3 is arranged so that each second electrode 35 of the expandable semiconductor chip 3 can be disposed corresponding to the disposition of each first electrode 21 of the first semiconductor chip 2.
  • the second semiconductor chip 31 and the third semiconductor chip 32 are formed such that the length in the Y direction is longer than the length in the X direction.
  • the center portion of the chip indicates the relative positional relationship of the arrangement region of the first electrode 21 with respect to the outer shape of the first semiconductor chip 2. Specifically, when the distance from the center of the semiconductor chip to one corner is D, it is defined as a range of D / 2 or less from the center of the semiconductor chip.
  • the arrangement of the first electrodes 21 is schematically shown in 2 rows and 10 columns, but more arrangements are conceivable in an actual semiconductor device. Specifically, there are about 10 rows in the X direction and about 100 columns in the Y direction. Further, an arrangement in which the interval between the first electrodes 21 is about 40 ⁇ m to 50 ⁇ m is assumed.
  • the semiconductor device 5 shown in FIG. 2 is used as a comparative example.
  • symbol is attached
  • the second semiconductor chip 31 constituting the semiconductor light emitting device 5 according to the comparative example shown in FIG. 2 is a single chip and does not have a resin extension portion. Accordingly, the first chip electrode 311 of the second semiconductor chip 31 and the first electrode 21 of the first semiconductor chip 2 are directly connected by the metal protrusion 4.
  • solder connection method which is a typical method of CoC connection
  • semiconductor chips having solder materials previously placed on electrodes are bonded to face each other, heated to melt the solder material, and then the solder material is cooled. Connect by solidifying.
  • Si silicon
  • the molten solder material is solidified and contracted during cooling. It cannot absorb deformation caused by stress.
  • stress remains on each element formation surface of each semiconductor chip 2, 31.
  • the transistor formed on the element formation surface is easily affected by the stress, and the source / drain current greatly varies depending on the residual stress.
  • the insulating layer made of a low-k material formed on the element formation surface may be cracked or peeled off at or near the interface due to the influence of residual stress.
  • the semiconductor device 1 according to the first embodiment is in an area where the extended semiconductor chip 3 is joined to the first semiconductor chip 2 via the metal protrusion 4. Only the resin expansion portion 33 having a low rigidity and a linear expansion coefficient that is relatively close to the metal protrusion 4 such as a solder material is formed. For this reason, the residual stress in the element formation surface of the first semiconductor chip 2 is reduced. Further, since the metal protrusions 4 themselves do not exist on the element formation surfaces of the second semiconductor chip 31 and the third semiconductor chip 32 constituting the extended semiconductor chip 3, the influence of the residual stress due to the metal protrusions 4 is avoided. be able to.
  • a configuration in which the first semiconductor chip 2 is mounted on the extended semiconductor chip 3 including a plurality of semiconductor chips is, for example,
  • the pads of the second semiconductor chip 31 and the third semiconductor chip 32 are also drawn out on the resin extension portion 33 even when the pads of the first semiconductor chip 2 are biased to a specific portion of the element formation surface.
  • the pads can be arranged so as to correspond to the pads of the first semiconductor chip 2.
  • the first semiconductor chip 2 is a memory chip formed by concentrating pads in the central portion of the element formation surface, the pads of a plurality of semiconductor chips are gathered on the resin extension portion 33, The pad of the memory chip can be mounted facing the pad of the resin extension portion 33.
  • the position where the first electrode 21 of the first semiconductor chip 2 and the second electrode 35 of the expandable semiconductor chip 3 are connected to each other is substantially the same as that of the first semiconductor chip 2.
  • the expandable semiconductor chip 3 is composed of two semiconductor chips 31 and 32, and the resin expansion portion 33 is formed between the semiconductor chips 31 and 32 so as to be long in the Y direction.
  • the planar shape of the resin expansion portion 33 is not limited to the shape of FIG. 1B, and can be variously changed according to the arrangement position of the first electrode 21 of the first semiconductor chip 2.
  • FIG. 3 shows a planar configuration of a semiconductor device according to a first modification of the first embodiment.
  • the plurality of first electrodes 21 of the first semiconductor chip 2 are arranged in a matrix shape that is long in the Y direction at substantially the center of the first semiconductor chip 2. And the interval in the X direction is relatively large.
  • the expandable semiconductor chip 3 is constituted by three chips, a second semiconductor chip 31, a third semiconductor chip 32, and a fourth semiconductor chip 36. Therefore, for example, the fourth semiconductor chip 36 is disposed between the second semiconductor chip 31 and the third semiconductor chip 32.
  • resin expansion portions 33 are integrally formed between the second semiconductor chip 31 and the fourth semiconductor chip 36 and between the third semiconductor chip 32 and the fourth semiconductor chip 36, respectively.
  • a second electrode (not shown) of the extended semiconductor chip 3 is formed so that the first electrodes 21 face each other.
  • FIG. 4 shows a planar configuration of a semiconductor device according to the second modification of the first embodiment.
  • the plurality of first electrodes 21 of the first semiconductor chip 2 are concentrated in a substantially central portion of the first semiconductor chip 2 in a planar cross shape. Has been placed.
  • the expandable semiconductor chip 3 is divided into four semiconductor chips 31, a third semiconductor chip 32, a fourth semiconductor chip 36, and a fifth semiconductor chip 37. Consists of chips. Therefore, for example, the semiconductor chips 31, 32, 36, and 37 are arranged in two rows and two columns, and the resin expansion portion 33 is arranged between the opposing side surfaces.
  • the resin extended portion 33 is integrally formed between the semiconductor chip 36 and the second semiconductor chip 31 so that the first electrodes 21 face each other on the resin extended portion 33.
  • Second electrodes (not shown) are respectively formed.
  • FIG. 5A and FIG. 5B show a planar configuration and a cross-sectional configuration of a semiconductor device according to a third modification of the first embodiment.
  • the plurality of first electrodes 21 of the first semiconductor chip 2 are in the vicinity of two opposing side portions of the first semiconductor chip 2. Are arranged in a row.
  • the extended semiconductor chip 3 is formed only by the second semiconductor chip 31.
  • a resin extension portion 33 is provided on all four side surfaces of the second semiconductor chip 31, that is, around the second semiconductor chip 31, and is formed integrally with the second semiconductor chip 31.
  • the second electrode 35 of the extended semiconductor chip 3 is formed on the resin extended portion 33 so that the first electrodes 21 face each other.
  • FIGS. 6A and 6B show a planar configuration and a cross-sectional configuration of a semiconductor device according to a fourth modification of the first embodiment.
  • the semiconductor device 1 according to the fourth modification is, as an example, similar to the semiconductor device 1 according to the second modification shown in FIG.
  • the semiconductor chip 3 is composed of four semiconductor chips 31, 32, 36 and 37.
  • the difference between the fourth modification and the second modification is that the resin extension portion 33 is formed in a region facing the first semiconductor chip 2 and in which the metal protrusion 4 is not formed on the resin extension portion 33 constituting the expandable semiconductor chip 3.
  • the through-hole 33a which penetrates is provided.
  • the conventional general method of injecting the underfill material 6 from the side surface of the first semiconductor chip 2 has insufficient filling of the underfill material 6. Become. For this reason, there exists a possibility that a void may generate
  • the underfill material 6 is directly applied to the position closer to the metal protrusion 4 from the back surface of the extended semiconductor chip 3 through the plurality of through holes 33 a provided in advance. Inject. Thereby, the filling property of the underfill material 6 can be improved in the peripheral region of each metal protrusion 4.
  • the number of through holes 33a provided in the resin extension 33 and the rewiring layer 34 may be appropriately adjusted according to the size and number of the semiconductor chips 2 and 3.
  • the fourth modification in which the through hole 33a is provided can also be applied to the semiconductor device 1 according to the first embodiment, the first modification, and the third modification.
  • the semiconductor device 7 includes, for example, a first semiconductor that uses silicon (Si) as a base material and includes a transistor and a multilayer wiring layer, respectively.
  • the expansion semiconductor chip 8 includes a chip 81 and a second semiconductor chip 82, and a resin substrate (wiring substrate) 9 that holds the expansion semiconductor chip 8 on the upper surface and is made of an epoxy resin material or the like as a base material.
  • a low-k material is used as an insulating layer for the multilayer wiring layer in each of the semiconductor chips 81 and 82.
  • a resin extended portion 83 made of an epoxy resin material or the like is filled.
  • the resin extension 83 the first semiconductor chip 81 and the second semiconductor chip 82 are integrally formed.
  • a plurality of first chip electrodes 811 made of a metal such as copper (Cu), aluminum (Al), or nickel (Ni) are formed on the surface of the first semiconductor chip 81 facing the resin substrate 9 and on the element formation surface. ing.
  • a plurality of second chip electrodes 821 made of a metal such as Cu, Al, or Ni are formed on the element formation surface of the second semiconductor chip 82.
  • a rewiring layer 84 made of an insulator such as polyimide is formed on the first semiconductor chip 81, the second semiconductor chip 82, and the resin extension portion 83 that are integrally molded. In the rewiring layer 84, a plurality of wirings 841 made of Cu, Al, or the like are formed.
  • first electrodes (pads) 85 made of a metal such as Cu, Al or Ni and used for external connection are formed.
  • One end of each wiring 841 is electrically connected to one of the first chip electrode 811 and the second chip electrode 821, and the other end is electrically connected to one of the first electrodes 85 on the rewiring layer 84. It is connected.
  • a plurality of second electrodes (pads) 91 are formed on the resin substrate 9 at positions facing the first electrodes 85 of the expandable semiconductor chip 8.
  • the first electrode 85 and the second electrode 91 facing each other are electrically connected with a metal protrusion (bump) 4 made of a solder material or gold interposed therebetween.
  • bump metal protrusion
  • the plurality of first electrodes 85 formed on the element forming surface side of the extended semiconductor chip 8 are all formed immediately above the resin extended portion 83.
  • an inspection electrode (not shown) or the like is provided above the element formation surface of the semiconductor chips 31 and 32. It may be formed in the region.
  • the plurality of second electrodes 91 are arranged in the center of the resin substrate 9 in a matrix in which the number of arrangement in the Y direction is larger than the number of arrangement in the X direction.
  • the resin expansion portion 83 of the expandable semiconductor chip 8 is configured so that the first electrodes 85 of the expandable semiconductor chip 8 can be respectively disposed corresponding to the disposition of the second electrodes 91 of the resin substrate 9.
  • the semiconductor chip 81 and the second semiconductor chip 82 are formed such that the length in the Y direction is longer than the length in the X direction.
  • the arrangement of the second electrodes 91 is schematically shown in 2 rows and 10 columns, but more arrangements are conceivable in an actual semiconductor device. Specifically, there are about 10 rows in the X direction and about 100 columns in the Y direction. Further, an arrangement in which the interval between the first electrodes 21 is about 40 ⁇ m to 50 ⁇ m is assumed.
  • planar shape of the resin expansion portion 83 is not limited to the shape of FIG. 7B, and can be variously changed according to the arrangement position of the second electrode 91 of the resin substrate 9.
  • the metal protrusions 4 themselves called bumps do not exist on the element formation surfaces of the first semiconductor chip 81 and the second semiconductor chip 82 constituting the extended semiconductor chip 8.
  • the effects of the shrinkage of the resin substrate 9, the solidification of the metal protrusions 4 and the cooling shrinkage are not transmitted to the element forming surface. Therefore, the influence of the residual stress of the resin substrate 9 and the metal protrusion 4 can be avoided.
  • the expandable semiconductor chip and the semiconductor device according to the present invention can prevent the influence of the thermal stress generated during the packaging of the semiconductor chip on the electrical characteristics of the active element and the physical damage of the constituent material, and are particularly face-down mounted. This is useful for a semiconductor device having an extended semiconductor chip.

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Abstract

　半導体装置（１）は、表面に第１電極（２１）が形成された第１半導体チップ（２）と、第２半導体チップ（３１）及び該第２半導体チップの少なくとも１つの側面から外方に形成された樹脂拡張部（３３）を有し、表面に第２電極（３５）が形成された拡張型半導体チップ（３）とを備えている。第１半導体チップと拡張型半導体チップとは、第１電極及び第２の電極の形成面同士を対向させて、第１電極と第２電極とを互いに接続している。拡張型半導体チップにおける第２電極のうち、第１電極と接続された第２電極は、樹脂拡張部の上にのみ形成されている。

Description

拡張型半導体チップ及び半導体装置
　本発明は、拡張型半導体チップ及び半導体装置に関し、特にフェイスダウン実装される拡張型半導体チップを有する半導体装置に関する。
　デジタルテレビ及びデジタルレコーダ等のシステムにおいては、高機能化に伴い、扱うデータ量が飛躍的に増加している。このため、システムに搭載される半導体メモリ装置においては、容量の増加と高いデータ転送レートとが要求されている。
　このような半導体メモリ装置を搭載する半導体装置として、メモリコントローラを実装した論理回路とメモリ回路とを１つのチップに集積するシステム・オン・チップ（System on Chip：ＳｏＣ）と、メモリコントローラを実装した論理回路チップとメモリ回路チップとを積層して１つのパッケージに収容するシステム・イン・パッケージ(System in Package：ＳｉＰ）とがある。
　現在は、製造コストが比較的に低いＳｉＰを用いたシステムが増える傾向にある。ＳｉＰ構造を採る半導体装置において、積層される論理回路チップとメモリ回路チップとの間を電気的に接続する方法には、論理回路チップの素子形成面とメモリチップの素子形成面とを対向させて、はんだ材等からなる金属突起（バンプ）を介してそれぞれの電極同士を直接に接続するチップ・オン・チップ（Chip on Chip：ＣｏＣ）技術を用いる方法がある。これにより、データ転送レートの向上を図っている（例えば、特許文献１を参照。）。
特開２０１０－１４１０８０号公報
　半導体装置の小型化が進むに従い、論理回路チップに含まれる能動素子（特にトランジスタ）は、ますます微細化されている。トランジスタの電気的特性は、半導体チップのパッケージング時に発生する熱応力による影響を受けやすく、例えば、半導体チップをＣｏＣ接続する場合に、はんだ材等の接合材が溶融し、その後、凝固する際に発生する半導体チップの素子形成面の残留応力によって、トランジスタのソースドレイン電流が大きく変動する。また、半導体チップの多層配線層に用いられる絶縁材料には、トランジスタの微細化に対応して、Ｌｏｗ－ｋ材料と呼ばれる低誘電率材料が用いられている。Ｌｏｗ－ｋ材料は、一般に機械的強度が低く、パッケージング時における半導体チップの素子形成面への応力により、Ｌｏｗ－ｋ材料からなる絶縁層にクラックが生じたり、近接する他の配線材料との界面又はその近傍において剥離が発生したりする。
　本発明は、前記の問題を解決し、半導体チップのパッケージング時に発生する熱応力による該半導体チップに含まれる能動素子等の電気的特性への影響及び構成材料の物理的損傷を防止できるようにすることを目的とする。
　前記の目的を達成するため、本発明は、少なくとも１つの半導体チップにおける少なくとも１つの側面上に半導体チップの側面から外方に形成された拡張部を設け、該拡張部の上に外部との電気的な接続をとる電極を形成する構成とする。
　具体的に、本発明に係る第１の半導体装置は、表面に第１の電極が形成された第１の半導体チップと、第２の半導体チップ及び該第２の半導体チップの少なくとも１つの側面から外方に形成された拡張部を有し、表面に第２の電極が形成された拡張型半導体チップとを備え、第１の半導体チップと拡張型半導体チップとは、第１の電極及び第２の電極の形成面同士を対向させて、第１の電極と第２の電極とを互いに接続し、拡張型半導体チップにおける第２の電極のうち、第１の電極と接続された第２の電極は、拡張部の上にのみ形成されている。
　本発明の第１の半導体装置によると、拡張型半導体チップにおける第２の電極のうち、第１の電極と接続された第２の電極は、拡張部の上にのみ形成されている。このため、拡張型半導体チップを構成する第２の半導体チップの素子形成面上には、第１の半導体チップと電気的な接続をとる第２の電極が存在しない。従って、パッケージング時に発生する熱応力の影響を回避することができる。
　本発明の第１の半導体装置において、第２の半導体チップは複数の半導体チップであり、拡張型半導体チップの拡張部は、第２の半導体チップにおける互いに隣接する側面同士の間に形成されていてもよい。
　また、本発明の第１の半導体装置において、拡張型半導体チップの拡張部は、第２の半導体チップの周囲に形成されていてもよい。
　本発明の第１の半導体装置において、拡張型半導体チップには、拡張部の表面に形成された第２の電極と第２の半導体チップの素子形成面の上に形成された第３の電極とを接続する配線が形成されていてもよい。
　本発明の第１の半導体装置において、拡張部には、第１の半導体チップと対向する領域に貫通孔が形成されており、第１の半導体チップと拡張型半導体チップとの間には、貫通孔を含め、封止用樹脂材が充填されていてもよい。
　本発明に係る第２の半導体装置は、表面に第１の電極が形成された配線基板と、半導体チップ及び該半導体チップの少なくとも１つの側面から外方に形成された拡張部を有し、表面に第２の電極が形成された拡張型半導体チップとを備え、配線基板と拡張型半導体チップとは、第１の電極及び第２の電極の形成面同士を対向させて、第１の電極と第２の電極とを互いに接続し、拡張型半導体チップにおける第２の電極のうち、第１の電極と接続された第２の電極は、拡張部の上にのみ形成されている。
　本発明の第２の半導体装置によると、拡張型半導体チップにおける第２の電極のうち、第１の電極と接続された第２の電極は、拡張部の上にのみ形成されている。このため、拡張型半導体チップを構成する第２の半導体チップの素子形成面上には、配線基板と電気的な接続をとる第２の電極が存在しない。従って、パッケージング時に発生する熱応力の影響を回避することができる。
　本発明の第２の半導体装置において、半導体チップは複数の半導体チップであり、拡張型半導体チップの拡張部は、半導体チップにおける互いに隣接する側面同士の間に形成されていてもよい。
　本発明に係る拡張型半導体チップは、複数の半導体チップと、半導体チップにおける互いに隣接する側面同士の間に形成された拡張部と、拡張部の上に形成され、外部と電気的な接続をとる電極とを備えている。
　本発明の拡張型半導体チップによると、拡張部の上に形成され、外部と電気的な接続をとる電極を備えている。このため、半導体チップの素子形成面上には、外部との電気的な接続をとる電極が存在しない。従って、パッケージング時に発生する熱応力の影響を回避することができる。
　本発明に係る拡張型半導体チップ及びそれを用いた半導体装置によると、半導体チップのパッケージング時に発生する熱応力による該半導体チップに含まれる能動素子等の電気的特性への影響及び構成材料の物理的損傷を防止することができる。
図１（ａ）～図１（ｃ）は本発明の第１の実施形態に係る拡張型半導体チップ及び半導体装置を示し、図１（ａ）は斜視図であり、図１（ｂ）は平面図であり、図１（ｃ）は図１（ｂ）のＩｃ－Ｉｃ線における断面図である。 図２（ａ）～図２（ｃ）は比較例に係る半導体装置を示し、図２（ａ）は斜視図であり、図２（ｂ）は平面図であり、図２（ｃ）は図２（ｂ）のIIｃ－IIｃ線における断面図である。 図３は第１の実施形態の第１変形例に係る拡張型半導体チップ及び半導体装置の変形例を示す平面図である。 図４は第１の実施形態の第２変形例に係る拡張型半導体チップ及び半導体装置の変形例を示す平面図である。 図５（ａ）及び図５（ｂ）は第１の実施形態の第３変形例に係る半導体装置を示し、図５（ａ）は平面図であり、図５（ｂ）は図５（ａ）のＶｂ－Ｖｂ線における断面図である。 図６（ａ）及び図６（ｂ）は第１の実施形態の第４変形例に係る拡張型半導体チップ及び半導体装置を示し、図６（ａ）は平面図であり、図６（ｂ）は図６（ａ）のVIｂ－VIｂ線における断面図である。 図７（ａ）～図７（ｃ）は本発明の第２の実施形態に係る拡張型半導体チップ及び半導体装置を示し、図７（ａ）は斜視図であり、図７（ｂ）は平面図であり、図７（ｃ）は図７（ｂ）のVIIｃ－VIIｃ線における断面図である。
　（第１の実施形態）
　本発明の第１の実施形態について図１（ａ）～図１（ｃ）を参照しながら説明する。
　図１（ａ）～図１（ｃ）に示すように、第１の実施形態に係る半導体装置１は、例えば、シリコン（Ｓｉ）を基材とし、トランジスタ及び多層配線層を有する第１半導体チップ２と、上面（素子形成面）に第１半導体チップ２を保持し、且つ複数の半導体チップ３１、３２を含む拡張型半導体チップ３とから構成されている。各半導体チップ２、３１及び３２における多層配線層には、絶縁層として、例えばＬｏｗ－ｋ材料が用いられている。
　第１半導体チップ２における拡張型半導体チップ３との対向面であり且つ素子形成面には、銅（Ｃｕ）、アルミニウム（Ａｌ）又はニッケル（Ｎｉ）等の金属からなり、外部接続用の複数の第１電極（パッド）２１が形成されている。
　拡張型半導体チップ３は、例えばシリコン（Ｓｉ）を基材とし、それぞれにトランジスタ及び多層配線層が形成された第２半導体チップ３１及び第３半導体チップ３２とを有している。第２半導体チップ３１及び第３半導体チップ３２における互いに隣接する側面同士の間には、エポキシ樹脂材等が充填されてなる樹脂拡張部３３が形成されている。この樹脂拡張部３３により、第２半導体チップ３１及び第３半導体チップ３２は一体に形成されている。なお、樹脂拡張部３３は、必ずしも樹脂材により形成される必要はなく、セラミック材等の絶縁体を介在させて接着材により固着してもよい。
　第２半導体チップ３１の上には、Ｃｕ、Ａｌ又はＮｉ等の金属からなる複数の第１チップ電極３１１が形成されている。同様に、第３半導体チップ３２の上には、Ｃｕ、Ａｌ又はＮｉ等の金属からなる複数の第２チップ電極３２１が形成されている。一体に成形された第２半導体チップ３１、第３半導体チップ３２及び樹脂拡張部３３の上面には、ポリイミド等の絶縁体からなる再配線層３４が形成されている。再配線層３４の内部には、Ｃｕ又はＡｌ等からなる複数の配線３４１が形成されている。また、再配線層３４の上には、Ｃｕ、Ａｌ又はＮｉ等の金属からなり、外部接続用の複数の第２電極（パッド）３５が形成されている。各配線３４１の一端は、第１チップ電極３１１及び第２チップ電極３２１のいずれかと電気的に接続され、また、その他端は、再配線層３４の上の第２電極３５のいずれかと電気的に接続されている。
　第１半導体チップ２における複数の第１電極２１と、拡張型半導体チップ３における複数の第２電極３５とは、互いに対向して配置されている。互いに対向する第１電極２１と第２電極３５とは、それぞれの間にはんだ材又は金等からなる金属突起（バンプ）４を介在させて電気的に接続されている。　
　ここで、第１の実施形態の特徴として、拡張型半導体チップ３の上面に形成された複数の第２電極３５は、そのすべてが樹脂拡張部３３の直上に形成されている。なお、再配線層３４の上の第１半導体チップ２と対向しない領域には、例えば検査用の電極（図示せず）等が、半導体チップ３１、３２の素子形成面の上側の領域に形成されていても構わない。
　図１（ｂ）に示すように、第１の実施形態においては、複数の第１電極２１は、第１半導体チップ２のほぼ中央部に、Ｘ方向の配列数よりもＹ方向の配列数が大きい行列状に配置されている。従って、第１半導体チップ２の各第１電極２１の配置に対応して、拡張型半導体チップ３の各第２電極３５がそれぞれ配置できるように、拡張型半導体チップ３の樹脂拡張部３３は、第２半導体チップ３１と第３半導体チップ３２との間に、Ｙ方向の長さがＸ方向の長さよりも長くなるように形成されている。
　本願明細書において、チップの中央部とは、第１半導体チップ２の外形に対する第１電極２１の配置領域の相対的な位置関係を示している。具体的には、半導体チップの中心から一角部までの距離をＤとした場合に、半導体チップの中心からＤ／２以下の範囲と定義する。
　図１（ａ）及び図１（ｂ）においては、第１電極２１の配列を、模式的に２行１０列で示したが、実際の半導体装置においては、より多くの配置が考えられる。具体的には、Ｘ方向に約１０行程度で、且つＹ方向に約１００列程度である。また、第１電極２１同士の間隔は４０μｍ～５０μｍ程度とする配列が想定される。
　以下、前記のように構成された半導体装置１によって、第１半導体チップ２と拡張型半導体チップ３とをパッケージングする際に発生する熱応力による各半導体チップのトランジスタの電気的特性への影響及び各半導体チップ２、３の多層配線層に含まれるＬｏｗ－ｋ材料からなる絶縁層に生じるクラック又は剥離等の物理的損傷を回避できる理由を説明する。ここでは、図２に示す半導体装置５を比較例とする。なお、図１に示す構成部材と同一の構成部材には同一の符号を付している。図２に示す比較例に係る半導体発光装置５を構成する第２半導体チップ３１は、単体のチップであり、樹脂拡張部を有していない。従って、第２半導体チップ３１の第１チップ電極３１１と、第１半導体チップ２の第１電極２１とは、金属突起４によって直接に接続されている。
　ＣｏＣ接続の代表的な工法であるはんだ接続法においては、あらかじめ電極上にはんだ材を載置した半導体チップ同士を対向させて接着し、加熱によりはんだ材を溶融させ、その後、はんだ材を冷却して固化させることにより接続する。図２に示す比較例の場合は、溶融したはんだ材の凝固及び冷却時の収縮に対し、各半導体チップ２、３１は剛性が高く線膨張係数が低いシリコン（Ｓｉ）を基材としているため、応力による変形を吸収できない。これにより、各半導体チップ２、３１の各素子形成面に応力が残留することになる。素子形成面に形成されているトランジスタは、その応力の影響を受けやすく、残留応力によってソースドレイン電流が大きく変動する。また、素子形成面に形成されたＬｏｗ－ｋ材料からなる絶縁層は、残留応力の影響により、クラックが生じたり、さらには界面又はその近傍で剥がれたりするおそれがある。
　これに対し、図１（ｃ）に示すように、第１の実施形態に係る半導体装置１は、拡張型半導体チップ３において、金属突起４を介して第１半導体チップ２と接合される領域に、剛性が低く且つ線膨張係数がはんだ材等の金属突起４と比較的に近い樹脂拡張部３３のみが形成されている。このため、第１半導体チップ２の素子形成面における残留応力は小さくなる。また、拡張型半導体チップ３を構成する第２半導体チップ３１及び第３半導体チップ３２の各素子形成面上においては、金属突起４自体が存在しないため、金属突起４による残留応力の影響を回避することができる。
　第１の実施形態のように、複数の半導体チップ（第２半導体チップ３１及び第３半導体チップ３２）を含む拡張型半導体チップ３の上に、第１の半導体チップ２を搭載する構成は、例えば、第１の半導体チップ２のパッドが素子形成面の特定の部分に偏って配置されている場合にも、第２半導体チップ３１及び第３半導体チップ３２のパッドを樹脂拡張部３３の上に引き出し、第１の半導体チップ２のパッドと対応するようにパッドを配置することができる。例えば、第１の半導体チップ２が、素子形成面の中央部分にパッドが集中して形成されたメモリチップであった場合に、複数の半導体チップのパッドを樹脂拡張部３３の上に集約し、メモリチップのパッドを樹脂拡張部３３のパッドと対向させて搭載することができる。これにより、下側の複数チップのパッドの配置に合わせた、特殊なパッド配置を持つメモリチップを準備する必要がなくなるので、汎用メモリを用いることが可能となる。
　第１の実施形態においては、前述したように、第１半導体チップ２の第１電極２１と拡張型半導体チップ３の第２電極３５とが互いに接続される位置が、第１半導体チップ２のほぼ中央部に、且つ、Ｘ方向の配列数よりもＹ方向の配列数が多くなるように行列状に配置されている。このため、拡張型半導体チップ３を２つの半導体チップ３１、３２で構成すると共に、樹脂拡張部３３を各半導体チップ３１、３２同士の間にＹ方向に長くなるように形成している。但し、樹脂拡張部３３の平面形状は、図１（ｂ）の形状に限られず、第１半導体チップ２の第１電極２１の配置位置に応じて種々に変更することができる。
　以下、第１の実施形態の変形例について図３～図６を参照しながら説明する。
　（第１の実施形態の第１変形例）
　図３は第１の実施形態の第１変形例に係る半導体装置の平面構成を示している。図３に示すように、第１変形例に係る半導体装置１は、第１半導体チップ２の複数の第１電極２１が、該第１半導体チップ２のほぼ中央部に、Ｙ方向に長い行列状に配置され、且つＸ方向の間隔が比較的に大きくなるように配置されている。複数の第１電極２１がこのように配置されている場合は、拡張型半導体チップ３を、第２半導体チップ３１、第３半導体チップ３２及び第４半導体チップ３６の３つのチップで構成する。従って、例えば、第２半導体チップ３１と第３半導体チップ３２との間に第４半導体チップ３６が挟まれるように配置する。
　さらに、第２半導体チップ３１と第４半導体チップ３６との間、及び第３半導体チップ３２と第４半導体チップ３６との間にそれぞれ樹脂拡張部３３を一体に形成して、各樹脂拡張部３３の上に各第１電極２１が対向するように、拡張型半導体チップ３の第２電極（図示せず）をそれぞれ形成する。
　（第１の実施形態の第２変形例）
　図４は第１の実施形態の第２変形例に係る半導体装置の平面構成を示している。図４に示すように、第２変形例に係る半導体装置１は、第１半導体チップ２の複数の第１電極２１が、該第１半導体チップ２のほぼ中央部に集中して平面十字状に配置されている。複数の第１電極２１がこのように配置されている場合は、拡張型半導体チップ３を、第２半導体チップ３１、第３半導体チップ３２、第４半導体チップ３６及び第５半導体チップ３７の４つのチップで構成する。従って、例えば、各半導体チップ３１、３２、３６及び３７を２行２列に配置し、その対向する側面同士の間に樹脂拡張部３３を配置する。
　一例として、第２半導体チップ３１と第３半導体チップ３２との間、第３半導体チップ３２と第５半導体チップ３７との間、第５半導体チップ３７と第４半導体チップ３６との間、及び第４半導体チップ３６と第２半導体チップ３１との間にそれぞれ樹脂拡張部３３を一体に形成して、樹脂拡張部３３の上に各第１電極２１が対向するように、拡張型半導体チップ３の第２電極（図示せず）をそれぞれ形成する。
　（第１の実施形態の第３変形例）
　図５（ａ）及び図５（ｂ）は第１の実施形態の第３変形例に係る半導体装置の平面構成及び断面構成を示している。図５（ａ）に示すように、第３変形例に係る半導体装置１は、第１半導体チップ２の複数の第１電極２１が、該第１半導体チップ２の対向する２つの側部の近傍に一列ずつ配置されている。複数の第１電極２１がこのように配置されている場合は、拡張型半導体チップ３を第２半導体チップ３１でのみ形成する。さらに、第２半導体チップ３１の４つの側面のすべてに、すなわち第２半導体チップ３１の周囲に樹脂拡張部３３を設け、第２半導体チップ３１と一体に形成する。さらに、樹脂拡張部３３の上に各第１電極２１が対向するように、拡張型半導体チップ３の第２電極３５をそれぞれ形成する。
　（第１の実施形態の第４変形例）
　図６（ａ）及び図６（ｂ）は第１の実施形態の第４変形例に係る半導体装置の平面構成及び断面構成を示している。図６（ａ）及び図６（ｂ）に示すように、第４変形例に係る半導体装置１は、一例として、図４に示した第２変形例に係る半導体装置１と同様に、拡張型半導体チップ３を４つの半導体チップ３１、３２、３６及び３７から構成している。
　第４変形例の第２変形例との相違点は、拡張型半導体チップ３を構成する樹脂拡張部３３に、第１半導体チップ２と対向し且つ金属突起４が形成されない領域に樹脂拡張部３３を貫通する貫通孔３３ａを設けている点である。
　具体的には、図６（ａ）に示すように、平面十字状に形成された樹脂拡張部３３のうち、第１半導体チップ２の複数の第１電極２１の外側で且つ第１半導体チップ２の外形線（全側面）の内側の領域において、樹脂拡張部３３及び再配線層３４を表裏方向に貫通する複数の貫通孔３３ａを設けている。
　第１半導体チップ２と拡張型半導体チップ３とが金属突起４によって接続された後、さらに、封止用樹脂材であるアンダーフィル材６を第１半導体チップ２と拡張型半導体チップ３との間に注入する。このとき、金属突起４の高さが小さい場合には、第１半導体チップ２の側面からアンダーフィル材６を注入するという従来の一般的な方法では、アンダーフィル材６の充填性が不十分となる。このため、金属突起４の周辺にボイドが発生するおそれがある。
　しかしながら、第４変形例においては、金属突起４による接続を行った後に、拡張型半導体チップ３の裏面から、あらかじめ設けた複数の貫通孔３３ａを通して金属突起４により近い位置にアンダーフィル材６を直接に注入する。これにより、各金属突起４の周辺領域に対して、アンダーフィル材６の充填性を向上することができる。
　なお、樹脂拡張部３３及び再配線層３４に設ける貫通孔３３ａの個数は、各半導体チップ２、３の大きさ及び個数によって適宜調整すればよい。また、貫通孔３３ａを設ける第４変形例は、第１の実施形態、その第１変形例及び第３変形例に係る半導体装置１においても、適用が可能である。
　（第２の実施形態）
　以下、本発明の第２の実施形態について図７（ａ）～図７（ｃ）を参照しながら説明する。
　図７（ａ）～図７（ｃ）に示すように、第２の実施形態に係る半導体装置７は、例えば、シリコン（Ｓｉ）を基材とし、それぞれトランジスタ及び多層配線層を有する第１半導体チップ８１及び第２半導体チップ８２を含む拡張型半導体チップ８と、上面に拡張型半導体チップ８を保持する、エポキシ樹脂材等を基材とした樹脂基板（配線基板）９とから構成されている。各半導体チップ８１及び８２における多層配線層には、絶縁層として、例えばＬｏｗ－ｋ材料が用いられている。
　拡張型半導体チップ８における第１半導体チップ８１及び第２半導体チップ８２の互いに隣接する側面同士の間には、エポキシ樹脂材等からなる樹脂拡張部８３が充填されている。この樹脂拡張部８３により、第１半導体チップ８１及び第２半導体チップ８２は一体に形成されている。
　第１半導体チップ８１における樹脂基板９と対向面であり且つ素子形成面には、銅（Ｃｕ）、アルミニウム（Ａｌ）又はニッケル（Ｎｉ）等の金属からなる複数の第１チップ電極８１１が形成されている。同様に、第２半導体チップ８２の素子形成面には、Ｃｕ、Ａｌ又はＮｉ等の金属からなる複数の第２チップ電極８２１が形成されている。一体に成形された第１半導体チップ８１、第２半導体チップ８２及び樹脂拡張部８３の上には、ポリイミド等の絶縁体からなる再配線層８４が形成されている。再配線層８４の内部には、Ｃｕ又はＡｌ等からなる複数の配線８４１が形成されている。また、再配線層８４の上には、Ｃｕ、Ａｌ又はＮｉ等の金属からなり、外部接続用の複数の第１電極（パッド）８５が形成されている。各配線８４１の一端は、第１チップ電極８１１及び第２チップ電極８２１のいずれかと電気的に接続され、また、その他端は、再配線層８４の上の第１電極８５のいずれかと電気的に接続されている。
　また、樹脂基板９の上には、拡張型半導体チップ８の第１電極８５と対向する位置に、複数の第２電極（パッド）９１が形成されている。互いに対向する第１電極８５と第２電極９１とは、それぞれの間にはんだ材又は金等からなる金属突起（バンプ）４を介在させて電気的に接続されている。　
　ここで、第２の実施形態の特徴として、拡張型半導体チップ８の素子形成面側に形成された複数の第１電極８５は、そのすべてが樹脂拡張部８３の直上に形成されている。なお、再配線層８４の上で、樹脂基板９の第２電極９１と対向しない領域には、例えば検査用の電極（図示せず）等が、半導体チップ３１、３２の素子形成面の上側の領域に形成されていても構わない。
　図７（ｂ）に示すように、第２の実施形態においては、複数の第２電極９１は、樹脂基板９のほぼ中央部に、Ｘ方向の配列数よりもＹ方向の配列数が大きい行列状に配置されている。従って、樹脂基板９の各第２電極９１の配置に対応して、拡張型半導体チップ８の各第１電極８５がそれぞれ配置できるように、拡張型半導体チップ８の樹脂拡張部８３は、第１半導体チップ８１と第２半導体チップ８２との間に、Ｙ方向の長さがＸ方向の長さよりも長くなるように形成されている。
　図７（ａ）及び図７（ｂ）においては、第２電極９１の配列を模式的に２行１０列で示したが、実際の半導体装置においては、より多くの配置が考えられる。具体的には、Ｘ方向に約１０行程度で、且つＹ方向に約１００列程度である。また、第１電極２１同士の間隔は４０μｍ～５０μｍ程度とする配列が想定される。
　但し、樹脂拡張部８３の平面形状は、図７（ｂ）の形状に限られず、樹脂基板９の第２電極９１の配置位置に応じて種々に変更することができる。
　第２の実施形態に係る半導体装置７によると、拡張型半導体チップ８のパッケージング時に発生する熱応力による各半導体チップ８１、８２のトランジスタの電気的特性への影響及びＬｏｗ－ｋ材料からなる絶縁層に生じるクラック又は剥離等の物理的損傷を回避することができる。
　すなわち、第１の実施形態と同様に、拡張型半導体チップ８を構成する第１半導体チップ８１及び第２半導体チップ８２の各素子形成面上においては、バンプと呼ばれる金属突起４自体が存在しないため、樹脂基板９の収縮、金属突起４の凝固及び冷却収縮等の影響は、素子形成面には伝わらない。従って、これら樹脂基板９及び金属突起４の残留応力による影響を回避することができる。
　本発明に係る拡張型半導体チップ及び半導体装置は、半導体チップのパッケージング時に発生する熱応力による能動素子等の電気的特性への影響及び構成材料の物理的損傷を防止でき、特にフェイスダウン実装される拡張型半導体チップを有する半導体装置等に有用である。
１　　　半導体装置
２　　　第１半導体チップ
２１　　第１電極
３　　　拡張型半導体チップ
３１　　第２半導体チップ
３２　　第３半導体チップ
３１１　第１チップ電極
３２１　第２チップ電極
３３　　樹脂拡張部
３３ａ　貫通孔
３４　　再配線層
３４１　配線
３５　　第２電極
３６　　第３半導体チップ
３７　　第４半導体チップ
４　　　金属突起
５　　　半導体装置
６　　　アンダーフィル材
７　　　半導体装置
８　　　拡張型半導体チップ
８１　　第１半導体チップ
８２　　第２半導体チップ
８１１　第１チップ電極
８２１　第２チップ電極
８３　　樹脂拡張部
８４　　再配線層
８４１　配線　
８５　　第１電極
９　　　樹脂基板
９１　　第２電極

Claims (8)

  1. 　表面に第１の電極が形成された第１の半導体チップと、
    　第２の半導体チップ及び該第２の半導体チップの少なくとも１つの側面から外方に形成された拡張部を有し、表面に第２の電極が形成された拡張型半導体チップとを備え、
    　前記第１の半導体チップと前記拡張型半導体チップとは、前記第１の電極及び第２の電極の形成面同士を対向させて、前記第１の電極と前記第２の電極とを互いに接続し、
    　前記拡張型半導体チップにおける前記第２の電極のうち、前記第１の電極と接続された第２の電極は、前記拡張部の上にのみ形成されている半導体装置。
  2. 　請求項１において、
    　前記第２の半導体チップは複数の半導体チップであり、
    　前記拡張型半導体チップの前記拡張部は、前記第２の半導体チップにおける互いに隣接する側面同士の間に形成されている半導体装置。
  3. 　請求項１において、
    　前記拡張型半導体チップの前記拡張部は、前記第２の半導体チップの周囲に形成されている半導体装置。
  4. 　請求項１～３のいずれか１項において、
    　前記拡張型半導体チップには、前記拡張部の表面に形成された前記第２の電極と前記第２の半導体チップの素子形成面の上に形成された第３の電極とを接続する配線が形成されている半導体装置。
  5. 　請求項１～４のいずれか１項において、
    　前記拡張部には、前記第１の半導体チップと対向する領域に貫通孔が形成されており、
    　前記第１の半導体チップと前記拡張型半導体チップとの間には、前記貫通孔を含め、封止用樹脂材が充填されている半導体装置。
  6. 　表面に第１の電極が形成された配線基板と、
    　半導体チップ及び該半導体チップの少なくとも１つの側面から外方に形成された拡張部を有し、表面に第２の電極が形成された拡張型半導体チップとを備え、
    　前記配線基板と前記拡張型半導体チップとは、前記第１の電極及び第２の電極の形成面同士を対向させて、前記第１の電極と前記第２の電極とを互いに接続し、
    　前記拡張型半導体チップにおける前記第２の電極のうち、前記第１の電極と接続された第２の電極は、前記拡張部の上にのみ形成されている半導体装置。
  7. 　請求項６において、
    　前記半導体チップは複数の半導体チップであり、
    　前記拡張型半導体チップの前記拡張部は、前記半導体チップにおける互いに隣接する側面同士の間に形成されている半導体装置。
  8. 　複数の半導体チップと、
    　前記半導体チップにおける互いに隣接する側面同士の間に形成された拡張部と、
    　前記拡張部の上に形成され、外部と電気的な接続をとる電極とを備えている拡張型半導体チップ。
PCT/JP2012/005307 2011-11-16 2012-08-24 拡張型半導体チップ及び半導体装置 WO2013073082A1 (ja)

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