JP2009200274A - 集積半導体装置 - Google Patents
集積半導体装置 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
【解決手段】集積素子回路または素子外形寸法の異なる複数個のLSIチップ2およびMEMSチップ3と、複数個のLSIチップ2およびMEMSチップ3の間に配置される絶縁材料4と、複数個のLSIチップ2およびMEMSチップ3と絶縁材料4上に全体的に配置される有機絶縁膜7と、有機絶縁膜7上に配置され、複数個のLSIチップ2およびMEMSチップ3を互いに接続する微細薄膜配線8と、複数個のLSIチップ2およびMEMSチップ3が配置されている領域上に選択的に配置されるI/O電極10と、I/O電極10上に形成されるバンプ電極5と、を備えたこと、を特徴とする。
【選択図】 図2
Description
次に、本実施の形態にかかる集積半導体装置の製造方法について説明する。図7−1〜図7−13は、本実施の形態にかかる集積半導体装置(擬似SOCチップ)1の工程断面図であり、図1のA−A矢視断面部分に相当する。
錫イオン(Sn2+) 12Vol%
鉛イオン(Pb2+) 30Vol%
脂肪族スルホン酸 41Vol%
ノニオン系界面活性剤 5Vol%
カチオン系界面活性剤 5Vol%
イソプロピルアルコール 7Vol%
さらに、図7−1〜図7−13で説明した集積半導体装置の製造方法で製造した集積半導体装置(擬似SOCチップ)1を回路配線基板200にフリップチップ実装する方法について説明する。具体的には、公知の技術であるハーフミラーを有して位置合わせを行うフリップチップボンダーを用いて、回路配線基板200の電極端子と集積半導体装置(擬似SOCチップ)1のバンプ電極5との位置合わせを行う。なお、集積半導体装置(擬似SOCチップ)1は加熱機構を有するコレットに保持され、350℃の窒素雰囲気中で予備加熱されている。
2 LSIチップ
3 MEMSチップ
4 絶縁材料
5 バンプ電極
6 コンタクト部
7、9 有機絶縁膜
8 微細薄膜配線
10 I/O電極
11 MEMS封止材料
12 MEMSキャビティ
13 ガラスマスク(集積転写基板)
14 微細配線パターン
15 露光エネルギー
16 コンタクトビア
17、20 開口部
18 多層金属層
19 レジスト膜
21 PbSnはんだ合金
100 従来の集積半導体装置(擬似SOCチップ)
200 回路配線基板
300 そり(応力変形)
Claims (6)
- 集積素子回路または素子外形寸法の異なる複数個の半導体素子と、
前記複数個の半導体素子の間に配置される絶縁材料と、
前記複数個の半導体素子と前記絶縁材料上に全体的に配置される有機絶縁膜と、
前記有機絶縁膜上に配置され、前記複数個の半導体素子を互いに接続する微細薄膜配線と、
前記複数個の半導体素子が配置されている領域上に選択的に配置されるI/O電極と、
前記I/O電極上に形成されるバンプ電極と、を備えたこと、
を特徴とする集積半導体装置。 - 前記I/O電極は、前記半導体素子の中心点から最大距離を除いて配置されること、を特徴とする請求項1に記載の集積半導体装置。
- 前記複数個の半導体素子のうち、少なくとも1つは電気機械素子であること、を特徴とする請求項1または2に記載の集積半導体装置。
- 前記集積半導体装置は、
前記バンプ電極により、回路配線基板上にフリップチップ実装されること、を特徴とする請求項1〜3のいずれか一項に記載の集積半導体装置。 - 前記絶縁材料は、少なくともシリカフィラを含有するエポキシ樹脂、ポリイミド樹脂、および、ベンゾシクロブテン(BCB)のうち、少なくとも1つで構成されていること、を特徴とする請求項1〜4のいずれか一項に記載の集積半導体装置。
- 前記バンプ電極は、少なくともTi、Ni、Al、Cu、Au、Ag、Pb、Sn、Pd、Wを含む金属、または、これらの合金で構成されていること、を特徴とする請求項1〜5のいずれか一項に記載の集積半導体装置。
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Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2013073082A1 (ja) * | 2011-11-16 | 2013-05-23 | パナソニック株式会社 | 拡張型半導体チップ及び半導体装置 |
JP2014027180A (ja) * | 2012-07-27 | 2014-02-06 | Toshiba Corp | 電子回路および半導体部品 |
JP2015526559A (ja) * | 2012-08-13 | 2015-09-10 | ヘンケル アイピー アンド ホールディング ゲゼルシャフト ミット ベシュレンクテル ハフツング | 液体圧縮成型封止材料 |
US9397057B2 (en) | 2014-06-02 | 2016-07-19 | Kabushiki Kaisha Toshiba | Plurality of semiconductor devices in resin with a via |
US9607949B2 (en) | 2014-03-20 | 2017-03-28 | Kabushiki Kaisha Toshiba | Semiconductor device having semiconductor chips in resin and electronic circuit device with the semiconductor device |
JP2019525488A (ja) * | 2016-08-12 | 2019-09-05 | コーボ ユーエス,インコーポレイティド | 性能を向上させたウエハレベルパッケージ |
US20200235054A1 (en) | 2019-01-23 | 2020-07-23 | Qorvo Us, Inc. | Rf devices with enhanced performance and methods of forming the same |
US20210296199A1 (en) | 2018-11-29 | 2021-09-23 | Qorvo Us, Inc. | Thermally enhanced semiconductor package with at least one heat extractor and process for making the same |
US11152363B2 (en) | 2018-03-28 | 2021-10-19 | Qorvo Us, Inc. | Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process |
US20220139862A1 (en) | 2019-01-23 | 2022-05-05 | Qorvo Us, Inc. | Rf devices with enhanced performance and methods of forming the same |
US11387157B2 (en) | 2019-01-23 | 2022-07-12 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
US11646289B2 (en) | 2019-12-02 | 2023-05-09 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
US11705428B2 (en) | 2019-01-23 | 2023-07-18 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
US11710680B2 (en) | 2019-01-23 | 2023-07-25 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
US11923238B2 (en) | 2019-12-12 | 2024-03-05 | Qorvo Us, Inc. | Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive |
US11961813B2 (en) | 2022-01-11 | 2024-04-16 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
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Cited By (27)
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CN103650135A (zh) * | 2011-11-16 | 2014-03-19 | 松下电器产业株式会社 | 扩展型半导体芯片以及半导体装置 |
JPWO2013073082A1 (ja) * | 2011-11-16 | 2015-04-02 | パナソニック株式会社 | 拡張型半導体チップ及び半導体装置 |
US9136219B2 (en) | 2011-11-16 | 2015-09-15 | Panasonic Corporation | Expanded semiconductor chip and semiconductor device |
WO2013073082A1 (ja) * | 2011-11-16 | 2013-05-23 | パナソニック株式会社 | 拡張型半導体チップ及び半導体装置 |
JP2014027180A (ja) * | 2012-07-27 | 2014-02-06 | Toshiba Corp | 電子回路および半導体部品 |
US9406622B2 (en) | 2012-07-27 | 2016-08-02 | Kabushiki Kaisha Toshiba | Electronic circuit and semiconductor component |
US11578202B2 (en) | 2012-08-13 | 2023-02-14 | Henkel Ag & Co. Kgaa | Liquid compression molding encapsulants |
JP2015526559A (ja) * | 2012-08-13 | 2015-09-10 | ヘンケル アイピー アンド ホールディング ゲゼルシャフト ミット ベシュレンクテル ハフツング | 液体圧縮成型封止材料 |
US9607949B2 (en) | 2014-03-20 | 2017-03-28 | Kabushiki Kaisha Toshiba | Semiconductor device having semiconductor chips in resin and electronic circuit device with the semiconductor device |
US9397057B2 (en) | 2014-06-02 | 2016-07-19 | Kabushiki Kaisha Toshiba | Plurality of semiconductor devices in resin with a via |
JP7265052B2 (ja) | 2016-08-12 | 2023-04-25 | コーボ ユーエス,インコーポレイティド | 性能を向上させたウエハレベルパッケージ |
JP2022071128A (ja) * | 2016-08-12 | 2022-05-13 | コーボ ユーエス,インコーポレイティド | 性能を向上させたウエハレベルパッケージ |
JP7037544B2 (ja) | 2016-08-12 | 2022-03-16 | コーボ ユーエス,インコーポレイティド | 性能を向上させたウエハレベルパッケージ |
JP2019525488A (ja) * | 2016-08-12 | 2019-09-05 | コーボ ユーエス,インコーポレイティド | 性能を向上させたウエハレベルパッケージ |
US11152363B2 (en) | 2018-03-28 | 2021-10-19 | Qorvo Us, Inc. | Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process |
US11646242B2 (en) | 2018-11-29 | 2023-05-09 | Qorvo Us, Inc. | Thermally enhanced semiconductor package with at least one heat extractor and process for making the same |
US20210296199A1 (en) | 2018-11-29 | 2021-09-23 | Qorvo Us, Inc. | Thermally enhanced semiconductor package with at least one heat extractor and process for making the same |
US11942389B2 (en) | 2018-11-29 | 2024-03-26 | Qorvo Us, Inc. | Thermally enhanced semiconductor package with at least one heat extractor and process for making the same |
US11387157B2 (en) | 2019-01-23 | 2022-07-12 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
US20200235054A1 (en) | 2019-01-23 | 2020-07-23 | Qorvo Us, Inc. | Rf devices with enhanced performance and methods of forming the same |
US20220139862A1 (en) | 2019-01-23 | 2022-05-05 | Qorvo Us, Inc. | Rf devices with enhanced performance and methods of forming the same |
US11705428B2 (en) | 2019-01-23 | 2023-07-18 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
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US11961813B2 (en) | 2022-01-11 | 2024-04-16 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
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