JP6116476B2 - チップスタックを製造するための方法及びその方法を実施するためのキャリア - Google Patents
チップスタックを製造するための方法及びその方法を実施するためのキャリア Download PDFInfo
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- JP6116476B2 JP6116476B2 JP2013510503A JP2013510503A JP6116476B2 JP 6116476 B2 JP6116476 B2 JP 6116476B2 JP 2013510503 A JP2013510503 A JP 2013510503A JP 2013510503 A JP2013510503 A JP 2013510503A JP 6116476 B2 JP6116476 B2 JP 6116476B2
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- H01L2924/013—Alloys
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/181—Encapsulation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10T428/24752—Laterally noncoextensive components
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Micromachines (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Description
‐ 使用される接着剤の化学的安定性
‐ 使用される接着剤の熱的安定性
‐ 使用される接着剤の熱機械的安定性
‐ 使用される接着剤の透明性の欠如(位置合わせ精度)
‐ チップの位置合わせ精度(フローティング)
‐ 取り外しプロセスにおける温度
‐ 特に、低い自由表面エネルギーを有するアモルファスポリマー物質から成ること、
‐ 低濃度又は超低濃度の水酸基又はカルボン酸基を有する少なくとも表面上のシリコン、ガラス、及び/又は、金属表面に対する接着性が低い又は接着性がないものであること、
‐ 溶液から形成可能であること。
‐ 自由表面エネルギーを低下させるための例えばフッ素/アルキルホスホン酸塩又は(フルオロ)アルキルシラン等の疎水性オルガノシランを有するシリコン製の表面の化学処理、又は、
‐ 支持領域内への又は支持領域としての永続的な接着防止コーティングを形成するためのキャリア上への低自由表面エネルギーを有するコーティングの化学気相堆積(CVD,chemical vapor deposition)法。
11 支持領域
12 オフセット
13 充填材
14 接着領域
15 キャリア面
16 側縁
17 ステージ
18 接触表面
19 充填層
20 ベース層
21 導電経路
22 接触パッド
24 チップ面
25 位置合わせマーク
26 ベース部分
27 露光サイト
30 チップ
31 チップスタック
32 チップスタック縁
33 チップ層
34 ハイブリッドウェーハ
35 ハイブリッドウェーハ縁
36 バンプ
37 チップ縁
38 チップ位置合わせマーク
40 層物質
50 末端バンプ
90 フォトマスク
Claims (12)
- チップスタック(31)を製造するための方法であって、
キャリア(10)のキャリア面(15)にベース層(20)をスピン若しくはスプレーコーティング又はラミネート加工によって適用するステップと、
前記ベース層(20)の上にチップスタック(31)を構築するステップと、
前記ベース層(20)から前記キャリア(10)を取り外すステップとを備え、
前記キャリア面(15)の上に、接着性の接着領域(14)と低接着性の支持領域(11)とが設けられて、前記ベース層(20)が、少なくとも主に前記支持領域(11)の表面全体にわたって適用され、
前記接着領域(14)内の前記キャリア面(15)の上であって、前記キャリア面(15)に対して後退させたオフセット(12)の上に、前記キャリア面(15)と同一平面で、選択的可溶性の充填材(13)が存在し、
前記ベース層(20)が少なくとも部分的に前記チップスタック(31)の一部分となる、方法。 - 前記ベース層(20)が、前記支持領域(11)の表面全体にわたって適用され、前記接着領域(14)に対して少なくとも部分的に適用される、請求項1に記載の方法。
- 前記チップスタック(31)が、特に切断によって、前記チップスタック(31)が前記キャリア(10)に接続したままであるように、前記キャリア(10)の取り外しの前に分離される、請求項1に記載の方法。
- 前記ベース層(20)を形成する物質がフレキシブルである、請求項1に記載の方法。
- 特に前記チップスタック(31)を構築する前に、ファンアウト結合構造(21)が前記ベース層(20)内に形成される、請求項1に記載の方法。
- 前記チップスタック(31)を構築する前に、前記キャリア面(15)の反対側のチップ面(24)の上に、前記チップスタック(31)を前記ファンアウト結合構造(21)に電気的に結合するための接触パッド(22)を適用する、請求項5に記載の方法。
- 前記チップスタック(31)の構築の前又は間に、特に請求項5に記載のファンアウト結合構造(21)の導入と同時に、前記ベース層(20)の上の前記コンタクトパッド(22)及び/又は前記チップスタック(31)の位置決め/配置のための位置合わせマーク(25)が、特に前記チップスタック(31)の縁(32)と同一平面で、前記ベース層(20)の中/上に存在している、請求項5に記載の方法。
- 前記チップスタック(31)が、結合によって前記ベース層(20)の上に直接固定される、請求項1に記載の方法。
- 前記チップスタック(31)を構築した後であって且つ前記キャリア(10)を取り外す前に、前記チップスタックを、前記ベース層(20)の物質に特に対応する層物質(40)で埋め込む、請求項1から8のいずれか一項に記載の方法。
- 前記キャリア(10)を、特に前記接着層(14)の接着力を低下させることによって、好ましくは前記充填材(13)の選択的分解によって、前記キャリア(10)の側縁から取り外す、請求項1に記載の方法。
- 前記ベース層(20)のベース部分(26)が、各チップスタック(31)の一部を形成する、請求項1から10のいずれか一項に記載の方法。
- 接着性の接着領域(14)及び低接着性の支持領域(11)がキャリア面(15)の上に設けられているキャリア(10)であって、ベース層(20)が少なくとも主に前記支持領域(11)の表面全体にわたって適用され、前記接着領域(14)内の前記キャリア面(15)の上において、前記キャリア面(15)に対して後退させたオフセット(12)の上に、選択的可溶性充填材(13)が存在している、キャリア(10)。
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PCT/EP2010/003119 WO2011144226A1 (de) | 2010-05-20 | 2010-05-20 | Verfahren zur herstellung von chipstapeln sowie einen träger für die durchführung des verfahrens |
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JP2013535093A JP2013535093A (ja) | 2013-09-09 |
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SG2014013569A (en) * | 2012-08-20 | 2014-10-30 | Ev Group E Thallner Gmbh | Packaging for microelectronic components |
JP2015005637A (ja) * | 2013-06-21 | 2015-01-08 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置 |
US9599670B2 (en) * | 2013-09-18 | 2017-03-21 | Taiwan Semiconductor Manufacturing Company Ltd | Circuit and method for monolithic stacked integrated circuit testing |
US9572257B2 (en) | 2014-07-31 | 2017-02-14 | Keysight Technologies, Inc. | Multi-layered printed circuit board having core layers including indicia |
US10529637B1 (en) * | 2018-10-31 | 2020-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit package and method of forming same |
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JP3544902B2 (ja) * | 1999-09-16 | 2004-07-21 | 株式会社東芝 | 半導体装置およびその製造方法 |
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JP4379102B2 (ja) * | 2003-12-12 | 2009-12-09 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
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CN103155146A (zh) | 2013-06-12 |
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SG185491A1 (en) | 2012-12-28 |
KR101665302B1 (ko) | 2016-10-24 |
US20130065360A1 (en) | 2013-03-14 |
CN103155146B (zh) | 2016-06-08 |
TWI563595B (en) | 2016-12-21 |
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