TWI713571B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI713571B
TWI713571B TW105126825A TW105126825A TWI713571B TW I713571 B TWI713571 B TW I713571B TW 105126825 A TW105126825 A TW 105126825A TW 105126825 A TW105126825 A TW 105126825A TW I713571 B TWI713571 B TW I713571B
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Taiwan
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copper
layer
insulating layer
wiring
semiconductor device
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TW105126825A
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TW201724449A (zh
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満倉一行
鳥羽正也
岩下健一
浦島航介
蔵渕和彦
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日商昭和電工材料股份有限公司
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Abstract

本發明提供一種可以良好的良率且低成本來製造晶片彼此的傳送優異的高密度的半導體裝置的製造方法。半導體裝置的製造方法包括：絕緣層形成步驟，於基板1上形成具有槽部4的絕緣層3；銅層形成步驟，於絕緣層3上以填埋槽部4的方式形成銅層5a；以及去除步驟，以保留槽部4內的銅層部分之方式利用飛切法將絕緣層3上的銅層5a去除。

Description

半導體裝置及其製造方法
本揭示是有關於一種半導體裝置及其製造方法。更詳細而言，本揭示是有關於一種用於效率良好地、低成本地製造微細化及高密度化的要求高的半導體裝置的製造方法，及利用該製造方法而製造的半導體裝置。
以半導體封裝的高密度化及高性能化為目的，提出將性能不同的晶片混載於一個封裝的實施形態。於該情況下，於成本方面優異的晶片間的高密度互連（interconnect）技術變得重要（例如參照專利文獻1）。
藉由於封裝上利用倒裝晶片（flip-chip）安裝將不同的封裝積層而連接的堆疊式封裝（package on package）被廣泛採用於智慧型手機及平板電腦終端中（例如參照非專利文獻1及非專利文獻2）。
進而，作為用於以高密度安裝多個晶片的其他形態，提出使用具有高密度配線的有機基板的封裝技術（有機中介層（interposer））、具有封裝通孔（Through Mold Via，TMV）的扇出（fan-out）型封裝技術（扇出型晶圓級封裝（Fan-out Wafer-level Package，FO-WLP））、使用矽中介層或玻璃中介層的封裝技術、使用矽通孔（Through Silicon Via，TSV）的封裝技術、或者將埋入基板中的晶片用於晶片間傳送的封裝技術等。
尤其在有機中介層及FO-WLP中，於將半導體晶片彼此並聯地搭載的情況下，為了以高密度使該半導體晶片彼此導通而需要微細配線層（例如參照專利文獻2）。 [現有技術文獻] [專利文獻]
[專利文獻1]日本專利特表2012-529770號公報 [專利文獻2]美國專利申請公開第2011/0221071號說明書 [非專利文獻]
[非專利文獻1]「作為PoP基礎封裝的封裝通孔（TMV）的應用，電子元件及技術會議（ECTC）」（Application of Through Mold Via（TMV）as PoP Base Package, Electronic Components and Technology Conference（ECTC））, 2008 [非專利文獻2]「利用嵌入式晶圓級PoP（eWLB-PoP）技術的高級薄型解決方案」（Advanced Low Profile PoP Solution with Embedded Wafer Level PoP（eWLB-PoP）Technology）, ECTC, 2012
[發明所欲解決之課題] 為了形成微細配線，通常需要利用濺鍍的種晶層形成、抗蝕劑形成、電鍍、抗蝕劑去除、及不需要的種晶層的去除等步驟，製程成本成為課題。因而，於微細配線的形成中，強烈期望由所述步驟的簡化而帶來的低成本化。
本揭示的目的在於提供一種可以良好的良率且低成本而製造的晶片彼此的傳送優異的高密度的半導體裝置及其製造方法。 [解決課題之手段]
本發明者等人為了解決所述課題而進行研究，結果發現了具有優異的特性的製造方法。
本實施形態的第1態樣是一種半導體裝置的製造方法，其包括：絕緣層形成步驟，於基板上形成具有槽部的絕緣層；銅層形成步驟，於絕緣層上以填埋槽部的方式形成銅層；以及去除步驟，以保留槽部內的銅層部分之方式利用飛切法將絕緣層上的銅層去除。
根據本實施形態的第1態樣，當形成配線（槽部內的銅層部分）時不需要化學機械研磨（Chemical Mechanical Polishing，CMP），與現有的製程相比，可提高良率，且不會產生配線（銅）的凹陷（dishing），因此可高密度地形成配線，並且可大幅度地減少製造成本。
本實施形態的第2態樣是一種半導體裝置，其是將半導體元件搭載於設於基板上的配線體而成，配線體具有相互積層的多個配線層，於多個配線層的各個中設置有於配線層的一面側具有槽部的絕緣層、及以填埋槽部的方式形成的銅配線，一面側的絕緣層及銅配線的表面粗糙度為0.03 μm以上且0.1 μm以下。
根據本實施形態的第2態樣，各配線層的一面側的絕緣層及銅配線的表面粗糙度為0.03 μm以上且0.1 μm以下。與使用CMP而使絕緣層及銅配線露出時的表面粗糙度相比，該表面粗糙度成為大的值。因此，當製造所述半導體裝置時，亦可於槽部內的銅配線的形成時不使用CMP，故與現有的製程相比，可提高良率，且不會產生銅配線的凹陷，因此可高密度地形成配線，並且可大幅度地減少製造成本。此外，藉由多個配線層的各自的一面側的絕緣層及銅配線具有所述表面粗糙度，可提高經由該一面側而接觸的配線層彼此的密接性。藉此可抑制配線層的剝離。 [發明的效果]
根據本實施形態，可以良好的良率且低成本來提供晶片彼此的傳送優異的高密度的半導體裝置。
以下，參照圖式對本實施形態進行詳細說明。以下的說明中，於同一或相當部分標註同一符號，並省略重複的說明。另外，只要無特別說明，則將上下左右等位置關係設為基於圖式所示的位置關係者。進而，圖式的尺寸比率並不限於圖示的比率。
於在記載及請求項中利用「左」、「右」、「正面」、「背面」、「上」、「下」、「上方」、「下方」、「第1」、「第2」等用語的情況下，該些為旨在進行說明者，未必是指永久地為該相對位置。另外，「層」這一語句當以平面圖進行觀察時，除了形成於整個面上的形狀的結構，亦包含形成於一部分中的形狀的結構。另外，「步驟」這一語句並非獨立的步驟，即便於無法明確地與其他步驟加以區分的情況下，若達成該步驟的所期望的目的，則亦包含於本用語中。另外，使用「～」所示的數值範圍表示包含「～」的前後所記載的數值分別作為最小值及最大值的範圍。另外，於本說明書中階段性地記載的數值範圍中，某一階段的數值範圍的上限值或下限值可置換為其他階段的數值範圍的上限值或下限值。
對製造本揭示的一實施形態中的圖6所示的半導體封裝（半導體裝置）101、及圖16所示的半導體封裝（半導體裝置）103的方法進行說明。再者，本揭示的半導體裝置的製造方法於需要微細化及多針化的形態中尤其適合。尤其，本揭示的製造方法可用於需要用以混載異種晶片的中介層的封裝形態。
參照圖1至圖6來對半導體封裝101的製造方法進行說明。
如圖1所示，首先，於基板1上形成第1銅配線2（銅配線形成步驟）。藉此，於基板1的上表面的一部分形成經圖案化的第1銅配線2。
基板1並無特別限定，為矽板、玻璃板、不鏽鋼（Stainless Steel，SUS）板、包含玻璃纖維布的基板（例如預浸布等）、或密封半導體元件的樹脂製的基板等。基板1亦可為25℃下的儲藏彈性係數為1 GPa以上的基板。
基板1的厚度t0例如為0.2 mm～2.0 mm。於厚度t0為0.2 mm以上的情況下，基板1的操作性變得良好。於厚度t0為2.0 mm以下的情況下，有可將基板1的材料費抑制得低的傾向。
基板1可為晶圓狀亦可為面板狀。俯視時的基板1的尺寸（size）並無特別限定。於基板1為晶圓狀的情況下，基板1的直徑例如為200 mm、300 mm或450 mm。於基板1為面板狀的情況下，基板1例如為一邊為300 mm～700 mm的矩形面板。
第1銅配線2例如可利用噴墨法、網版印刷法、或噴塗法來形成。例如，使用印刷裝置，並將銅膏塗佈於基板1上，藉此可於基板1上形成第1銅配線2。另外，藉由銅箔的層壓、濺鍍、或鍍敷處理而形成銅層，經由抗蝕劑圖案進行該蝕刻，藉此亦可形成第1銅配線2。藉由使用銅膏形成第1銅配線2，不需要用於配線形成的種晶層，且亦可省略抗蝕劑形成步驟及抗蝕劑去除步驟。因此，與形成種晶層的現有的製程相比，可大幅度地減少製造成本。
銅膏為將銅粒子分散於溶劑中的材料。使銅粒子分散的溶劑並無特別限定，可使用包含具有醇基、酯基、或胺基等的化合物的溶劑。
銅粒子的平均粒徑並無特別限定，例如為10 nm～500 nm。就分散性的觀點而言，銅粒子的平均粒徑較佳為20 nm～300 nm。另外，就燒結性的觀點而言，銅粒子的平均粒徑更佳為50 nm～200 nm。所謂本說明書中的銅粒子的平均粒徑，為對隨機選擇的200個銅粒子進行測定的長軸的長度的算術平均值。再者，銅粒子的長軸的長度例如可使用掃描式電子顯微鏡來測定。
銅膏的黏度可根據使用方法來選擇。例如，於使用網版印刷法而將銅膏塗佈於基板1的情況下，該銅膏的黏度只要為0.1 Pa·s～30 Pa·s即可。另外，於使用噴墨印刷法或噴塗法的情況下，銅膏的黏度只要為0.1 mPa·s～30 mPa·s即可。
繼而，如圖2所示，於基板1上形成覆蓋第1銅配線2的絕緣層3（絕緣層形成步驟）。
絕緣層3例如是使用液狀或膜狀的絕緣材料而形成。就膜厚平坦性及成本的觀點而言，較佳為使用膜狀的絕緣材料。另外，絕緣層3中可含有填料。就形成微細的槽部4的觀點而言，該填料的平均粒徑例如為500 nm以下。相對於絕緣材料的總量的填料的含量例如只要小於1質量%即可。再者，絕緣層3中亦可不含有填料。
於使用所述膜狀的絕緣材料來形成絕緣層3的情況下，例如藉由層壓步驟將該絕緣材料貼附於形成有第1銅配線2的基板1上。該層壓步驟例如是將溫度設定為40℃～120℃而進行。因此，作為膜狀的絕緣材料，較佳為使用能夠在40℃～120℃下進行層壓的感光性絕緣膜。藉由將能夠層壓的溫度設為40℃以上，可抑制室溫下的感光性絕緣膜的黏性（黏著性）變強，並且可維持感光性絕緣膜的良好的操作性。藉由將感光性絕緣膜的能夠層壓的溫度設為120℃以下，可抑制於層壓步驟後的感光性絕緣膜中產生翹曲。再者，所謂「室溫」表示25℃左右。
就形成後述的微細的槽部4的觀點而言，絕緣層3的厚度例如為10 μm以下。另外，絕緣層3的厚度較佳為5 μm以下，更佳為3 μm以下。另外，就電氣可靠性的觀點而言，絕緣層3的厚度例如為1 μm以上。
就抑制絕緣層3的翹曲的觀點而言，絕緣層3的硬化後的熱膨脹係數例如為80 ppm/℃以下。就抑制回流焊步驟及溫度循環試驗中的剝離或裂紋的觀點而言，該熱膨脹係數較佳為70 ppm/℃以下。另外，就提高絕緣層3的應力緩和性並且容易形成微細的槽部4的觀點而言，該熱膨脹係數更佳為20 ppm/℃以上。
形成絕緣層3後於該絕緣層3形成槽部4（槽部形成步驟）。槽部4的兩側壁是藉由絕緣層3而形成。第1銅配線2的上表面的一部分自一部分的槽部4中的兩側壁之間露出。槽部4例如具有0.5 μm～5 μm的線寬。
具體而言，於槽部形成步驟中，作為具有剖面大致矩形形狀的槽部4，形成以與第1銅配線2重疊的方式形成的多個第1槽部4a、及以不與第1銅配線2重疊的方式形成的多個第2槽部4b。第1槽部4a以使第1銅配線2的上表面露出的方式設置。因此，第1槽部4a的兩側面（兩側壁）由絕緣層3構成，第1槽部4a的底表面由第1銅配線2構成。因而，於槽部形成步驟結束後的狀態下，第1銅配線2的上表面的一部分自第1槽部4a的兩側壁之間露出。另一方面，第2槽部4b的兩側面（兩側壁）及底表面由絕緣層3構成。再者，只要第1槽部4a的底表面的至少一部分由第1銅配線2構成即可，第1槽部4a的底表面的一部分亦可由絕緣層3構成。
作為槽部4的形成方法，例如可列舉雷射剝蝕、光微影、或壓印等。就槽部4的微細化及成本的觀點而言，較佳為進行曝光及顯影的光微影。於使用光微影的情況下，較佳為使用具有絕緣性的膜狀的感光性樹脂材料（感光性絕緣膜）作為絕緣層3。
於絕緣層3為感光性絕緣膜的情況下，可不使用抗蝕劑遮罩而對絕緣層3直接進行曝光及顯影來形成槽部4。於該情況下，可省略抗蝕劑形成步驟及抗蝕劑去除步驟，故可實現步驟的簡化。再者，感光性樹脂材料可為負型，亦可為正型。
作為於所述光微影中對感光性樹脂材料進行曝光的方法，可使用公知的投影曝光方式、接觸曝光方式、或直接描繪曝光方式等。另外，為了對感光性樹脂材料進行顯影，例如可使用碳酸鈉、或四甲基氫氧化銨（Tetramethyl Ammonium Hydroxide，TMAH）等的鹼性水溶液。
於槽部形成步驟中，亦可於形成槽部4後進而對絕緣層3進行加熱硬化。例如將加熱溫度設定為100℃～200℃，將加熱時間設定為30分鐘～3小時後，對絕緣層3進行加熱硬化。
繼而，如圖3所示，以覆蓋槽部4的方式形成銅層5a（銅層形成步驟）。
具體而言，例如藉由將銅膏塗佈於絕緣層3的上表面，以填埋槽部4（第1槽部4a及第2槽部4b）的方式將該銅膏塗佈於絕緣層3上（塗佈步驟）。而且，對經塗佈的銅膏進行燒結處理，而獲得經燒結處理的銅層5a（燒結步驟）。銅層5a（尤其是槽部4內的銅層部分）電氣連接於自槽部4露出的第1銅配線2。此處，所謂藉由對銅膏進行燒結而獲得的銅層5a、與藉由現有的濺鍍、鍍敷等而獲得的銅，認為密度等不同。因此，例如可基於剖面圖來判斷兩者。藉由使用銅膏而形成銅層5a，不需要用於形成後述的第2銅配線5的種晶層，且亦可省略抗蝕劑形成步驟及抗蝕劑去除步驟。因此，與形成種晶層的現有的製程相比，可大幅度地減少製造成本。
作為銅膏的塗佈方法，例如可列舉噴墨法、印刷法、旋塗法、或噴塗法等。
另外，作為銅膏的燒結方法，例如可列舉利用加熱的燒結、或利用氙氣閃光燈的光燒結。於藉由加熱對銅膏進行燒結的情況下，例如可於氮氣環境下、氫存在下、或酸存在下進行銅膏的燒結步驟。就獲得細密且體積電阻值低的銅層的觀點而言，較佳為於酸存在下進行燒結步驟。所謂酸存在下，是指於氣體中存在已揮發的酸。另外，作為酸，可使用甲酸、乙酸等，較佳為使用甲酸。就以更短的時間獲得細密且體積電阻值低的銅層的觀點而言，更佳為於氮氣與甲酸混合存在的環境下進行燒結步驟。氮氣中的甲酸含量例如為0.005體積%～10體積%。就獲得均質的銅層的觀點而言，氮氣中的甲酸含量較佳為0.01體積%～5體積%。
就可以短時間進行燒結且可抑制絕緣層的熱改質的觀點而言，銅膏的燒結溫度例如可設定為80℃～200℃。就使體積電阻值降低的觀點而言，較佳為將燒結溫度設定為120℃～200℃。另外，就獲得更細密的銅層的觀點而言，更佳為將燒結溫度設定為120℃～180℃。
就傳送效率的觀點而言，燒結的銅層的體積電阻率例如為40 μΩ·cm以下。就抑制發熱量的觀點而言，該體積電阻率較佳為30 μΩ·cm以下。另外，就可靠性的觀點而言，該體積電阻率更佳為20 μΩ·cm以下。再者，該體積電阻率通常為3 μΩ·cm以上。
繼而，如圖4所示，藉由飛切法將絕緣層3的上部的銅層5a去除（去除步驟）。藉此，填埋於槽部4內的銅層部分露出，形成具有第1銅配線2、絕緣層3、及填埋於該絕緣層3上的銅層部分的配線層30。
具體而言，以保留槽部4內的銅層部分之方式利用飛切法將絕緣層3上的銅層5a去除。藉此，塗佈於設於絕緣層3的槽部4內並經燒結的銅層部分露出。
再者，槽部4中的第1槽部4a內的銅層部分亦可稱為電氣連接於第1銅配線2的第2銅配線5。即，所述去除步驟中，將銅層5a的一部分去除而形成第2銅配線5。如圖3所示，銅層5a是形成於絕緣層3及槽部4的整個面上。換言之，亦可於應形成第2銅配線5的區域（槽部4）以外的區域形成有銅層5a。因此，所述去除步驟可稱為將銅層5a中的形成於槽部4內以外的區域的銅層部分去除的步驟。
於飛切法中例如使用利用金剛石鑽頭的研削裝置。作為具體例，可使用300 mm晶圓對應的自動平整機（automatic surface planer）（迪士科（Disco）股份有限公司製造，商品名「DAS8930」）。再者，利用飛切法的銅層5a的所述去除亦可稱為平坦化處理。另外，所述去除步驟除飛切法以外亦可組合蝕刻等。
當藉由利用飛切法的研削而以保留槽部4內的銅層部分之方式將絕緣層3上的銅層5a去除時，亦可包含絕緣層3的一部分在內而進行去除。所謂絕緣層3的一部分，為絕緣層3的上表面及該上表面附近的區域。絕緣層3的上表面附近的區域的厚度例如被設定為絕緣層3的整體厚度中的10%以內。藉由如此般將絕緣層3的一部分去除，可減少經由銅的污染，故可靠性提高。再者，於絕緣層3的一部分被去除的同時，槽部4內的第2銅配線5的一部分亦被去除。
於利用飛切法而研削的配線層30中，構成與基板1為相反側的面的絕緣層3及第2銅配線5的表面粗糙度（由日本工業標準（Japanese Industrial Standards，JIS）B 0601 2001規定的算術平均粗糙度（Ra））例如分別為0.03 μm以上且0.1 μm以下。為了將該些的表面粗糙度設為0.03 μm以上且0.1 μm以下，較佳為使用平整機對第2銅配線5、絕緣層3、及絕緣層3上部的銅層5a進行物理性研削。作為平整機，例如可使用自動平整機（迪士科（Disco）股份有限公司製造，商品名「DAS8930」）。例如於傳送速度1 mm/s、主軸轉數2000 rpm的條件下，利用飛切法進行研削。研削後的絕緣層3及第2銅配線5的表面粗糙度例如使用雷射顯微鏡（奧林巴斯（Olympus）股份有限公司製造的「LEXT OLS3000」），對包含絕緣層3與第2銅配線5的100 μm×100μm的範圍進行掃描而測定。再者，例如於藉由CMP將上部的銅層5a去除而使絕緣層3及第2銅配線5露出的情況下，絕緣層3及第2銅配線5的各自的表面粗糙度成為20 nm以下（0.02 μm以下）。
繼而，如圖5所示，藉由反覆進行所述銅配線形成步驟、所述絕緣層形成步驟、所述槽部形成步驟、所述銅層形成步驟、及所述去除步驟，於基板1上形成積層有多個配線層30而成的高密度配線層（配線體）100。再者，多個配線層30的與基板1為相反側的表面分別利用飛切法來進行研削。因此，多個配線層30的與基板1為相反側的面的表面粗糙度為0.03 μm以上且0.1 μm以下。
具體而言，如圖5所示，於形成第2銅配線5後在絕緣層3及第2銅配線5上形成另一第1銅配線2。此處，以電氣連接於第2銅配線5的方式形成另一第1銅配線2。繼而，以覆蓋另一第1銅配線2的方式形成具有另一槽部4的另一絕緣層3。另一槽部4可以與槽部4重疊的方式設置，亦可以不與槽部4重疊的方式設置。繼而，與所述銅層形成步驟及所述去除步驟同樣地進行而形成另一第2銅配線5。另一第2銅配線5以經由另一第1銅配線2與第2銅配線5而電氣連接於第1銅配線2的方式設置。
繼而，如圖6所示，使用底部填充材料10而將半導體元件7搭載於所獲得的高密度配線層100上，從而形成半導體封裝101。
於對高密度配線層100的半導體元件7的搭載中，於將半導體元件7搭載於高密度配線層100之前，首先，於高密度配線層100上形成電極9。該高密度配線層100的電極9例如是使用與所述銅配線形成步驟同樣的方法來形成。
電極9以電氣連接於在高密度配線層100中露出的另一第2銅配線5的方式設置。另外，於電極9使用與所述銅配線形成步驟同樣的方法來形成的情況下，該電極9由銅構成。
繼而，使半導體元件7的電極8與高密度配線層100的電極9進行金屬連接。作為使電極8與電極9進行金屬連接的方法，例如可列舉於電極8與電極9之間形成焊料8a，藉由該焊料8a的接合而使電極8與電極9相互進行金屬連接。此時，亦可藉由加熱壓接並使用焊料8a來使電極8與電極9進行金屬連接。焊料8a例如為球狀的形狀。焊料8a例如可藉由鍍敷處理或印刷法來形成。
作為用於將半導體元件7固定於高密度配線層100上的底部填充材料10，例如可使用毛細管底部填充膠（Capillary Underfill，CUF）、成型底部填充膠（Mold Underfill，MUF）、非導電膏（Non-conductive Paste，NCP）、非導電膜（Non-conductive Film，NCF）、或感光性底部填充膠。
半導體元件7並無特別限定，例如除圖形處理單元（Graphics Processing Unit，GPU）、動態隨機存取記憶體（Dynamic random-access memory，DRAM）或靜態隨機存取記憶體（Static random-access memory，SRAM）等揮發性記憶體、快閃記憶體等非揮發性記憶體、射頻（Radio Frequency，RF）晶片以外，可使用矽光子晶片（silicon photonics chip）、微機電系統（Microelectro Mechanical system，MEMS）、感測晶片（sensor chip）等。另外，可使用具有TSV的半導體元件。
作為半導體元件7，亦可使用積層有半導體元件而成者。例如，可使用利用TSV而積層的半導體元件。半導體元件7的厚度例如為200 μm以下。就將半導體封裝101薄型化的觀點而言，半導體元件7的厚度較佳為100 μm以下。另外，就半導體封裝101的操作性的觀點而言，例如只要半導體元件7的厚度為30 μm以上即可。
以下，參照圖7至圖16來對半導體封裝103的製造方法進行說明。
如圖7所示，首先，於作為暫時基板的載體14上形成暫時固定層11（暫時固定層形成步驟）。
暫時固定層11的形成方法並無特別限定，例如可列舉旋塗、噴塗、或層壓等。暫時固定層11例如具有含有聚醯亞胺、聚苯并噁唑、矽、氟等非極性成分的樹脂、含有藉由加熱或紫外線照射（UV（Ultraviolet）照射）而體積膨脹或起泡的成分的樹脂、含有藉由加熱或UV照射而進行交聯反應的成分的樹脂、或藉由光照射而發熱的樹脂。
就可程度高地兼顧操作性與自載體14的剝離容易性的觀點而言，暫時固定層11較佳為具有藉由增加光或熱等外部刺激而容易剝離的性質。就暫時固定層11不殘存於後述的半導體裝置上而能夠容易地剝離該暫時固定層11的觀點而言，暫時固定層11更佳為含有藉由加熱處理而體積膨脹的粒子。於將含有藉由加熱而體積膨脹或起泡的成分（起泡劑）的材料用於暫時固定層11的情況下，就後述的絕緣材料12的硬化溫度及燒結溫度的觀點而言，該起泡劑較佳為於200℃以上急劇地起泡或發生體積膨脹。
繼而，如圖8所示，於暫時固定層11上形成第1銅配線2（銅配線形成步驟）。
亦可將第1銅配線2設為與後述其他設於基板上的電極連接的連接用電極部。
繼而，如圖9所示，於暫時固定層11上形成覆蓋第1銅配線2的絕緣層3(絕緣層形成步驟)。
而且，於該絕緣層3上形成槽部4(槽部形成步驟)。
繼而，如圖10所示，將銅膏塗佈於槽部4。具體而言，藉由將銅膏塗佈於絕緣層3的上表面，以填埋槽部4的方式將銅膏塗佈於絕緣層3上(塗佈步驟)。而且，對經塗佈的銅膏進行燒結處理，而獲得經燒結處理的銅層5a(燒結步驟)。此處，獲得包括具有槽部4的絕緣層3、及形成於槽部4內並作為銅膏的燒結體的銅層5a，且具有暫時固定層11作為絕緣層3的下層的積層體。
繼而，如圖11所示，將絕緣層3的上部的銅層5a去除(去除步驟)。
於去除步驟中例如使用飛切法，以保留槽部4內的銅層部分之方式將絕緣層3上的銅層5a去除。
繼而，如圖12所示，藉由反覆進行所述銅配線形成步驟、所述絕緣層形成步驟、所述槽部形成步驟、所述塗佈步驟、所述燒結步驟及所述去除步驟，於暫時固定層11上形成高密度配線層100。
於圖12中，藉由與圖5同樣地於絕緣層3及第2銅配線5上依序形成另一第1銅配線2、另一絕緣層3、及另一第2銅配線5，於暫時固定層11上形成高密度配線層100。
繼而，如圖13所示，使用底部填充材料10而將半導體元件7搭載於所獲得的高密度配線層100上。
再者，於高密度配線層100上設有所述電極9，該電極9經由焊料8a而與半導體元件7的電極8電氣連接。
繼而，如圖14所示，以絕緣材料12來密封半導體元件7(密封步驟)。絕緣材料12可使用液狀、固體狀、或片狀的材料。絕緣材料12亦可與底部填充材料10兼用。
繼而，如圖15所示，將載體14及暫時固定層11剝離，從而獲得帶配線層的半導體元件102。藉由經過以上說明的步驟，可以更良好的良率且以容易獲得經濟的恩惠的方式製作晶片彼此的傳送優異的高密度的半導體裝置。
作為自高密度配線層100剝離載體14的方法，可列舉撕除(peel)剝離、滑動剝離、或加熱剝離等。另外，亦可於自高密度配線層100剝離載體14後，利用溶劑或電漿等來清洗高密度配線層100，將殘存的暫時固定層11去除。
於剝離載體14之前，作為提高暫時固定層11的剝離容易性的處理，亦可實施加熱處理或光照射等。
若為不阻礙半導體裝置的功能的範圍，則暫時固定層11亦可殘留於高密度配線層100上。再者，經剝離的載體14亦可進行再循環。
亦可於在載體14及暫時固定層11經剝離的帶配線層的半導體元件102中的第1銅配線2露出的面重新形成焊料或銅墊等的連接用電極部。再者，就提高傳送密度的觀點而言，配線層(第1銅配線及第2銅配線)可為多個。另外，就容易獲得經濟的恩惠的觀點而言，半導體元件7亦可包含多個。
新的連接用電極部的形成方法並無特別限定，例如可使用塗佈所述的銅膏並進行燒結處理的方法。除此以外，亦可使用利用熔融焊料的方法、或形成抗蝕劑而施加電鍍或無電鍍的方法來形成新的連接用電極部。新的連接用電極部可包含單一的金屬，亦可包含多種金屬。
新的連接用電極部例如包含金、銀、銅、鎳、銦、鈀、錫、或鉍等的至少任一者。
繼而，如圖16所示，將經絕緣材料12密封的帶配線層的半導體元件102切斷。藉此，由於可將經絕緣材料12密封的狀態的帶配線層的半導體元件102單片化而獲得多個，因此更容易獲得經濟的恩惠。而且，將經密封的帶配線層的半導體元件102分別搭載於基板13，從而製作半導體封裝103。
基板13例如具有包括配線24的基板芯材料21、形成於基板芯材料21上的絕緣層22、及自絕緣層22的一部分露出且連接於配線24的基板連接材料23。另外，於基板13上以基板連接材料23露出的方式形成有底部填充材料25。底部填充材料25設於基板13與帶配線層的半導體元件102之間，具有使基板13與帶配線層的半導體元件102之間的應力緩和的功能。
所謂帶配線層的半導體元件102的絕緣層3、與基板13所具有的絕緣層22，可由相互相同的材料構成，亦可由相互不同的材料構成。同樣地，所謂底部填充材料10與底部填充材料25，可由相互相同的材料構成，亦可由相互不同的材料構成。就可抑制半導體封裝103的翹曲的觀點而言，基板13的熱膨脹係數例如只要為30ppm/℃以下即可。就抑制回流焊步驟及溫度循環試驗中的剝離或裂紋的觀點而言，該熱膨脹係數較佳為20ppm/℃以下。
再者，於現有的製造半導體裝置的製程中，在使用銅膏作為銅配線的材料的情況下，存在有機材料(例如形成絕緣層3的有機材料)與該銅膏的密接性變得不充分的情況、及作為銅膏的燒結體的銅配線的強度變得不充分的情況。然而，藉由使用所述實施形態中的半導體裝置的製造方法，能夠形成可充分表現出銅配線的耐回流焊性、耐溫度循環性、及可撓性等，且具有高的可靠性的銅配線。
以上對本揭示的一實施形態的半導體裝置的製造方法進行了說明，但本揭示並不限定於所述實施形態，亦可於不超出其主旨的範圍內進行適當變更。
於所述實施形態中，銅層5a是使用銅膏而形成，但並不限於此。例如亦可使用濺鍍、電鍍、及無電鍍的至少任一者來形成銅層5a。或者，亦可藉由將濺鍍、電鍍、及無電鍍的至少任一者與銅膏的塗佈步驟及燒結步驟組合來形成銅層5a。再者，所謂使用銅膏而獲得的銅層、與藉由現有的濺鍍或鍍敷等而獲得的銅層，認為銅的密度等相互不同。因此，例如可藉由對剖面圖進行觀察來判斷是否為使用銅膏而獲得的銅層。
另外，於所述實施形態中，藉由對絕緣層3直接進行曝光及顯影來形成槽部4，但並不限於此。例如，絕緣層3的光微影亦可使用抗蝕劑遮罩來進行。
1、13‧‧‧基板 2‧‧‧第1銅配線 3、22‧‧‧絕緣層 4‧‧‧槽部 4a‧‧‧第1槽部 4b‧‧‧第2槽部 5‧‧‧第2銅配線 5a‧‧‧銅層 7‧‧‧半導體元件 8、9‧‧‧電極 8a‧‧‧焊料 10、25‧‧‧底部填充材料 11‧‧‧暫時固定層 12‧‧‧絕緣材料 14‧‧‧載體 21‧‧‧基板芯材料 23‧‧‧基板連接材料 24‧‧‧配線 30‧‧‧配線層 100‧‧‧高密度配線層（配線體） 101、103‧‧‧半導體封裝（半導體裝置） 102‧‧‧帶配線層的半導體元件 t0‧‧‧厚度
圖1是示意性地表示於基板上形成第1銅配線的狀態的剖面圖。 圖2是示意性地表示於絕緣層形成槽部的狀態的剖面圖。 圖3是示意性地表示將銅膏塗佈於槽部後加以燒結而形成銅層的狀態的剖面圖。 圖4是示意性地表示將絕緣層的上部的銅層去除而形成第2銅配線的狀態的剖面圖。 圖5是示意性地表示形成有另一第1銅配線、另一絕緣層、及另一第2銅配線的狀態的剖面圖。 圖6是示意性地表示使用底部填充材料而將半導體元件搭載於高密度配線層的狀態的剖面圖。 圖7是示意性地表示於載體上形成暫時固定層的狀態的剖面圖。 圖8是示意性地表示形成第1銅配線的狀態的剖面圖。 圖9是示意性地表示於絕緣層形成槽部的狀態的剖面圖。 圖10是示意性地表示將銅膏塗佈於槽部後加以燒結而形成第1銅層的狀態的剖面圖。 圖11是示意性地表示將第1絕緣層的上部的銅層去除的狀態的剖面圖。 圖12是示意性地表示形成有另一第1銅配線、另一絕緣層、及另一第2銅配線的狀態的剖面圖。 圖13是示意性地表示使用底部填充材料而將半導體元件搭載於高密度配線層的狀態的剖面圖。 圖14是示意性地表示以絕緣材料密封半導體元件的狀態的剖面圖。 圖15是示意性地表示將載體及暫時固定層自帶配線層的半導體元件剝離的狀態的剖面圖。 圖16是示意性地表示將經密封的帶配線層的半導體元件搭載於基板的狀態的剖面圖。
1‧‧‧基板
2‧‧‧第1銅配線
3‧‧‧絕緣層
5‧‧‧第2銅配線
7‧‧‧半導體元件
8、9‧‧‧電極
8a‧‧‧焊料
10‧‧‧底部填充材料
100‧‧‧高密度配線層
101‧‧‧半導體封裝

Claims (10)

  1. 一種半導體裝置的製造方法，其包括：絕緣層形成步驟，於基板上形成具有槽部的絕緣層；銅層形成步驟，於所述絕緣層上以填埋所述槽部的方式形成銅層；以及去除步驟，以保留所述槽部內的所述銅層部分之方式利用飛切法將所述絕緣層上的所述銅層去除，所述去除步驟後的所述絕緣層及所述銅層部分的表面粗糙度為0.03μm以上且0.1μm以下。
  2. 如申請專利範圍第1項所述的半導體裝置的製造方法，其中於所述去除步驟中，包含所述絕緣層的一部分在內而利用所述飛切法進行去除。
  3. 如申請專利範圍第1項或第2項所述的半導體裝置的製造方法，其中所述絕緣層為使用感光性樹脂材料而形成者，且所述半導體裝置的製造方法更包括：槽部形成步驟，於所述銅層形成步驟前對所述絕緣層進行曝光及顯影，藉此於所述絕緣層形成所述槽部。
  4. 如申請專利範圍第1項或第2項所述的半導體裝置的製造方法，其中所述槽部具有0.5μm~5μm的線寬。
  5. 如申請專利範圍第1項或第2項所述的半導體裝置的製造方法，其中於所述銅層形成步驟中，藉由將銅膏塗佈於所述絕緣層的至少所述槽部，並對所述銅膏進行燒結處理來形成所述銅層。
  6. 如申請專利範圍第5項所述的半導體裝置的製造方法，其中所述燒結處理後的所述銅層的體積電阻率為3μΩ．cm~40μΩ．cm。
  7. 如申請專利範圍第5項所述的半導體裝置的製造方法，其中於所述燒結處理中，在酸存在下以80℃~200℃對所述銅膏進行加熱。
  8. 如申請專利範圍第1項或第2項所述的半導體裝置的製造方法，其更包括：暫時固定層形成步驟，於所述基板上形成暫時固定層，於所述絕緣層形成步驟中，於所述暫時固定層上形成所述絕緣層。
  9. 如申請專利範圍第8項所述的半導體裝置的製造方法，其中於所述暫時固定層形成步驟中，形成含有在200℃以上體積膨脹的粒子的所述暫時固定層。
  10. 一種半導體裝置，其是將半導體元件搭載於設於基板上的配線體而成，所述配線體具有相互積層的多個配線層，於所述多個配線層的各個中設置有於所述配線層的一面側具有槽部的絕緣層、及以填埋所述槽部的方式形成的銅配線，所述一面側的所述絕緣層及所述銅配線的表面粗糙度為0.03μm以上且0.1μm以下。
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7110731B2 (ja) * 2017-05-30 2022-08-02 大日本印刷株式会社 貫通電極基板及びその製造方法
US11705414B2 (en) * 2017-10-05 2023-07-18 Texas Instruments Incorporated Structure and method for semiconductor packaging
US10777430B2 (en) 2018-06-27 2020-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Photonic integrated package and method forming same
KR102551034B1 (ko) * 2018-09-07 2023-07-05 삼성전자주식회사 반도체 패키지 및 그 제조방법
KR102131984B1 (ko) * 2018-10-23 2020-07-08 현대오트론 주식회사 인쇄 회로 기판
US10886149B2 (en) * 2019-01-31 2021-01-05 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
DE102019127924B3 (de) * 2019-10-16 2021-01-21 Tdk Electronics Ag Bauelement und Verfahren zur Herstellung eines Bauelements
KR20210051346A (ko) * 2019-10-30 2021-05-10 삼성전자주식회사 발진기 구조체 및 발진기 구조체를 포함하는 전자 장치
JP7414597B2 (ja) * 2020-03-12 2024-01-16 キオクシア株式会社 配線形成方法
JP2022070566A (ja) * 2020-10-27 2022-05-13 アオイ電子株式会社 回路基板の製造方法、回路基板、積層基板および支持基板
EP4307845A1 (en) * 2022-07-12 2024-01-17 AT&S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier with stamped design layer structure and embedded component
CN115566014A (zh) * 2022-09-26 2023-01-03 盛合晶微半导体(江阴)有限公司 集成电路封装结构及制备方法

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070193026A1 (en) * 2006-02-23 2007-08-23 Chun Christine Dong Electron attachment assisted formation of electrical conductors
EP2075825A1 (en) * 2007-12-28 2009-07-01 Interuniversitaire Microelectronica Centrum vzw ( IMEC) semiconductor device comprising conductive structures and a planarized surface
US20130034934A1 (en) * 2010-08-09 2013-02-07 Sk Link Co., Ltd. Wafer level package structure and method for manufacturing the same
TW201401512A (zh) * 2012-04-20 2014-01-01 Semiconductor Energy Lab 半導體裝置及其製造方法
US20140008821A1 (en) * 2012-07-05 2014-01-09 Nitto Denko Corporation Sealing resin sheet, method for producing electronic component package and electronic component package
TW201417285A (zh) * 2012-08-10 2014-05-01 Semiconductor Energy Lab 半導體裝置及其製造方法
TW201436242A (zh) * 2010-03-08 2014-09-16 Semiconductor Energy Lab 半導體裝置及半導體裝置的製造方法
TW201513223A (zh) * 2008-04-25 2015-04-01 Semiconductor Energy Lab 半導體裝置及其製造方法
TW201523885A (zh) * 2013-10-22 2015-06-16 Semiconductor Energy Lab 半導體裝置及半導體裝置的製造方法
TW201530663A (zh) * 2009-11-20 2015-08-01 Semiconductor Energy Lab 半導體裝置製造方法

Family Cites Families (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2075825A (en) * 1933-11-01 1937-04-06 Cesare Barbieri Cyclic process of producing amines of saturated hydrocarbons
US5440805A (en) 1992-03-09 1995-08-15 Rogers Corporation Method of manufacturing a multilayer circuit
JPH0715101A (ja) * 1993-06-25 1995-01-17 Shinko Electric Ind Co Ltd 酸化物セラミック回路基板及びその製造方法
JPH08222834A (ja) * 1995-02-13 1996-08-30 Toppan Printing Co Ltd 配線回路の形成方法および多層配線回路基板の製造方法
JPH09331136A (ja) * 1996-06-12 1997-12-22 Sumitomo Bakelite Co Ltd 導電性ペーストを用いたプリント配線板
JPH11142633A (ja) * 1997-11-05 1999-05-28 Alps Electric Co Ltd カラーフィルタの製造方法
JP2002246744A (ja) * 2001-02-20 2002-08-30 Nec Corp 導体形成方法およびこれを用いた多層配線基板製造方法
JP3667273B2 (ja) * 2001-11-02 2005-07-06 Ｎｅｃエレクトロニクス株式会社 洗浄方法および洗浄液
JP3761461B2 (ja) * 2001-12-13 2006-03-29 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
JP2003204140A (ja) * 2002-01-10 2003-07-18 Sony Corp 配線基板の製造方法、多層配線基板の製造方法および多層配線基板
JP2004104074A (ja) * 2002-07-17 2004-04-02 Sumitomo Electric Ind Ltd 半導体装置用部材
TWI234210B (en) * 2002-12-03 2005-06-11 Sanyo Electric Co Semiconductor module and manufacturing method thereof as well as wiring member of thin sheet
JP4634045B2 (ja) * 2003-07-31 2011-02-16 富士通株式会社 半導体装置の製造方法、貫通電極の形成方法、半導体装置、複合半導体装置、及び実装構造体
JP4353845B2 (ja) * 2004-03-31 2009-10-28 富士通株式会社 半導体装置の製造方法
TW200605169A (en) * 2004-06-29 2006-02-01 Sanyo Electric Co Circuit device and process for manufacture thereof
JP4671802B2 (ja) * 2004-10-18 2011-04-20 富士通株式会社 めっき方法、半導体装置の製造方法及び回路基板の製造方法
JP2006210891A (ja) * 2004-12-27 2006-08-10 Mitsuboshi Belting Ltd ポリイミド樹脂の無機薄膜パターン形成方法
US7588835B2 (en) * 2005-03-11 2009-09-15 Hitachi Chemical Company, Ltd. Method of treating the surface of copper and copper
JP4667094B2 (ja) * 2005-03-18 2011-04-06 富士通株式会社 電子装置の製造方法
JP4827454B2 (ja) * 2005-07-22 2011-11-30 キヤノン株式会社 ズームレンズおよびそれを有する撮像装置
JP5103724B2 (ja) * 2005-09-30 2012-12-19 富士通株式会社 インターポーザの製造方法
JP5003082B2 (ja) * 2006-09-26 2012-08-15 富士通株式会社 インターポーザ及びその製造方法
JP5069449B2 (ja) * 2006-11-14 2012-11-07 新光電気工業株式会社 配線基板及びその製造方法
JP2008205331A (ja) * 2007-02-22 2008-09-04 Toppan Printing Co Ltd 多層配線基板の製造方法および多層配線基板
JP4466662B2 (ja) * 2007-03-06 2010-05-26 株式会社デンソー 半導体装置の金属電極形成方法
DE102007030129A1 (de) 2007-06-29 2009-01-02 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung einer Mehrzahl optoelektronischer Bauelemente und optoelektronisches Bauelement
WO2009057654A1 (ja) * 2007-11-01 2009-05-07 Dai Nippon Printing Co., Ltd. 部品内蔵配線板、部品内蔵配線板の製造方法
JP2010258415A (ja) * 2009-02-12 2010-11-11 Sumitomo Bakelite Co Ltd 複合体、複合体の製造方法及び半導体装置
JP2012530362A (ja) * 2009-06-19 2012-11-29 アイメック 金属／有機誘電体界面でのクラックの低減
US8227904B2 (en) 2009-06-24 2012-07-24 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
JP5581519B2 (ja) 2009-12-04 2014-09-03 新光電気工業株式会社 半導体パッケージとその製造方法
JP2011192726A (ja) 2010-03-12 2011-09-29 Renesas Electronics Corp 電子装置および電子装置の製造方法
US8921144B2 (en) * 2010-06-25 2014-12-30 International Business Machines Corporation Planar cavity MEMS and related structures, methods of manufacture and design structures
KR101140982B1 (ko) * 2010-09-07 2012-05-03 삼성전기주식회사 단층 인쇄회로기판 및 그 제조 방법
WO2012036219A1 (ja) * 2010-09-17 2012-03-22 旭硝子株式会社 発光素子用基板および発光装置
JP2012190858A (ja) * 2011-03-08 2012-10-04 Ngk Spark Plug Co Ltd 配線基板の製造方法
JP5406241B2 (ja) * 2011-04-19 2014-02-05 株式会社フジクラ 配線板の製造方法
CA2744652A1 (en) * 2011-06-28 2012-12-28 Alton Payne Retractable mixer system and method of using same
JP5606421B2 (ja) * 2011-10-27 2014-10-15 株式会社日立製作所 銅ナノ粒子を用いた焼結性接合材料及びその製造方法及び電子部材の接合方法
JP5878362B2 (ja) * 2011-12-22 2016-03-08 新光電気工業株式会社 半導体装置、半導体パッケージ及び半導体装置の製造方法
JP5878054B2 (ja) * 2012-03-27 2016-03-08 ルネサスエレクトロニクス株式会社 半導体装置の製造方法及び半導体装置
JP5598739B2 (ja) * 2012-05-18 2014-10-01 株式会社マテリアル・コンセプト 導電性ペースト
BR112014032296A2 (pt) * 2012-06-27 2017-06-27 Shell Int Research método para a recuperação de petróleo, e, sistema
JP2014148732A (ja) * 2013-02-04 2014-08-21 Yamagata Univ 新規被覆銅微粒子及びその製造方法
JP2014179593A (ja) * 2013-02-15 2014-09-25 Nitto Denko Corp 半導体素子用封止シート、半導体装置及び半導体装置の製造方法
JP2014187334A (ja) * 2013-03-25 2014-10-02 Disco Abrasive Syst Ltd ウエハレベルパッケージ構造およびその製造方法
JP2014187333A (ja) * 2013-03-25 2014-10-02 Disco Abrasive Syst Ltd ウエハレベルパッケージ構造およびその製造方法
JP2014236190A (ja) * 2013-06-05 2014-12-15 富士通株式会社 配線の形成方法、半導体装置の製造方法及び回路基板の製造方法
JP6216180B2 (ja) * 2013-08-01 2017-10-18 日東電工株式会社 封止用シート、及び、当該封止用シートを用いた半導体装置の製造方法
JP2015126129A (ja) * 2013-12-26 2015-07-06 日東電工株式会社 電子部品パッケージの製造方法

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070193026A1 (en) * 2006-02-23 2007-08-23 Chun Christine Dong Electron attachment assisted formation of electrical conductors
EP2075825A1 (en) * 2007-12-28 2009-07-01 Interuniversitaire Microelectronica Centrum vzw ( IMEC) semiconductor device comprising conductive structures and a planarized surface
TW201513223A (zh) * 2008-04-25 2015-04-01 Semiconductor Energy Lab 半導體裝置及其製造方法
TW201530663A (zh) * 2009-11-20 2015-08-01 Semiconductor Energy Lab 半導體裝置製造方法
TW201436242A (zh) * 2010-03-08 2014-09-16 Semiconductor Energy Lab 半導體裝置及半導體裝置的製造方法
US20130034934A1 (en) * 2010-08-09 2013-02-07 Sk Link Co., Ltd. Wafer level package structure and method for manufacturing the same
TW201401512A (zh) * 2012-04-20 2014-01-01 Semiconductor Energy Lab 半導體裝置及其製造方法
US20140008821A1 (en) * 2012-07-05 2014-01-09 Nitto Denko Corporation Sealing resin sheet, method for producing electronic component package and electronic component package
TW201417285A (zh) * 2012-08-10 2014-05-01 Semiconductor Energy Lab 半導體裝置及其製造方法
TW201523885A (zh) * 2013-10-22 2015-06-16 Semiconductor Energy Lab 半導體裝置及半導體裝置的製造方法

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