JP6880661B2 - 半導体用仮固定材及びそれを用いた半導体装置の製造方法。 - Google Patents
半導体用仮固定材及びそれを用いた半導体装置の製造方法。 Download PDFInfo
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- JP6880661B2 JP6880661B2 JP2016216467A JP2016216467A JP6880661B2 JP 6880661 B2 JP6880661 B2 JP 6880661B2 JP 2016216467 A JP2016216467 A JP 2016216467A JP 2016216467 A JP2016216467 A JP 2016216467A JP 6880661 B2 JP6880661 B2 JP 6880661B2
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Landscapes
- Laminated Bodies (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Description
Claims (8)
- (A)キャリア及び該キャリア上に設けられた銅箔を有するピーラブル銅箔と、
(B)前記ピーラブル銅箔上に設けられた熱硬化性樹脂層と、
を備える半導体用仮固定材。 - 180℃で1時間加熱された後の前記熱硬化性樹脂層の5%重量減少温度が、260℃以上である、請求項1に記載の半導体用仮固定材。
- 前記キャリアと前記銅箔との間の剥離強度が0.001〜0.050kN/mである、請求項1又は2に記載の半導体用仮固定材。
- 当該半導体用仮固定材を180℃で1時間加熱した後の、前記ピーラブル銅箔と前記熱硬化性樹脂層との間の剥離強度が0.050kN/m以上である、請求項1〜3のいずれか一項に記載の半導体用仮固定材。
- 前記ピーラブル銅箔の厚さが2〜30μmである、請求項1〜4のいずれか一項に記載の半導体用仮固定材。
- 前記熱硬化性樹脂層の厚さが2〜50μmである、請求項1〜5のいずれか一項に記載の半導体用仮固定材。
- 支持体上に、請求項1〜6のいずれか一項に記載の半導体用仮固定材をその熱硬化性樹脂層が前記支持体に接する向きで設ける工程と、
前記半導体用仮固定材の前記支持体とは反対側の面上に半導体素子を搭載する工程と、
前記半導体素子を封止する封止樹脂層を前記半導体用仮固定材上に形成する工程と、
前記封止樹脂層上に前記半導体素子と接続する配線層を形成する工程と、
前記ピーラブル銅箔のキャリアと銅箔とを剥離することにより、前記半導体素子、前記封止樹脂層及び前記配線層を有する封止体から前記支持体を分離する工程と、
を含む、半導体装置の製造方法。 - 支持体上に、請求項1〜6のいずれか一項に記載の半導体用仮固定材をその熱硬化性樹脂層が前記支持体に接する向きで設ける工程と、
前記半導体用仮固定材の前記支持体とは反対側の面上に配線層を形成する工程と、
前記配線層と接続する半導体素子を前記配線層上に搭載する工程と、
前記半導体素子を封止する封止樹脂層を前記配線層上に形成する工程と、
前記ピーラブル銅箔のキャリアと銅箔とを剥離することにより、前記半導体素子、前記封止樹脂層及び前記配線層を有する封止体から前記支持体を分離する工程と、
を含む、半導体装置の製造方法。
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WO2022185489A1 (ja) * | 2021-03-04 | 2022-09-09 | 昭和電工マテリアルズ株式会社 | 半導体装置の製造方法 |
JP2024015735A (ja) * | 2022-07-25 | 2024-02-06 | 株式会社レゾナック | 仮固定用フィルム、仮固定用積層体、半導体装置の製造方法、及び仮固定用組成物 |
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JP2009033082A (ja) * | 2007-06-27 | 2009-02-12 | Hitachi Chem Co Ltd | 半導体用接着フィルム、これを用いた半導体パッケージ用基板及び半導体装置並びに半導体装置の製造方法 |
JP5473838B2 (ja) * | 2010-03-30 | 2014-04-16 | 日本電解株式会社 | 支持体金属箔付き複合金属層、これを用いた配線板とその製造方法、この配線板を用いた半導体パッケージの製造方法 |
JP6557960B2 (ja) * | 2014-10-31 | 2019-08-14 | 日立化成株式会社 | 半導体装置製造用部材、及びそれを用いた半導体装置の製造方法 |
JP2016134497A (ja) * | 2015-01-19 | 2016-07-25 | 凸版印刷株式会社 | 配線基板積層体及びこれを用いた半導体装置の製造方法 |
JP2016139752A (ja) * | 2015-01-29 | 2016-08-04 | 日立化成株式会社 | 半導体装置の製造方法 |
JP6468017B2 (ja) * | 2015-03-18 | 2019-02-13 | 日立化成株式会社 | 半導体装置の製造方法 |
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