JP2013518432A - Icダイ又はウエハをtsvウエハに接合するためのデュアルキャリア - Google Patents
Icダイ又はウエハをtsvウエハに接合するためのデュアルキャリア Download PDFInfo
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- JP2013518432A JP2013518432A JP2012551156A JP2012551156A JP2013518432A JP 2013518432 A JP2013518432 A JP 2013518432A JP 2012551156 A JP2012551156 A JP 2012551156A JP 2012551156 A JP2012551156 A JP 2012551156A JP 2013518432 A JP2013518432 A JP 2013518432A
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Abstract
Description
例
Claims (13)
- スタックされた電子的部品を形成する方法であって、
第1のディボンデング温度を有する第1の接着性材料を用いて、シリコン貫通ビア(TSV)ダイを含むTSVウエハの上側に第1のキャリアウエハを搭載すること、
薄くされたTSVウエハを形成するため、前記TSVウエハの下側から前記TSVウエハを薄くすることであって、前記薄くすることが、露出されたTSVティップを形成するため、前記TSVウエハ上に埋め込まれたTSVティップを露出させることを含むこと、
第2の接着性材料を用いて前記下側に第2のキャリアウエハを搭載することであって、前記第2の接着性材料が、前記第1のディボンデング温度に比較して高い第2のディボンデング温度を有すること、
前記薄くされたTSVウエハから前記第1のキャリアウエハを取り除くため、
前記薄くされたTSVウエハを前記第1のディボンデング温度を超える温度まで加熱すること、及び、
電子的部品を含むスタックされたTSVウエハを形成するため、前記薄くされたTSVウエハの前記上側の前記TSVダイ上に少なくとも第2のICダイを結合すること、
を含む、方法。 - 請求項1に記載の方法であって、前記第1の接着性材料及び前記第2の接着性材料の両方が熱可塑性物質を含む、方法。
- 請求項1に記載の方法であって、前記露出されたTSVティップが、前記薄くされたTSVウエハの下側から少なくとも5マイクロメートル突出する、突出するTSVティップである、方法。
- 請求項1に記載の方法であって、
前記第2のICダイと前記TSVウエハの前記上側との間に硬化可能な誘電体フィルム(CDF)を提供することを更に含み、
単一の処理工程で、電子的部品を含む前記スタックされたTSVウエハを形成するため、前記第2のICダイを前記結合することが、前記CDFからのアンダーフィルと、前記第2のICダイを結合するための接合とを形成する、圧縮成形を提供する熱プレスプロセス、を含む、
方法。 - 請求項1に記載の方法であって、電子的部品を含む前記スタックされたTSVウエハを前記形成することが、前記第2のICダイを前記結合した後、アンダーフィル材料又は非導電性のペースト(NCP)でアンダーフィルすることを更に含む、方法。
- 請求項4に記載の方法であって、前記第2のICダイを前記結合することが、フリップチップ結合を含む、方法。
- 請求項4に記載の方法であって、前記第2のICダイが複数のTSVを含み、前記第2のICダイを前記結合することが、前記第2のICダイのフェイスアップ結合を含む、方法。
- 請求項1に記載の方法であって、
電子的部品を含む前記スタックされたTSVウエハから前記第2のキャリアウエハを取り除くこと、及び、
複数の個片化されたスタックされたICダイを形成するため、電子的部品を含む前記スタックされたTSVウエハをソーイングすること、
を更に含む、方法。 - 請求項8に記載の方法であって、
前記複数の個片化されたスタックされたICダイの少なくとも1つを、その上にランドパッドを有するパッケージ基板に結合すること、及び、
アンダーフィル材料又は非導電性のペースト(NCP)でキャピラリアンダーフィルすること、
を更に含む、方法。 - 請求項8に記載の方法であって、前記露出されたTSVティップが、前記薄くされたTSVウエハの前記下側から少なくとも5マイクロメートル突出する、突出するTSVティップであり、この方法が、
前記ソーイングする前に前記突出するTSVティップ上に硬化可能な誘電体フィルム(CDF)を提供すること、
前記複数の個片化されたスタックされたICダイの少なくとも1つを、その上にランドパッドを有するパッケージ基板上に置くこと、及び
単一の処理工程で、前記個片化されたスタックされたICダイの前記突出するTSVティップを、前記パッケージ基板の前記ランドパッドへ結合するため、前記CDFからのアンダーフィルと接合と形成するため圧縮成形を提供する熱プレスプロセスを含む、結合すること、
を更に含む、方法。 - 請求項1に記載の方法であって、
前記第2のICダイを前記結合した後の前記第2のICダイを覆うため、モールド材料をオーバーモールドすることを含むモールド層を形成すること、
電子的部品を含む前記スタックされたTSVウエハから前記第2のキャリアウエハを取り除くこと、及び、
複数の個片化されたスタックされたICダイを形成するため、電子的部品を含む前記スタックされたTSVウエハをソーイングすること、
を更に含む、方法。 - 請求項11に記載の方法であって、
前記複数の個片化されたスタックされたICダイの少なくとも1つを、その上にランドパッドを有するパッケージ基板に結合すること、及び、
その後、アンダーフィル材料又は非導電性のペースト(NCP)でキャピラリアンダーフィルすること、
を更に含む、方法。 - 請求項11に記載の方法であって、前記露出されたTSVティップが、前記薄くされたTSVウエハの前記下側から少なくとも5マイクロメートル突出する、突出するTSVティップであり、この方法が、
前記ウエハをソーイングする前に前記突出するTSVティップ上に硬化可能な誘電体フィルム(CDF)を提供すること、
前記複数の個片化されたスタックされたICダイの少なくとも1つを、その上にランドパッドを有するパッケージ基板を置くこと、及び、
単一の処理工程で、パッケージ基板の前記ランドパッドに前記突出するTSVティップを結合するために、前記CDFからのアンダーフィルと接合とを形成するため圧縮成形を提供する熱プレスプロセスを含む第2の結合をすること、
を更に含む、方法。
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US12/694,012 US8017439B2 (en) | 2010-01-26 | 2010-01-26 | Dual carrier for joining IC die or wafers to TSV wafers |
US12/694,012 | 2010-01-26 | ||
PCT/US2010/060927 WO2011093955A2 (en) | 2010-01-26 | 2010-12-17 | Dual carrier for joining ic die or wafers to tsv wafers |
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JP2013518432A true JP2013518432A (ja) | 2013-05-20 |
JP2013518432A5 JP2013518432A5 (ja) | 2014-02-06 |
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US (1) | US8017439B2 (ja) |
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Also Published As
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WO2011093955A2 (en) | 2011-08-04 |
US20110183464A1 (en) | 2011-07-28 |
CN102844859A (zh) | 2012-12-26 |
US8017439B2 (en) | 2011-09-13 |
WO2011093955A3 (en) | 2011-10-06 |
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