JP2016213370A - 半導体装置及び半導体装置の製造方法 - Google Patents
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- 229910052802 copper Inorganic materials 0.000 description 4
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
(I)キャリア上に複数の第1の半導体素子(チップ)を搭載する工程と、
(II)前記第1の半導体素子を絶縁材料で一括封止して、封止体を形成する工程と、
(III)前記キャリアを剥離して、前記第1の半導体素子の電極を露出させる工程と、
(IV)前記複数の第1の半導体素子の2以上の第1の半導体素子を跨るように、第2の半導体素子を、フリップチップ接続により搭載する工程と、
を備える半導体装置の製造方法である。
より効率的に半導体パッケージを製造するためには、個片化した半導体素子4と、パネル又はウェハ状態の半導体素子封止パッケージ100を150℃以下で仮圧着した後、リフロー工程によって金属接続させることが最も好ましい。
具体的には、半導体素子2の電極(図示せず)に、はんだボール等の電気接続のための金属接続部材9を搭載し(図6)、個片化する(図示せず)。金属接続部材9の搭載は市販のN2リフロー装置等を用いて容易に行うことができる。
Claims (7)
- (I)キャリア上に複数の第1の半導体素子を搭載する工程と、
(II)前記第1の半導体素子を絶縁材料で一括封止して、封止体を形成する工程と、
(III)前記キャリアを剥離して、前記第1の半導体素子の電極を露出させる工程と、
(IV)前記複数の第1の半導体素子の2以上の第1の半導体素子を跨るように、第2の半導体素子をフリップチップ接続により搭載する工程と、
を備える半導体装置の製造方法。 - 前記絶縁材料が、フィルム状の材料又はシート状の材料である請求項1記載の半導体装置の製造方法。
- 前記第2の半導体素子が、アンダーフィル付チップである請求項1又は2に記載の半導体装置の製造方法。
- 前記アンダーフィルが、フィルム状の材料又はシート状の材料である請求項3記載の半導体装置の製造方法。
- 前記アンダーフィルが、感光性材料である請求項1〜4のいずれか一項に記載の半導体装置の製造方法。
- 前記(II)工程後であって前記(III)工程前に、(II-1)前記封止体を薄化する工程を備える請求項1〜5のいずれか一項に記載の半導体装置の製造方法。
- 請求項1〜6のいずれか一項に記載の製造方法を用いて製造された半導体装置。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018226394A3 (en) * | 2017-06-09 | 2019-03-21 | Apple Inc. | HIGH DENSITY INTERCONNECTION USING A SORTANCE INTERPOSER MICROCHIP |
US11309895B2 (en) | 2018-04-12 | 2022-04-19 | Apple Inc. | Systems and methods for implementing a scalable system |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003243604A (ja) * | 2002-02-13 | 2003-08-29 | Sony Corp | 電子部品及び電子部品の製造方法 |
US20110285006A1 (en) * | 2010-05-19 | 2011-11-24 | Chao-Fu Weng | Semiconductor Package and Method for Making the Same |
JP2012169440A (ja) * | 2011-02-14 | 2012-09-06 | Fujitsu Semiconductor Ltd | 半導体装置及びその製造方法 |
JP2013516060A (ja) * | 2009-12-24 | 2013-05-09 | アイメック | 窓介在型ダイパッケージング |
JP2014082359A (ja) * | 2012-10-17 | 2014-05-08 | Olympus Corp | 半導体基板、半導体装置、および固体撮像装置、並びに半導体基板の製造方法 |
JP2014526139A (ja) * | 2011-06-30 | 2014-10-02 | ムラタ エレクトロニクス オサケユキチュア | システムインパッケージデバイスを製造する方法、および、システムインパッケージデバイス |
JP2015031724A (ja) * | 2013-07-31 | 2015-02-16 | 日立化成株式会社 | 半導体装置の製造方法及びその製造方法によって得られる半導体装置 |
WO2015045089A1 (ja) * | 2013-09-27 | 2015-04-02 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP2015086359A (ja) * | 2013-09-24 | 2015-05-07 | 日東電工株式会社 | 半導体チップ封止用熱硬化性樹脂シート及び半導体パッケージの製造方法 |
-
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- 2015-05-12 JP JP2015097216A patent/JP6792322B2/ja active Active
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003243604A (ja) * | 2002-02-13 | 2003-08-29 | Sony Corp | 電子部品及び電子部品の製造方法 |
JP2013516060A (ja) * | 2009-12-24 | 2013-05-09 | アイメック | 窓介在型ダイパッケージング |
US20110285006A1 (en) * | 2010-05-19 | 2011-11-24 | Chao-Fu Weng | Semiconductor Package and Method for Making the Same |
JP2012169440A (ja) * | 2011-02-14 | 2012-09-06 | Fujitsu Semiconductor Ltd | 半導体装置及びその製造方法 |
JP2014526139A (ja) * | 2011-06-30 | 2014-10-02 | ムラタ エレクトロニクス オサケユキチュア | システムインパッケージデバイスを製造する方法、および、システムインパッケージデバイス |
JP2014082359A (ja) * | 2012-10-17 | 2014-05-08 | Olympus Corp | 半導体基板、半導体装置、および固体撮像装置、並びに半導体基板の製造方法 |
JP2015031724A (ja) * | 2013-07-31 | 2015-02-16 | 日立化成株式会社 | 半導体装置の製造方法及びその製造方法によって得られる半導体装置 |
JP2015086359A (ja) * | 2013-09-24 | 2015-05-07 | 日東電工株式会社 | 半導体チップ封止用熱硬化性樹脂シート及び半導体パッケージの製造方法 |
WO2015045089A1 (ja) * | 2013-09-27 | 2015-04-02 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018226394A3 (en) * | 2017-06-09 | 2019-03-21 | Apple Inc. | HIGH DENSITY INTERCONNECTION USING A SORTANCE INTERPOSER MICROCHIP |
US10943869B2 (en) | 2017-06-09 | 2021-03-09 | Apple Inc. | High density interconnection using fanout interposer chiplet |
US11594494B2 (en) | 2017-06-09 | 2023-02-28 | Apple Inc. | High density interconnection using fanout interposer chiplet |
US11309895B2 (en) | 2018-04-12 | 2022-04-19 | Apple Inc. | Systems and methods for implementing a scalable system |
US11831312B2 (en) | 2018-04-12 | 2023-11-28 | Apple Inc. | Systems and methods for implementing a scalable system |
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Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
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S533 | Written request for registration of change of name |
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R350 | Written notification of registration of transfer |
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S531 | Written request for registration of change of domicile |
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R350 | Written notification of registration of transfer |
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