JP5784775B2 - 半導体パッケージ及びその製造方法 - Google Patents
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
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- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
[第1の実施の形態に係る半導体パッケージの構造]
図4は、第1の実施の形態に係る半導体パッケージを例示する断面図である。図4を参照するに、半導体パッケージ10は、半導体チップ20及び樹脂部30が形成する面の上に極薄の配線構造体40が形成され、更に配線構造体40上に外部接続端子49が形成された構造を有する。半導体チップ20と配線構造体40とは、はんだバンプ等を用いずに直接接続されている。
続いて、第1の実施の形態に係る半導体パッケージの製造方法について説明する。図5〜図20は、第1の実施の形態に係る半導体パッケージの製造工程を例示する図である。
[第2の実施の形態に係る半導体パッケージの構造]
図21は、第2の実施の形態に係る半導体パッケージを例示する断面図である。図21を参照するに、半導体パッケージ60において、樹脂部30が樹脂部61に置換された点と、電極パッド22上に突起電極23が形成された点が図4に示す半導体パッケージ10との主な相違点である。以下、半導体パッケージ60について、半導体パッケージ10と共通する部分の説明は省略し、異なる部分を中心に説明する。
続いて、第2の実施の形態に係る半導体パッケージの製造方法について説明する。図22〜図26は、第2の実施の形態に係る半導体パッケージの製造工程を例示する図である。
20 半導体チップ
21 半導体基板
22 電極パッド
23 突起電極
30、61 樹脂部
31 第1樹脂部
32 第2樹脂部
32x、45x 開口部
40 配線構造体
41 第1絶縁層
41x 第1ビアホール
42 第1配線層
43 第2絶縁層
43x 第2ビアホール
44 第2配線層
45 ソルダーレジスト層
49 外部接続端子
50 支持体
50x 凹部
51 粘着層
57 ダイシングブレード
D 奥行き
H 深さ
T 厚さ
W 幅
Claims (7)
- 半導体チップと、
前記半導体チップの側面を封止する樹脂部と、
前記樹脂部の一方の面上及び前記半導体チップの回路形成面上に形成された、絶縁層及び前記絶縁層上に配置された配線層を含む配線構造体と、を有し、
前記樹脂部は、第1樹脂部上に、前記第1樹脂部よりも前記絶縁層との密着性に優れた第2樹脂部が積層された構造を含み、
前記半導体チップの前記回路形成面は、前記第2樹脂部の表面よりも窪んだ位置にあって、かつ、前記第2樹脂部から露出し、
前記絶縁層は、前記樹脂部の一方の面をなす前記第2樹脂部の表面と、前記回路形成面とを連続的に覆い、
前記絶縁層には前記配線層と一体的に形成されたビア配線が形成され、前記ビア配線は前記回路形成面の電極パッドと直接接続されている半導体パッケージ。 - 前記半導体チップの前記回路形成面の反対面は、前記樹脂部の他方の面から露出し、かつ、前記樹脂部の他方の面と面一である請求項1記載の半導体パッケージ。
- 支持体の一方の面に設けられた凹部に、回路形成面が前記凹部の内底面と対向し、かつ、一部が前記凹部から突出するように半導体チップを配置する第1工程と、
前記支持体の一方の面に、前記半導体チップの前記回路形成面の反対面を含む突出部を封止する第1樹脂部を形成する第2工程と、
前記支持体を除去し、前記回路形成面を前記第1樹脂部の一方の面から露出させる第3工程と、
前記第1樹脂部の一方の面上と、前記第1樹脂部から露出する前記半導体チップの側面を封止する第2樹脂部を形成する第4工程と、
前記回路形成面上及び前記第2樹脂部上に、前記第1樹脂部を基体の一部とし、前記半導体チップと電気的に接続される配線構造体を形成する第5工程と、を有し、
前記第4工程では、前記回路形成面上及び前記第1樹脂部の一方の面上を封止するように前記第2樹脂部を形成した後、前記回路形成面上に形成された前記第2樹脂部を除去する半導体パッケージの製造方法。 - 前記第1樹脂部の他方の面を研削して前記回路形成面の反対面を前記他方の面から露出させ、前記回路形成面の反対面を前記他方の面と面一にする第6工程を有する請求項3記載の半導体パッケージの製造方法。
- 前記第2工程では、前記第1樹脂部を圧縮成形で形成する請求項3又は4記載の半導体パッケージの製造方法。
- 前記支持体は金属であり、
前記第3工程では、前記支持体をエッチングにより除去する請求項3乃至5の何れか一項記載の半導体パッケージの製造方法。 - 前記支持体の一方の面には、複数の凹部が設けられており、
前記第1工程では、前記複数の凹部のそれぞれに前記半導体チップを配置し、
各半導体チップと電気的に接続される配線構造体を形成した後に、少なくとも一つの前記半導体チップを有するように、前記配線構造体と前記第1及び第2樹脂部を切断し、複数の半導体パッケージを作製する請求項3乃至6の何れか一項記載の半導体パッケージの製造方法。
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US10256211B2 (en) | 2014-07-28 | 2019-04-09 | Intel Corporation | Multi-chip-module semiconductor chip package having dense package wiring |
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US20210375814A1 (en) * | 2017-12-06 | 2021-12-02 | Anhui Yunta Electronic Technologies Co., Ltd. | Integrated circuit module structure and method for manufacturing same |
JP7104582B2 (ja) * | 2018-08-07 | 2022-07-21 | 株式会社ディスコ | パッケージ基板の製造方法、基板及び粘着性部材 |
WO2022024369A1 (ja) * | 2020-07-31 | 2022-02-03 | 国立大学法人東北大学 | 半導体装置の製造方法、半導体装置を備えた装置の製造方法、半導体装置、半導体装置を備えた装置 |
CN113161249A (zh) * | 2021-03-31 | 2021-07-23 | 矽磐微电子(重庆)有限公司 | 半导体封装方法及半导体封装结构 |
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