TWI758320B - 半導體封裝 - Google Patents

半導體封裝 Download PDF

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Publication number
TWI758320B
TWI758320B TW106130204A TW106130204A TWI758320B TW I758320 B TWI758320 B TW I758320B TW 106130204 A TW106130204 A TW 106130204A TW 106130204 A TW106130204 A TW 106130204A TW I758320 B TWI758320 B TW I758320B
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Taiwan
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substrate
pads
semiconductor
pitch
package
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TW106130204A
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TW201834190A (zh
Inventor
表聲磤
沈鍾輔
金知晃
趙汊濟
韓相旭
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南韓商三星電子股份有限公司
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Abstract

一種半導體封裝包括：第一基底，包括第一上部接墊，所述第一上部接墊位於所述第一基底的頂表面上；第二基底，包括第二上部接墊，所述第二上部接墊位於所述第二基底的頂表面上，所述第二上部接墊的節距小於所述第一上部接墊的節距；以及第一半導體晶片，位於以下兩者上並電連接到以下兩者：（i）所述第一上部接墊中的至少一個以及（ii）所述第二上部接墊中的至少一個。

Description

半導體封裝
本發明是有關於一種半導體封裝，且特別是有關於一種半導體封裝的電連接。 [相關申請的交叉參考] 本專利申請主張在2016年12月16日在韓國智慧財產權局提出申請的韓國專利申請第10-2016-0172919號的優先權，所述韓國專利申請的公開內容全文併入本申請供參考。
半導體晶片可以半導體封裝的形式實現以適當地應用於電子產品。在一般的半導體封裝中，半導體晶片可安裝在印刷電路板（printed circuit board，PCB）上且可經由接合配線（bonding wires）或凸塊電連接到印刷電路板。隨著電子產業的發展，對半導體晶片的高性能積體電路的需求已日益增加。因此，已經對半導體晶片的積體電路進行了各種設計。
本發明概念的一些示例性實施例可為半導體封裝提供高可靠性。
本發明概念的一些示例性實施例也可提供具有各種節距的半導體封裝。
根據示例性實施例，一種半導體封裝可包括：第一基底，包括第一上部接墊，所述第一上部接墊位於所述第一基底的頂表面上；第二基底，包括第二上部接墊，所述第二上部接墊位於所述第二基底的頂表面上，所述第二上部接墊的節距小於所述第一上部接墊的節距；以及第一半導體晶片，位於以下兩者上並電連接到以下兩者：（i）所述第一上部接墊中的至少一個以及（ii）所述第二上部接墊中的至少一個。
根據示例性實施例，一種半導體封裝可包括：第一基底，具有孔；第二基底，位於所述第一基底的所述孔中；至少一個半導體晶片，位於所述第一基底及所述第二基底上；第一連接部，位於所述第一基底與所述半導體晶片之間；以及第二連接部，位於所述第二基底與所述半導體晶片之間。所述第二連接部的節距可小於所述第一連接部的節距。
根據示例性實施例，一種半導體封裝可包括：多個半導體晶片，沿橫向排列；第一接墊，位於所述半導體晶片的表面上；第二接墊，位於所述半導體晶片的所述表面上；第一基底，經由所述第一接墊電連接到所述半導體晶片，所述第一基底面對所述半導體晶片的所述表面；以及第二基底，經由所述第二接墊電連接到所述半導體晶片，所述第二基底面對所述半導體晶片的所述表面，所述第二接墊的節距小於所述第一接墊的節距。
根據示例性實施例，一種半導體封裝可包括：第一基底，包括位於所述第一基底的第一表面上的第一基底接墊，所述第一基底接墊具有第一節距；第二基底，包括位於所述第二基底的第一表面上的第二基底接墊，所述第二基底接墊具有第二節距，所述第二節距小於所述第一節距；以及第一半導體晶片，包括第一晶片接墊及第二晶片接墊，所述第一晶片接墊具有第三節距，所述第二晶片接墊具有第四節距，所述第四節距小於所述第三節距，所述第一半導體晶片同時位於所述第一基底接墊中的至少一個與所述第二基底接墊中的至少一個上以使所述第一晶片接墊中的一個電耦合到所述第一基底接墊中的所述至少一個且所述第二晶片接墊中的一個電耦合到所述第二基底接墊中的所述至少一個。
在下文中將闡述根據本發明概念一些示例性實施例的半導體封裝及其製造方法。
圖1A是說明根據本發明概念示例性實施例的半導體封裝的平面圖。圖1B是沿圖1A所示線IB-IB’截取的剖視圖。
參照圖1A及圖1B，半導體封裝1可包括封裝基底1000、第一凸塊710、第一基底100、第二基底200、模塑圖案400及半導體晶片500。封裝基底1000可包括印刷電路板（PCB）。
第一基底100可設置在封裝基底1000上。第一基底100可包括印刷電路板（PCB）。第一基底100可包括第一基礎層110、第一導電結構120及第一上部接墊150。第一基礎層110可包括依序堆疊的多個第一基礎層110。第一基礎層110可包含絕緣材料。舉例來說，第一基礎層110可包含聚合物或陶瓷。第一導電結構120可包括第一下部接墊121、第一通孔122及第一導電圖案123。第一下部接墊121可設置在第一基底100的底表面100b上。第一通孔122可穿透第一基礎層110。第一導電圖案123可設置在第一基礎層110之間且可連接到第一通孔122。第一上部接墊150可設置在第一基底100的頂表面100a上且可分別連接到第一通孔122中的對應的一個第一通孔122。第一基底100的頂表面100a可與第一基底100的底表面100b相反。第一上部接墊150可不在第三方向D3上與第一下部接墊121對齊。因此，第一上部接墊150的排列自由度可得到提高。第一方向D1及第二方向D2可平行於第一基底100的頂表面100a。第二方向D2可與第一方向D1相交。第三方向D3可實質上垂直於第一基底100的頂表面100a。第一凸塊710可設置在第一基底100與封裝基底1000之間。第一凸塊710可電連接到第一導電結構120及封裝基底1000。第一導電結構120可向半導體晶片500傳送訊號，可向半導體晶片500供應電壓，及/或可使半導體晶片500接地。第一導電結構120可彼此電隔離。儘管圖式中未示出，然而可在第一基底100的頂表面100a上設置第一內連圖案，且第一內連圖案的寬度可大於10 μm。第一內連圖案之間的距離可大於10 μm。第一基底100可具有穿透第一基底100的孔190。孔190可從頂表面100a到達底表面100b穿透第一基底100。
第二基底200可設置在第一基底100的孔190中。第二基底200可與第一基底100間隔開。第二基底200的頂表面200a可設置在與第一基底100的頂表面100a實質上相同的水平高度上。可使用印刷電路板作為第二基底200。第二基底200可包括第二基礎層210、內連線240及第二上部接墊250。第二基礎層210可包含聚合物或陶瓷。儘管圖式中未示出，然而第二基礎層210可包括多個堆疊的層。如果第一基底100與第二基底200之間的熱膨脹係數差異大，則在半導體封裝1的操作期間，在第一基底100及/或第二基底200中可能會出現開裂。舉例來說，如果第二基底200包括半導體晶片，則第一基底100與第二基底200之間的熱膨脹係數差異可為大的。根據本發明概念的一些示例性實施例，第一基底100及第二基底200可包括印刷電路板。因此，半導體封裝1的可靠性可得到提高。儘管圖式中未示出，然而可在第二基底200的頂表面200a上設置第二內連圖案，且第二內連圖案的寬度可小於10 μm。第二內連圖案之間的距離可小於10 μm。
第二上部接墊250可設置在第二基底200的頂表面200a上。第二上部接墊250的節距可小於第一上部接墊150的節距。第二上部接墊250可用作傳送訊號的接墊。內連線240可設置在第二基底200（例如，第二基礎層210）中。不同於圖1B，內連線240可設置在第二基底200的頂部部分上。內連線240可電連接到第二上部接墊250中的至少兩個。多個半導體晶片500可設置在第一基底100的頂表面100a及第二基底200的頂表面200a上。各半導體晶片500可在橫向上彼此間隔開。舉例來說，各半導體晶片500可在第一方向D1上彼此間隔開。當在平面圖中觀察時，半導體晶片500中的每一者可與第一基底100及第二基底200重疊。半導體晶片500中的每一者可設置在第一上部接墊150及第二上部接墊250上。
在半導體晶片500的表面500b上可設置有第一接墊510及第二接墊520。當在平面圖中觀察時，第一接墊510及第二接墊520可分別與第一上部接墊150及第二上部接墊250重疊。半導體晶片500的表面500b可用作主動表面。半導體晶片500的表面500b可面對第一基底100及第二基底200。第一接墊510及第二接墊520可電連接到設置在半導體晶片500中的電路圖案（圖中未示出）。在本說明書中，連接到半導體晶片500的電連接可意指連接到設置在半導體晶片500中的電路圖案的電連接。第一接墊510及第二接墊520可包含導電材料（例如，金屬）。當在平面圖中觀察時，第一接墊510可與第一基底100重疊。第一接墊510可具有第一節距P1。此處，用語「節距」可意指重複排列的元件中的相鄰的兩個元件的兩個對應的側壁之間的距離。
在第一基底100與半導體晶片500之間可設置有第一連接部610。第一連接部610可電連接到第一上部接墊150及第一接墊510。半導體晶片500可經由第一連接部610電連接到第一基底100。半導體晶片500電連接到第一基底100可意指半導體晶片500電連接到第一導電結構120中的至少一個。第一導電結構120可向半導體晶片500傳送電訊號或從半導體晶片500接收電訊號，可向半導體晶片500供應電壓，及/或可將半導體晶片500接地。當在平面圖中觀察時，第一連接部610可與第一接墊510及第一上部接墊150重疊。第一連接部610的節距可實質上等於第一接墊510的第一節距P1及第一上部接墊150的節距。第一上部接墊150可不在第三方向D3上與第一下部接墊121對齊，且因此，第一上部接墊150的排列自由度可得到提高。因此，可減少對半導體晶片500中的電路圖案的設計的限制。第一連接部610中的每一者可包括焊料球、凸塊、或柱體。第一連接部610可包含導電材料(例如，金屬)。
當在平面圖中觀察時，第二接墊520可與第二基底200重疊。第二接墊520可以第二節距P2排列。第二節距P2可不同於第一節距P1。具體來說，第二節距P2可小於第一節距P1。
在第二基底200與半導體晶片500之間可設置有第二連接部620。半導體晶片500可經由第二接墊520及第二連接部620電連接到第二基底200。半導體晶片500中的一個可電連接到第一上部接墊150中的一個或一些以及第二連接部620中的一個或一些。半導體晶片500中的另一個可電連接到第一上部接墊150中的另一個或另一些以及第二連接部620中的另一個或另一些。內連線240可將第二上部接墊250中的一個電連接到第二上部接墊250中的另一個。因此，半導體晶片500可經由第二連接部620電連接到內連線240。半導體晶片500可經由內連線240將電訊號傳送到彼此。第二連接部620中的每一者可包括例如焊料球、凸塊、或柱體。第二連接部620可包含導電材料（例如，金屬）。當在平面圖中觀察時，第二連接部620可分別與第二上部接墊250及第二接墊520重疊。第二連接部620可電連接到第二上部接墊250及第二接墊520。第二連接部620的節距可實質上等於第二接墊520的第二節距P2及第二上部接墊250的節距。第二連接部620的節距可小於第一連接部610的節距。
如果省略第二基底200，則第二接墊520可以與第一接墊510相同或相似的節距排列。在這種情形中，半導體晶片500的電路圖案設計可受到限制或約束。如果省略第二基底200，則第一上部接墊150可以各種節距排列。在這種情形中，製造第一基底100的製程可變得複雜。根據一些示例性實施例，第二基底200可放寬半導體晶片500的電路圖案的設計約束條件。由於半導體晶片500安裝在第一基底100及第二基底200上，因此可簡化製造第一基底100的製程。半導體晶片500可通過第二基底200容易地電連接到彼此。換句話說，半導體晶片500可經由第二基底200的內連線240電連接到彼此。
在半導體晶片500的表面500b上可分別設置有底部填充層410。底部填充層410可密封第一連接部610及第二連接部620。在第一基底100與第二基底200之間可設置有模塑圖案400。模塑圖案400可進一步延伸到第一基底100的底表面100b上以及第二基底200的底表面200b上。第二基底200的底表面200b可與第二基底200的頂表面200a相反。模塑圖案400可包含絕緣聚合物材料。
圖2是與圖1A所示線IB-IB’對應的剖視圖，其示出根據本發明概念示例性實施例的半導體封裝。在下文中，為容易及方便地進行解釋，與以上示例性實施例相同的元件的說明將予以省略或僅簡要提及。
參照圖1A及圖2，半導體封裝2可包括封裝基底1000、第一凸塊710、第一基底100、第二基底200、模塑圖案400、半導體晶片500及第二凸塊720。第二凸塊720可設置在封裝基底1000與第二基底200之間。第二基底200可包括第二基礎層210、第二上部接墊250、內連線240及第二導電結構220。第二基礎層210可設置有多個。第二基礎層210的數目可等於或大於第一基礎層110的數目。內連線240可電連接到第二上部接墊250中的至少兩個。內連線240可在半導體晶片500之間用作訊號傳送路徑。連接到內連線240的第二上部接墊250可用作訊號傳送接墊。
第二導電結構220可包括第二下部接墊221、第二通孔222及第二導電圖案223。第二導電結構220可電連接到第二上部接墊250中對應的一個。在下文中，將闡述第二導電結構220及連接到第二導電結構220的單個第二上部接墊250作為本示例性實施例中的實例。第二下部接墊221可設置在第二基底200的底表面200b上。第二導電圖案223可設置在各第二基礎層210之間且可電連接到第二通孔222。第二通孔222可穿透第二基礎層210中的至少一個。第二通孔222可設置在第二下部接墊221與第二導電圖案223之間以及第二導電圖案223與第二上部接墊250之間。第二凸塊720可設置在封裝基底1000與第二下部接墊221之間以將封裝基底1000與第二下部接墊221電連接到彼此。半導體晶片500的第二接墊520可經由第二連接部620、第二上部接墊250、第二導電結構220及第二凸塊720電連接到封裝基底1000。在一些示例性實施例中，半導體晶片500中的每一者可經由第二導電結構220接地。在一些示例性實施例中，可經由第二導電結構220向半導體晶片500中的每一者供應外部電壓。第二上部接墊250可不在第三方向D3上與第二下部接墊221對齊。因此，可以較少的設計約束條件來設計半導體晶片500的電路圖案以及封裝基底1000的內連線（圖中未示出）。在一些示例性實施例中，可省略第二導電圖案223，且第二上部接墊250可在第三方向D3上與第二凸塊720對齊。第二導電結構220可與內連線240電隔離。因此，可防止在第二導電結構220與內連線240之間發生短路。
圖3是與圖1A所示線IB-IB’對應的剖視圖，其示出根據本發明概念示例性實施例的半導體封裝。在下文中，為容易及方便地進行解釋，與以上示例性實施例相同的元件的說明將予以省略或僅簡要提及。
參照圖1A及圖3，半導體封裝3可包括封裝基底1000、第一凸塊710、第一基底100、第二基底200、模塑圖案400、半導體晶片500及虛擬凸塊721。封裝基底1000、第一凸塊710、第一基底100、第二基底200及半導體晶片500可與參照圖1A及圖1B所闡述的相同。虛擬凸塊721可設置在封裝基底1000與第二基底200之間。第二基底200可通過虛擬凸塊721穩定地附裝到封裝基底1000上。虛擬凸塊721可與封裝基底1000中所包含的導電元件、第二基底200中所包含的導電元件及半導體晶片500電隔離。舉例來說，虛擬凸塊721可與內連線240電隔離。另外，虛擬凸塊721可與第一凸塊710電隔離。
圖4是與圖1A所示線IB-IB’對應的剖視圖，其示出根據本發明概念示例性實施例的半導體封裝。在下文中，為容易及方便地進行解釋，與以上示例性實施例相同的元件的說明將予以省略或僅簡要提及。
參照圖1A及圖4，半導體封裝4可包括封裝基底1000、第一凸塊710、第一基底100、第二基底200、模塑圖案400及半導體晶片500。第一基底100可具有孔190。孔190可從第一基底100的頂表面100a朝第一基底100的底表面100b延伸。孔190可不穿透第一基底100的底表面100b。孔190的底表面190b可設置在第一基底100中。因此，孔190的底表面190b可與第一基底100的底表面100b間隔開。
第二基底200可嵌置在第一基底100的孔190中。舉例來說，第二基底200可設置在孔190的底表面190b上。第二基底200的厚度可小於第一基底100的厚度。第二基底200可與孔190的內側壁間隔開。模塑圖案400可設置在孔190中。模塑圖案400可填充第一基底100與第二基底200之間的間隙。
第一凸塊710可設置在封裝基底1000與第一導電結構120之間。半導體晶片500可經由第一導電結構120及第一凸塊710電連接到封裝基底1000。
虛擬凸塊721可進一步設置在封裝基底1000與第一基底100之間。虛擬凸塊721可支撐第一基底100。
圖5是與圖1A所示線IB-IB’對應的剖視圖，其示出根據本發明概念示例性實施例的半導體封裝。在下文中，為容易及方便地進行解釋，與以上示例性實施例相同的元件的說明將予以省略或僅簡要提及。
參照圖1A及圖5，半導體封裝5可包括封裝基底1000、第一凸塊710、第一基底100、第二基底200、模塑圖案400、半導體晶片500及第二凸塊720。第一基底100的孔190的底表面190b可設置在第一基底100中。第一基底100可包括第一基礎層110及第一導電結構120且可進一步包括連接通孔140。連接通孔140可穿透第一基礎層110中的至少一個。舉例來說，連接通孔140可設置在第一基底100的底表面100b與孔190的底表面190b之間。當在平面圖中觀察時，連接通孔140可與孔190重疊。連接通孔140可與第一導電結構120絕緣。
第二基底200可設置在孔190的底表面190b上且可與孔190的內側壁間隔開。第二基底200可包括第二基礎層210、第二上部接墊250、內連線240及第二導電結構220。第二基礎層210可包括依序堆疊的多個第二基礎層210。第二導電結構220可包括第二下部接墊221、第二通孔222及第二導電圖案223。第二導電結構220可包括第二下部接墊221，且因此第二導電結構220可在第二基底200的底表面200b處被暴露出。第二導電結構220可電連接到連接通孔140。
第二凸塊720可設置在封裝基底1000與第一基底100的底表面100b之間。第二凸塊720可電連接到連接通孔140。因此，半導體晶片500可經由第二導電結構220電連接到封裝基底1000。第二導電結構220可用作接地導電結構或電源導電結構。第二導電結構可在實體上與內連線240間隔開且可與內連線240電隔離。由於第二導電結構220，可對半導體晶片500的電路圖案及/或封裝基底1000的內連圖案進行各種設計。
可在封裝基底1000與第一基底100之間進一步設置虛擬凸塊721。虛擬凸塊721可在實體上與第一凸塊710及第二凸塊720間隔開且可與第一凸塊710及第二凸塊720電隔離。
圖6是說明根據本發明概念示例性實施例的半導體封裝的剖視圖。在下文中，為容易及方便地進行解釋，與以上示例性實施例相同的元件的說明將予以省略或僅簡要提及。
參照圖1A及圖6，半導體封裝6可包括封裝基底1000、第一凸塊710、第一基底100、第二基底200、模塑圖案400、底部填充層410、以及半導體晶片501、502及503。半導體晶片501、502及503可包括第一半導體晶片501、第二半導體晶片502及第三半導體晶片503。第一半導體晶片501可與參照圖1A及圖1B闡述的半導體晶片500中的一個相同。舉例來說，第一半導體晶片501可經由第一連接部610及第二連接部620電連接到第一基底100及第二基底200。
第二半導體晶片502可設置在第一基底100及第二基底200上。第二半導體晶片502可設置有多個。第二半導體晶片502可堆疊在一起。第二半導體晶片502可經由第一連接部610及第二連接部620電連接到第一基底100及第二基底200。在第二半導體晶片502中可設置有穿孔522。第二半導體晶片502可經由穿孔522電連接到彼此。第二半導體晶片502可經由內連線240與第一半導體晶片501交換電訊號。半導體晶片502可經由第一導電結構120電連接到封裝基底1000。第二半導體晶片502可經由第一導電結構120接地或者可經由第一導電結構120被供應電源電壓。第二半導體晶片502的數目並非僅限於圖6所示第二半導體晶片502的數目，而是可作出各種變化。在一些示例性實施例中，可設置單個第二半導體晶片502。儘管圖式中未示出，然而第二基底200可進一步包括圖2所示第二導電結構220。
可在第二半導體晶片502上設置第三半導體晶片503。第三半導體晶片503可不包括穿孔。第三半導體晶片503可經由穿孔522電連接到第二半導體晶片502。第三半導體晶片503可經由穿孔522及內連線240電連接到第一半導體晶片501。第三半導體晶片503可經由穿孔522及第一導電結構120電連接到封裝基底1000。
圖7A是說明根據本發明概念示例性實施例的半導體封裝的平面圖。圖7B是沿圖7A所示線VIIB-VIIB’截取的剖視圖。在下文中，為容易及方便地進行解釋，與以上示例性實施例相同的元件的說明將予以省略或僅簡要提及。
參照圖7A及圖7B，半導體封裝7可包括封裝基底1000、第一凸塊710、第一基底100、第二基底200、模塑圖案400、半導體晶片501及502、以及第三基底300。第一基底100可設置在封裝基底1000上。第一基底100可包括第一基礎層110及第一導電結構120。第一基礎層110及第一導電結構120可與參照圖1A及圖1B所闡述的第一基礎層110及第一導電結構120實質上相同。第一導電結構120可電連接到第一凸塊710。然而，不同於圖1A及圖1B，第一基底100可不具有孔190。
第二基底200可設置在封裝基底1000上。第二基底200可在橫向上與第一基底100間隔開。舉例來說，第二基底200可在第一方向D1上與第一基底100間隔開。第二基底200可包括第二基礎層210、內連線240及第二上部接墊250。第二上部接墊250的節距可小於第一上部接墊150的節距。虛擬凸塊721可設置在封裝基底1000與第二基底200之間。儘管圖式中未示出，然而，第二基底200可進一步包括圖2所示第二導電結構220。
第三基底300可設置在封裝基底1000上。第三基底300可在第一方向D1上與第二基底200間隔開。第三基底300的頂表面300a可設置在與第二基底200的頂表面200a以及第一基底100的頂表面100a實質上相同的水平高度上。第三基底300可包括第三基礎層310、第三導電結構320及第三上部接墊350。第三基礎層310、第三導電結構320及第三上部接墊350可分別與參照圖1A及圖1B闡述的第一基礎層110、第一導電結構120及第一上部接墊150實質上相同。第三導電結構320可彼此電隔離。第三導電結構320可包括第三下部接墊321、第三通孔322及第三導電圖案323。第三上部接墊350的節距可不同於第二上部接墊250的節距。舉例來說，第三上部接墊350的節距可大於第二上部接墊250的節距。第三上部接墊350的節距可等於或不同於第一上部接墊150的節距。第三凸塊730可設置在封裝基底1000與第三基底300之間。第三導電結構320可經由第三凸塊730電連接到封裝基底1000。
半導體晶片501及502可包括第一半導體晶片501及第二半導體晶片502。第一半導體晶片501可安裝在第一基底100及第二基底200上。第一半導體晶片501可與參照圖1A及圖1B闡述的半導體晶片500中的一個相同。舉例來說，在第一半導體晶片501的一個表面501b上可設置有第一接墊510及第二接墊520。第二接墊520的第二節距P2可小於第一接墊510的第一節距P1。第一半導體晶片501可經由第一連接部610連接到第一基底100。第一半導體晶片501可經由第二連接部620電連接到第二基底200的內連線240。
第二半導體晶片502可安裝在第二基底200及第三基底300上。第二半導體晶片502可在橫向上與第一半導體晶片501間隔開。舉例來說，第二半導體晶片502可在第一方向D1上與第一半導體晶片501間隔開。第二半導體晶片502的一個表面502b可面對第二基底200及第三基底300。在第二半導體晶片502的一個表面502b上可設置有第二接墊520及第三接墊530。在平面圖中，第二半導體晶片502的第二接墊520可與第二基底200重疊，且第二半導體晶片502的第三接墊530可與第三基底300重疊。第三接墊530可具有第三節距P3。第二節距P2可不同於第三節距P3。舉例來說，第二節距P2可小於第三節距P3。第三節距P3可等於或不同於第一節距P1。
第二半導體晶片502的第二接墊520可經由第二連接部620電連接到第二基底200。第二半導體晶片502可經由內連線240電連接到第一半導體晶片501。
第二半導體晶片502的第三接墊530可經由第三基底300電連接到封裝基底1000。舉例來說，第二半導體晶片502的第三接墊530可經由第三基底300的第三導電結構320電連接到封裝基底1000。在第三基底300與第二半導體晶片502之間可設置有第三連接部630。第三連接部630可連接到第三上部接墊350及第三接墊530。第三接墊530的第三節距P3可實質上等於第三連接部630的節距以及第三上部接墊350的節距。在一些示例性實施例中，由於設置有第三基底300，因此對第二半導體晶片502的接墊520的節距P2以及接墊530的節距P3的設計的限制可減少。第三導電結構320可向第二半導體晶片502傳送電訊號或電壓或者可將第二半導體晶片502接地。
模塑圖案400可填充第一基底100與第二基底200之間的間隙以及第二基底200與第三基底300之間的間隙。另外，模塑圖案400可延伸到第一基底100的底表面100b上、第二基底200的底表面200b上及/或第三基底300的底表面300b上。
圖8A至圖8E是與圖1A所示線IB-IB’對應的剖視圖，其示出根據本發明概念示例性實施例的製造半導體封裝的方法。在下文中，為容易及方便地進行解釋，與以上示例性實施例相同的特徵的說明將予以省略或僅簡要提及。
參照圖1及圖8A，可將第一基底100設置在支撐基底800上。第一基底100的頂表面100a可與黏合層810實體接觸。第一基底100可通過黏合層810而黏合到支撐基底800。舉例來說，可使用印刷電路板（PCB）作為第一基底100。第一基底100可包括第一基礎層110、第一導電結構120及第一上部接墊150。第一上部接墊150可具有第一節距。
參照圖1A及圖8B，可在第一基底100中形成孔190。舉例來說，可移除第一基底100的一部分來形成孔190。當在平面圖中觀察時，可在第一基底100的中心部分中形成孔190。孔190可暴露出黏合層810。
參照圖1A及圖8C，可將第二基底200及模塑圖案400設置在支撐基底800上。第二基底200可設置在第一基底100的孔190中。可將第二基底200的頂表面200a黏合到黏合層810。可將第二基底200的頂表面200a設置在與第一基底100的頂表面100a相同的水平高度上。第二基底200可包括第二基礎層210、內連線240及第二上部接墊250。第二上部接墊250可具有第二節距。第二節距可小於第一節距。模塑圖案400可形成在第一基底100的底表面100b上以及第二基底200的底表面200b上。另外，模塑圖案400可延伸到第一基底100與第二基底200之間的間隙中。
參照圖1A及圖8D，可移除模塑圖案400的一些部分以形成開口405。開口405可形成在模塑圖案400中。開口405可暴露出第一下部接墊121。之後，可移除支撐基底800及黏合層810以暴露出第一基底100的頂表面100a以及第二基底200的頂表面200a。可將第二基底200的頂表面200a設置在與第一基底100的頂表面100a實質上相同的水平高度上。
參照圖1A及圖8E，可將半導體晶片500安裝在第一基底100及第二基底200上。舉例來說，可在半導體晶片500中的每一者的一個表面500b上形成第一接墊510及第二接墊520。可在第一基底100及第二基底200上將半導體晶片500中的每一者設置成使得第一接墊510及第二接墊520分別與第一上部接墊150及第二上部接墊250對齊。可在第一上部接墊150與第一接墊510之間形成第一連接部610。半導體晶片500可經由第一連接部610連接到第一基底100。可在第二上部接墊250與第二接墊520之間形成第二連接部620。半導體晶片500可經由第二連接部620連接到第二基底200。由於第一基底100的頂表面100a與第二基底200的頂表面200a設置在實質上相同的水平高度上，因此可容易地將半導體晶片500安裝在第一基底100及第二基底200上。可在半導體晶片500的表面500b上形成底部填充層410。底部填充層410可密封第一連接部610及第二連接部620。可在第一基底100的底表面100b上形成焊料710'以連接到第一下部接墊121。
再次參照圖1A及圖1B，可將第一基底100及第二基底200安裝在封裝基底1000上以製造半導體封裝1。可將焊料710'連接到封裝基底1000以使焊料710'形成到第一凸塊710中。在一些示例性實施例中，可在封裝基底1000上形成封裝焊料（圖中未示出）。圖8E所示焊料710'可與封裝焊料接觸，且可對焊料710'以及封裝焊料執行回焊製程以形成第一凸塊710。可通過第一基底100及第一凸塊710將半導體晶片500連接到封裝基底1000。
在某些示例性實施例中，在圖8A至圖8E所示的製造方法中，可使用包括第二導電結構220的第二基底200來製造圖2所示半導體封裝2。可進一步在封裝基底1000與第二基底200之間形成虛擬凸塊721以製造圖3所示半導體封裝3。
根據本發明概念的一些示例性實施例，半導體晶片中的每一者可具有第一接墊及第二接墊。第二接墊的節距可不同於第一接墊的節距。可將半導體晶片中的每一者安裝在第一基底及第二基底上。第二基底的第二上部接墊的節距可不同於第一基底的第一上部接墊的節距。通過在半導體封裝中設置這種第二基底，可以較少的設計約束條件來設計並製造第一基底的第一上部接墊。結果，可減少對半導體晶片的接墊的節距的限制，從而對半導體晶片的電路圖案進行各種設計。
儘管已參照一些示例性實施例闡述了本發明概念，然而對所屬領域中的技術人員來說將顯而易見的是，在不背離本發明概念的精神及範圍的條件下，可作出各種改變及潤飾。因此，應理解，以上示例性實施例並非限制性的，而是說明性的。因此，本發明概念的範圍應由以上權利要求及其等效範圍所許可的最廣範圍的解釋來確定，而不應受上述說明約束或限制。
1、2、3、4、5、6、7‧‧‧半導體封裝100‧‧‧第一基底100a、200a、300a‧‧‧頂表面100b、190b、200b、300b‧‧‧底表面110‧‧‧第一基礎層120‧‧‧第一導電結構121‧‧‧第一下部接墊122‧‧‧第一通孔123‧‧‧第一導電圖案140‧‧‧連接通孔150‧‧‧第一上部接墊190‧‧‧孔200‧‧‧第二基底210‧‧‧第二基礎層220‧‧‧第二導電結構221‧‧‧第二下部接墊222‧‧‧第二通孔223‧‧‧第二導電圖案240‧‧‧內連線250‧‧‧第二上部接墊300‧‧‧第三基底310‧‧‧第三基礎層320‧‧‧第三導電結構321‧‧‧第三下部接墊322‧‧‧第三通孔323‧‧‧第三導電圖案350‧‧‧第三上部接墊400‧‧‧模塑圖案405‧‧‧開口410‧‧‧底部填充層500‧‧‧半導體晶片500b、501b、502b‧‧‧表面501‧‧‧半導體晶片502‧‧‧半導體晶片503‧‧‧半導體晶片510‧‧‧第一接墊520‧‧‧接墊522‧‧‧穿孔530‧‧‧接墊610‧‧‧第一連接部620‧‧‧第二連接部630‧‧‧第三連接部710‧‧‧第一凸塊710'‧‧‧焊料720‧‧‧第二凸塊721‧‧‧虛擬凸塊730‧‧‧第三凸塊800‧‧‧支撐基底810‧‧‧黏合層1000‧‧‧封裝基底D1‧‧‧第一方向D2‧‧‧第二方向D3‧‧‧第三方向P1‧‧‧第一節距P2‧‧‧節距P3‧‧‧節距IB-IB’、VIIB-VIIB’‧‧‧線
根據附圖及隨附詳細說明，本發明概念將變得更顯而易見。 圖1A是說明根據本發明概念示例性實施例的半導體封裝的平面圖。 圖1B是沿圖1A所示線IB-IB’截取的剖視圖。 圖2是說明根據本發明概念示例性實施例的半導體封裝的剖視圖。 圖3是說明根據本發明概念示例性實施例的半導體封裝的剖視圖。 圖4是說明根據本發明概念示例性實施例的半導體封裝的剖視圖。 圖5是說明根據本發明概念示例性實施例的半導體封裝的剖視圖。 圖6是說明根據本發明概念示例性實施例的半導體封裝的剖視圖。 圖7A是說明根據本發明概念示例性實施例的半導體封裝的平面圖。 圖7B是沿圖7A所示線VIIB-VIIB’ 截取的剖視圖。 圖8A至圖8E是說明根據本發明概念示例性實施例的製造半導體封裝的方法的剖視圖。
1‧‧‧半導體封裝
100‧‧‧第一基底
100a、200a‧‧‧頂表面
100b、200b‧‧‧底表面
110‧‧‧第一基礎層
120‧‧‧第一導電結構
121‧‧‧第一下部接墊
122‧‧‧第一通孔
123‧‧‧第一導電圖案
150‧‧‧第一上部接墊
190‧‧‧孔
200‧‧‧第二基底
210‧‧‧第二基礎層
240‧‧‧內連線
250‧‧‧第二上部接墊
400‧‧‧模塑圖案
410‧‧‧底部填充層
500‧‧‧半導體晶片
500b‧‧‧表面
510‧‧‧第一接墊
520‧‧‧接墊
610‧‧‧第一連接部
620‧‧‧第二連接部
710‧‧‧第一凸塊
1000‧‧‧封裝基底
D1‧‧‧第一方向
D3‧‧‧第三方向
P1‧‧‧第一節距
P2‧‧‧節距

Claims (24)

  1. 一種半導體封裝，包括：第一基底，包括第一上部接墊，所述第一上部接墊位於所述第一基底的頂表面上；第二基底，包括第二上部接墊，所述第二上部接墊位於所述第二基底的頂表面上，所述第二上部接墊的節距小於所述第一上部接墊的節距；第一半導體晶片，位於以下兩者上並電連接到以下兩者：(i)所述第一上部接墊中的至少一個以及(ii)所述第二上部接墊中的至少一個；以及模塑圖案，位於所述第一基底的底表面上以及所述第二基底的底表面上。
  2. 如申請專利範圍第1項所述的半導體封裝，其中，所述第一半導體晶片包括多個第一半導體晶片，且所述第一半導體晶片沿橫向排列。
  3. 如申請專利範圍第2項所述的半導體封裝，其中，所述第一半導體晶片中的一個連接到所述第二上部接墊中的一個，所述第一半導體晶片中的另一個連接到所述第二上部接墊中的另一個，且所述第二基底包括內連線，所述內連線連接到所述第二上部接墊中的所述一個及所述第二上部接墊中的所述另一個。
  4. 如申請專利範圍第3項所述的半導體封裝，進一步包括：導電結構，位於所述第二基底中，所述導電結構電連接到所述第二上部接墊中的所述至少一個，所述導電結構與所述內連線電隔離；以及凸塊，位於所述第二基底的所述底表面上，所述凸塊電連接到所述導電結構。
  5. 如申請專利範圍第4項所述的半導體封裝，其中，所述導電結構包括位於所述第二基底的所述底表面上的下部接墊，且所述第二上部接墊不與所述下部接墊垂直對齊。
  6. 如申請專利範圍第1項所述的半導體封裝，進一步包括：第二半導體晶片，位於所述第一基底及所述第二基底上，所述第二半導體晶片位於所述第一半導體晶片的一側；以及第三半導體晶片，位於所述第二半導體晶片上。
  7. 如申請專利範圍第1項所述的半導體封裝，進一步包括：第三基底，位於所述第二基底的一側，所述第三基底包括位於所述第三基底的頂表面上的第三上部接墊；以及第二半導體晶片，位於所述第二基底及所述第三基底上，所述第二半導體晶片電連接到所述第二上部接墊中的至少另一個及所述第三上部接墊中的至少一個。
  8. 一種半導體封裝，包括：第一基底，具有孔；第二基底，位於所述第一基底的所述孔中； 至少一個半導體晶片，位於所述第一基底及所述第二基底上；第一連接部，位於所述第一基底與所述半導體晶片之間；第二連接部，位於所述第二基底與所述半導體晶片之間，所述第二連接部的節距小於所述第一連接部的節距；以及模塑圖案，位於所述第一基底的底表面上以及所述第二基底的底表面上且延伸到所述第一基底與所述第二基底之間的間隙中。
  9. 如申請專利範圍第8項所述的半導體封裝，其中，所述第二基底包括電連接到所述第二連接部中的至少兩個的內連線。
  10. 如申請專利範圍第9項所述的半導體封裝，其中，所述至少一個半導體晶片包括多個半導體晶片，且所述半導體晶片中的一個經由所述內連線電連接到所述半導體晶片中的另一個。
  11. 如申請專利範圍第8項所述的半導體封裝，其中，所述孔穿透所述第一基底的所述頂表面及所述底表面，且所述第一基底的所述頂表面及所述底表面彼此相對。
  12. 一種半導體封裝，包括：多個半導體晶片，沿橫向排列；第一接墊，位於所述半導體晶片的表面上；第二接墊，位於所述半導體晶片的所述表面上；第一基底，經由所述第一接墊電連接到所述半導體晶片，所述第一基底的頂表面面對所述半導體晶片的所述表面； 第二基底，經由所述第二接墊電連接到所述半導體晶片，所述第二基底的頂表面面對所述半導體晶片的所述表面，所述第二接墊的節距小於所述第一接墊的節距；以及模塑圖案，位於所述第一基底的底表面上以及所述第二基底的底表面上且延伸到所述第一基底與所述第二基底之間的間隙中，其中所述第一基底的所述頂表面及所述底表面彼此相對，以及其中所述第二基底的所述頂表面及所述底表面彼此相對。
  13. 如申請專利範圍第12項所述的半導體封裝，其中，所述第二基底包括將所述第二接墊中的至少兩個電連接到彼此的內連線。
  14. 如申請專利範圍第13項所述的半導體封裝，其中，所述半導體晶片包括第一半導體晶片及第二半導體晶片，且所述第一半導體晶片經由所述內連線電連接到所述第二半導體晶片。
  15. 如申請專利範圍第13項所述的半導體封裝，進一步包括：導電結構，位於所述第二基底中，所述導電結構電連接到所述第二接墊中的至少一個，所述導電結構包括導電通孔及導電接墊，所述導電接墊位於所述第二基底的所述底表面上，所述第二 基底的所述底表面與所述第二基底的所述頂表面相對，所述第二基底的所述頂表面面對所述半導體晶片。
  16. 如申請專利範圍第15項所述的半導體封裝，其中，所述導電結構與所述內連線電隔離。
  17. 如申請專利範圍第13項所述的半導體封裝，其中，所述第一基底包括第一基底層及位於所述第一基底層中的第一導電結構，且所述第一導電結構電連接到所述第一接墊。
  18. 如申請專利範圍第12項所述的半導體封裝，進一步包括：封裝基底，其中所述第一基底及所述第二基底位於所述封裝基底上，且所述第一基底及所述第二基底垂直地位於所述封裝基底與所述半導體晶片之間。
  19. 如申請專利範圍第18項所述的半導體封裝，進一步包括：第一凸塊，位於所述封裝基底與所述第一基底之間，且電連接到所述第一基底；以及虛擬凸塊，位於所述封裝基底與所述第二基底之間，所述虛擬凸塊與所述第二基底電隔離。
  20. 如申請專利範圍第18項所述的半導體封裝，其中，所述第一基底包括印刷電路板，且 所述第二基底包括印刷電路板。
  21. 一種半導體封裝，包括：第一基底，包括位於所述第一基底的第一表面上的第一基底接墊，所述第一基底接墊具有第一節距；第二基底，包括位於所述第二基底的第一表面上的第二基底接墊，所述第二基底接墊具有第二節距，所述第二節距小於所述第一節距；第一半導體晶片，包括第一晶片接墊及第二晶片接墊，所述第一晶片接墊具有第三節距，所述第二晶片接墊具有第四節距，所述第四節距小於所述第三節距，所述第一半導體晶片位於所述第一基底接墊中的至少一個與所述第二基底接墊中的至少一個上以使所述第一晶片接墊中的一個電耦合到所述第一基底接墊中的所述至少一個且所述第二晶片接墊中的一個電耦合到所述第二基底接墊中的所述至少一個；以及模塑圖案，位於所述第一基底的第二表面上以及所述第二基底的第二表面上且延伸到所述第一基底與所述第二基底之間的間隙中，其中所述第一基底的所述第一表面及所述第二表面彼此相對，以及其中所述第二基底的所述第一表面及所述第二表面彼此相對。
  22. 如申請專利範圍第21項所述的半導體封裝，進一步包括：第一連接部，將所述第一晶片接墊中的所述一個與所述第一基底接墊中的所述至少一個電耦合；以及第二連接部，將所述第二晶片接墊中的所述一個與所述第二基底接墊中的所述至少一個電耦合。
  23. 如申請專利範圍第21項所述的半導體封裝，其中，所述第二基底包括將所述第二基底接墊中的至少兩個電連接到彼此的內連線。
  24. 如申請專利範圍第21項所述的半導體封裝，其中，所述第一基底包括完全地穿過所述第一基底的孔，且所述第二基底容置在所述孔中。
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