TW201830598A - 具有虛設連接器的半導體封裝及其形成方法 - Google Patents
具有虛設連接器的半導體封裝及其形成方法 Download PDFInfo
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- TW201830598A TW201830598A TW106131638A TW106131638A TW201830598A TW 201830598 A TW201830598 A TW 201830598A TW 106131638 A TW106131638 A TW 106131638A TW 106131638 A TW106131638 A TW 106131638A TW 201830598 A TW201830598 A TW 201830598A
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Abstract
一種實施例封裝包含一第一封裝。該第一封裝包含:一第一積體電路晶粒;一囊封劑,其圍繞該第一積體電路晶粒;及重佈層,其位於該囊封劑及該第一積體電路晶粒上方。該封裝亦包含藉由複數個功能連接器來接合至該第一封裝之一第二封裝。該等功能連接器及該等重佈層將該第二封裝之一第二積體電路晶粒電連接至該第一積體電路晶粒。該封裝亦包含經安置於該第一封裝與該第二封裝之間的複數個虛設連接器。面向該第一封裝之該複數個虛設連接器之各者之一端與該第一封裝實體分離。
Description
本發明實施例係關於具有虛設連接器的半導體封裝及其形成方法。
歸因於各種電子組件(例如電晶體、二極體、電阻器、電容器等等)之整合密度不斷提高,半導體業已經歷快速增長。整合密度之提高多半源於最小構件大小之反覆減小,此允許將更多組件整合至一給定區域中。隨著縮小電子裝置之需求不斷增長,需要更小且更具創意之半導體晶粒封裝技術。此等封裝系統之一實例係堆疊封裝(PoP)技術。在一PoP裝置中,一頂部半導體封裝經堆疊於一底部半導體封裝之頂部上以提供一高整合度及組件密度。PoP技術一般能夠在一印刷電路板(PCB)上產生具有增強功能及小佔用面積之半導體裝置。
根據本發明的一實施例,一種封裝包括:一第一封裝,其包括一第一積體電路晶粒、圍繞該第一積體電路晶粒之一囊封劑及位於該囊封劑及該第一積體電路晶粒上方之一重佈層;一第二封裝,其藉由複數個功能連接器來接合至該第一封裝,其中該等功能連接器及該重佈層將該第二封裝之一第二積體電路晶粒電連接至該第一積體電路晶粒;及複數個虛設連接器,其等經安置於該第一封裝與該第二封裝之間,其中面向該第一封裝之該複數個虛設連接器之各者之一端與該第一封裝實體分離。 根據本發明的一實施例,一種封裝包括:一第一封裝組件,其包括經囊封於一囊封劑中之一第一半導體晶粒、延伸貫穿該囊封劑之一導電通路及經電連接至該第一半導體晶粒及該導電通路之一重佈層;一第二封裝組件,其藉由經安置於該第二封裝組件之一底面上的第一複數個連接器來實體接合至該第一封裝組件;第二複數個連接器,其等經安置於該第二封裝組件之該底面上,其中該第二複數個連接器與該第一半導體晶粒電隔離;且其中該第一複數個連接器及該第二複數個連接器具有不同大小。 根據本發明的一實施例,一種方法包括:將一第一積體電路晶粒囊封於一囊封劑中;形成經電連接至該第一積體電路晶粒之一重佈層(RDL);使用複數個功能連接器將一基板接合至該RDL,其中該複數個功能連接器將一第二積體電路晶粒電連接至該第一積體電路晶粒,且其中該第一積體電路晶粒及該第二積體電路晶粒經安置於該基板之對置側上;將複數個虛設連接器安置於該基板與該RDL之間,其中在一俯視圖中,該複數個功能連接器在該複數個虛設連接器下方延伸,且其中該複數個功能連接器至少部分環繞該複數個虛設連接器;及將一底膠施配於該基板與該RDL之間。
以下揭露提供用於實施本發明實施例之不同特徵的諸多不同實施例或實例。下文將描述組件及配置之具體實例以簡化本揭露。當然,此等僅為實例且不意在限制。例如,在以下描述中,「使一第一構件形成於一第二構件上方或一第二構件上」可包含其中形成直接接觸之該第一構件及該第二構件的實施例,且亦可包含其中額外構件可形成於該第一構件與該第二構件之間使得該第一構件及該第二構件可不直接接觸的實施例。另外,本揭露可在各種實例中重複元件符號及/或字母。此重複旨在簡化及清楚且其本身不指示所討論之各種實施例及/或組態之間的一關係。 此外,為了方便描述,可在本文中使用空間相對術語(諸如「下面」、「下方」、「下」、「上方」、「上」及其類似者)來描述一元件或構件與另一(些)元件或構件之關係,如圖中所繪示。除圖中所描繪之定向之外,空間相對術語亦意欲涵蓋裝置在使用或操作中之不同定向。設備可依其他方式定向(旋轉90度或依其他定向),且亦可據此解譯本文中所使用之空間相對描述詞。 可在一特定背景(即,具有經安置於一第一封裝組件與一第二封裝組件之間的虛設連接器的一封裝結構(例如一堆疊封裝(PoP)結構))中討論本文中所討論之實施例。在一些實施例中,該第二封裝組件係一記憶體封裝(例如,具有一或多個動態隨機存取記憶體(DRAM)晶粒),其使用功能連接器來實體及電耦合至該第一封裝組件(例如具有一邏輯晶粒及重佈結構之一整合式扇出(InFO)封裝)。該等虛設連接器可與該第一封裝組件之功能電路(例如該邏輯晶粒及該等重佈結構)實體及/或電斷接。在一些實施例中,該等虛設連接器亦可與該第二封裝組件之功能電路電斷接。 在一俯視圖中,該等功能連接器可經安置於該第一封裝組件及該第二封裝組件之一周邊處。在該俯視圖中,該等虛設連接器可經安置於該第一封裝組件及該第二封裝組件之一中央區域處。在一些實施例中,在該俯視圖中,該等功能連接器可環繞該等虛設連接器。在將該第一封裝組件及該第二封裝組件接合在一起之後,可將一底膠施配於該第一封裝組件與該第二封裝組件之間及該等功能連接器及該等虛設連接器周圍。經觀察,可藉由將虛設連接器包含於各種實施例封裝中來在施配期間平整該底膠之一波前。一平整波前可減少該第一封裝組件與該第二封裝組件之間的該底膠中之缺陷(例如空隙之存在及/或大小)。與無虛設連接器之實施例相比,可減少底膠缺陷(例如空隙),此可導致可靠性測試前及可靠性測試後之較高良率及較少製造缺陷。例如,較大空隙或較多空隙可導致可靠性測試後之一爆米花效應,此可引起封裝失效。可藉由包含虛設連接器來減少此等空隙之數量及大小兩者。 此外,本揭露之教示適用於包含接合兩個封裝組件之功能連接器的任何封裝結構。其他實施例涵蓋其他應用,諸如一般技術者將在閱讀本揭露之後輕易明白之不同封裝類型或不同組態。應注意,本文中所討論之實施例可不必繪示可存在於一結構中之每個組件或構件。例如,諸如當討論一個組件可足以傳達實施例之態樣時,可自一圖省略多個該組件。此外,本文中所討論之方法實施例可經討論為依一特定順序執行;然而,其他方法實施例可依任何邏輯順序執行。 圖1至圖20繪示根據一些實施例之用於形成一第一封裝組件之一程序期間之中間步驟之橫截面圖。圖1繪示一載體基板100及經形成於載體基板100上之一離型層(release layer) 102。圖中分別繪示用於形成一第一封裝及一第二封裝之一第一封裝區域600及一第二封裝區域602。 載體基板100可為一玻璃載體基板、一陶瓷載體基板或其類似者。載體基板100可為一晶圓,使得多個封裝可同時形成於載體基板100上。離型層102可由一基於聚合物之材料形成,其可與載體基板100一起自將在後續步驟中形成之上覆結構移除。在一些實施例中,離型層102係一基於環氧樹脂之熱離型材料(其在被加熱時失去其黏著性),諸如一光熱轉換(LTHC)離型塗層。在其他實施例中,離型層102可為一紫外線(UV)膠,其在曝露於UV光時失去其黏著性。離型層102可經施配為一液體且經固化,可為經層疊至載體基板100上之一層疊膜,或可為類似者。離型層102之頂面可經整平且可具有一高度共面性。 在圖2中,形成一介電層104及一金屬化圖案106 (有時指稱一重佈層106或重佈線106)。如圖2中所繪示,一介電層104經形成於離型層102上。介電層104之底面可與離型層102之頂面接觸。在一些實施例中,介電層104由一聚合物(諸如聚苯並㗁唑(PBO)、聚醯亞胺、苯並環丁烯(BCB)或其類似者)形成。在其他實施例中,介電層104由氮化物(諸如氮化矽)、氧化物(諸如氧化矽、磷矽酸鹽玻璃(PSG)、硼矽酸鹽玻璃(BSG)、摻硼磷矽酸鹽玻璃(BPSG)或其類似者)或其類似者形成。可藉由諸如旋塗、化學氣相沈積(CVD)、層疊、類似者或其等之一組合的任何可接受沈積程序來形成介電層104。 金屬化圖案106經形成於介電層104上。作為形成金屬化圖案106之一實例,一晶種層(圖中未展示)經形成於介電層104上方。在一些實施例中,晶種層係一金屬層,其可為一單一層或包括由不同材料形成之複數個子層的一複合層。在一些實施例中,晶種層包括一鈦層及該鈦層上方之一銅層。可使用(例如) PVD或其類似者來形成晶種層。接著,一光阻層經形成且圖案化於晶種層上。可藉由旋塗或其類似者來形成光阻層,且可使光阻層曝光以圖案化。光阻層之圖案對應於金屬化圖案106。圖案化形成貫穿光阻層之開口以曝露晶種層。一導電材料經形成於光阻層之開口中及晶種層之曝露部分上。可藉由鍍覆(諸如電鍍或無電電鍍或其類似者)來形成導電材料。導電材料可包括一金屬,如銅、鈦、鎢、鋁或其類似者。接著,移除光阻層及其上未形成導電材料之晶種層之部分。可藉由一可接受灰化或剝離程序(諸如,使用氧電漿或其類似者)來移除光阻層。一旦已移除光阻層,則(諸如)藉由使用一可接受蝕刻程序(諸如,藉由濕式或乾式蝕刻)來移除晶種層之曝露部分。晶種層之剩餘部分及導電材料形成金屬化圖案106。 在圖3中,一介電層108經形成於金屬化圖案106及介電層104上。在一些實施例中,介電層108由一聚合物形成,該聚合物可為可使用一微影光罩來圖案化之一光敏材料,諸如PBO、聚醯亞胺、BCB或其類似者。在其他實施例中,介電層108由氮化物(諸如氮化矽)、氧化物(諸如氧化矽、PSG、BSG、BPSG)或其類似者形成。可藉由旋塗、層疊、CVD、類似者或其等之一組合來形成介電層108。接著,圖案化介電層108以形成開口來曝露金屬化圖案106之部分。圖案化可藉由一可接受程序,諸如:當介電層係一光敏材料時,藉由使介電層108曝光;或藉由使用(例如)一各向異性蝕刻之蝕刻。 介電層104及108及金屬化圖案106可指稱一後側重佈結構110。如圖中所繪示,後側重佈結構110包含兩個介電層104及108及一個金屬化圖案106。在其他實施例中,後側重佈結構110可包含任何數目個介電層、金屬化圖案及通路。可藉由重複用於形成一金屬化圖案106及介電層108之程序來使一或多個額外金屬化圖案及介電層形成於後側重佈結構110中。可在一金屬化圖案之形成期間藉由使晶種層及金屬化圖案之導電材料形成於下伏介電層之開口中來形成通路。因此,通路可互連且電耦合各種金屬化圖案。 此外,在圖3中,形成貫穿通路112。作為形成貫穿通路112之一實例,一晶種層經形成於後側重佈結構110 (例如介電層108及金屬化圖案106之曝露部分,如圖中所繪示)上方。在一些實施例中,晶種層係一金屬層,其可為一單一層或包括由不同材料形成之複數個子層的一複合層。在一些實施例中,晶種層包括一鈦層及該鈦層上方之一銅層。可使用(例如) PVD或其類似者來形成晶種層。一光阻層經形成且圖案化於晶種層上。可藉由旋塗或其類似者來形成光阻層,且可使光阻層曝光以圖案化。光阻層之圖案對應於貫穿通路。圖案化形成貫穿光阻層以曝露晶種層之開口。一導電材料經形成於光阻層之開口中及晶種層之曝露部分上。可藉由鍍覆(諸如電鍍或無電電鍍或其類似者)來形成導電材料。導電材料可包括一金屬,如銅、鈦、鎢、鋁或其類似者。移除光阻層及其上未形成導電材料之晶種層之部分。可藉由一可接受灰化或剝離程序(諸如,使用氧電漿或其類似者)來移除光阻層。一旦已移除光阻層,則(諸如)藉由使用一可接受蝕刻程序(諸如,藉由濕式或乾式蝕刻)來移除晶種層之曝露部分。晶種層之剩餘部分及導電材料形成貫穿通路112。 在圖4中,藉由一黏著劑116將積體電路晶粒114黏附至介電層108。如圖4中所繪示,將兩個積體電路晶粒114黏附於第一封裝區域600及第二封裝區域602之各者中,且在其他實施例中,可將更多或更少積體電路晶粒114黏附於各區域中。例如,在一實施例中,可將僅一個積體電路晶粒114黏附於各區域中。積體電路晶粒114可為邏輯晶粒(例如中央處理單元、微控制器等等)、記憶體晶粒(例如動態隨機存取記憶體(DRAM)晶粒、靜態隨機存取記憶體(SRAM)晶粒等等)、電源管理晶粒(例如電源管理積體電路(PMIC)晶粒)、射頻(RF)晶粒、感測器晶粒、微機電系統(MEMS)晶粒、信號處理晶粒(例如數位信號處理(DSP)晶粒)、前端晶粒(例如類比前端(AFE)晶粒)、類似者或其等之一組合。此外,在一些實施例中,積體電路晶粒114可為不同大小(例如不同高度及/或表面積),且在其他實施例中,積體電路晶粒114可為相同大小(例如相同高度及/或表面積)。 積體電路晶粒114可在黏附至介電層108之前根據適用製程來處理以在積體電路晶粒114中形成積體電路。例如,積體電路晶粒114各包含一半導體基板118,諸如摻雜或未摻雜矽或一絕緣體上覆半導體(SOI)基板之一主動層。半導體基板可包含其他半導體材料,諸如:鍺;化合物半導體,其包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦;合金半導體,其包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP;或其等之組合。亦可使用諸如多層或梯度基板之其他基板。諸如電晶體、二極體、電容器、電阻器等等之裝置可經形成於半導體基板118中及/或半導體基板118上,且可由互連結構120 (其由(例如)半導體基板118上之一或多個介電層中之金屬化圖案形成)互連以形成一積體電路。 積體電路晶粒114進一步包括與外部連接之襯墊122,諸如鋁襯墊。襯墊122位於積體電路晶粒114之所謂各自主動側上。鈍化膜124位於積體電路晶粒114及襯墊122之部分上。開口貫穿鈍化膜124而至襯墊122。晶粒連接器126 (諸如導電柱)(例如,包括諸如銅之一金屬)位於貫穿鈍化膜124之開口中且經機械及電耦合至各自襯墊122。可藉由(例如)鍍覆或其類似者來形成晶粒連接器126。晶粒連接器126電耦合積體電路晶粒114之各自積體電路。 一介電材料128位於積體電路晶粒114之主動側上,諸如,位於鈍化膜124及晶粒連接器126上。介電材料128橫向囊封晶粒連接器126,且介電材料128與各自積體電路晶粒114橫向相連。介電材料128可為聚合物(諸如PBO、聚醯亞胺、BCB或其類似者)、氮化物(諸如氮化矽或其類似者)、氧化物(諸如氧化矽、PSG、BSG、BPSG或其類似者)、類似者或其等之一組合,且可(例如)藉由旋塗、層疊、CVD或其類似者來形成。 黏著劑116位於積體電路晶粒114之後側上且將積體電路晶粒114黏附至後側重佈結構110,諸如說明圖中之介電層108。黏著劑116可為任何適合黏著劑、環氧樹脂、晶粒附著膜(DAF)或其類似者。黏著劑116可經施加於積體電路晶粒114之一後側(諸如各自半導體晶圓之一後側)或可經施加於載體基板100之表面上方。積體電路晶粒114可(諸如)藉由鋸切或切割來單粒化,且可使用(例如)一取置工具藉由黏著劑116來黏附至介電層108。 在圖5中,一囊封劑130經形成於各種組件上。囊封劑130可為模製化合物、環氧樹脂或其類似者,且可藉由壓縮模製、轉移模製或其類似者來施加。在固化之後,囊封劑130可經歷一研磨程序以曝露貫穿通路112及晶粒連接器126。在研磨程序之後,貫穿通路112、晶粒連接器126及囊封劑130之頂面係共面的。在一些實施例中,若(例如)已曝露貫穿通路112及晶粒連接器126,則可省略研磨。 在圖6至圖15及圖19中,形成一前側重佈結構160。如圖19中將繪示,前側重佈結構160包含介電層132、140、148及156及金屬化圖案138、146及154 (有時指稱重佈層138、146及154或重佈線138、146及154)。 在圖6中,介電層132經沈積於囊封劑130、貫穿通路112及晶粒連接器126上。在一些實施例中,介電層132由一聚合物形成,該聚合物可為可使用一微影光罩來圖案化之一光敏材料,諸如PBO、聚醯亞胺、BCB或其類似者。在其他實施例中,介電層132由氮化物(諸如氮化矽)、氧化物(諸如氧化矽、PSG、BSG、BPSG)或其類似者形成。可藉由旋塗、層疊、CVD、類似者或其等之一組合來形成介電層132。 接著,在圖7中,圖案化介電層132。圖案化形成開口以曝露貫穿通路112及晶粒連接器126之部分。圖案化可藉由一可接受程序,諸如:當介電層132係一光敏材料時,藉由使介電層132曝光;或藉由使用(例如)一各向異性蝕刻之蝕刻。若介電層132係一光敏材料,則可在曝露之後使介電層132顯影。 在圖8中,具有通路之金屬化圖案138經形成於介電層132上。作為形成金屬化圖案138之一實例,一晶種層(圖中未展示)經形成於介電層132上方及貫穿介電層132之開口中。在一些實施例中,晶種層係一金屬層,其可為一單一層或包括由不同材料形成之複數個子層的一複合層。在一些實施例中,晶種層包括一鈦層及該鈦層上方之一銅層。可使用(例如) PVD或其類似者形成晶種層。接著,一光阻層經形成且圖案化於晶種層上。光阻層可藉由旋塗或其類似者來形成且可經曝光以圖案化。光阻層之圖案對應於金屬化圖案138。圖案化形成貫穿光阻層以曝露晶種層之開口。一導電材料經形成於光阻層之開口中及晶種層之曝露部分上。可藉由鍍覆(諸如電鍍或無電電鍍或其類似者)來形成導電材料。導電材料可包括一金屬,如銅、鈦、鎢、鋁或其類似者。接著,移除光阻層及其上未形成導電材料之晶種層之部分。可藉由一可接受灰化或剝離程序(諸如,使用氧電漿或其類似者)來移除光阻層。一旦已移除光阻層,則(諸如)藉由使用一可接受蝕刻程序(諸如,藉由濕式或乾式蝕刻)來移除晶種層之曝露部分。晶種層之剩餘部分及導電材料形成金屬化圖案138及通路。通路經形成於貫穿介電層132而至(例如)貫穿通路112及/或晶粒連接器126之開口中。 在圖9中,介電層140經沈積於金屬化圖案138及介電層132上。在一些實施例中,介電層140由一聚合物形成,該聚合物可為可使用一微影光罩來圖案化之一光敏材料,諸如PBO、聚醯亞胺、BCB或其類似者。在其他實施例中,介電層140由氮化物(諸如氮化矽)、氧化物(諸如氧化矽、PSG、BSG、BPSG)或其類似者形成。可藉由旋塗、層疊、CVD、類似者或其等之一組合來形成介電層140。 接著,在圖10中,圖案化介電層140。圖案化形成開口以曝露金屬化圖案138之部分。圖案化可藉由一可接受程序,諸如:當介電層係一光敏材料時,藉由使介電層140曝光;或藉由使用(例如)一各向異性蝕刻之蝕刻。若介電層140係一光敏材料,則可在曝露之後使介電層140顯影。 在圖11中,具有通路之金屬化圖案146經形成於介電層140上。作為形成金屬化圖案146之一實例,一晶種層(圖中未展示)經形成於介電層140上方及貫穿介電層140之開口中。在一些實施例中,晶種層係一金屬層,其可為一單一層或包括由不同材料形成之複數個子層的一複合層。在一些實施例中,晶種層包括一鈦層及該鈦層上方之一銅層。可使用(例如) PVD或其類似者來形成晶種層。接著,一光阻層經形成且圖案化於晶種層上。光阻層可藉由旋塗或其類似者來形成且可經曝光以圖案化。光阻層之圖案對應於金屬化圖案146。圖案化形成貫穿光阻層以曝露晶種層之開口。一導電材料經形成於光阻層之開口中及晶種層之曝露部分上。可藉由鍍覆(諸如電鍍或無電電鍍或其類似者)來形成導電材料。導電材料可包括一金屬,如銅、鈦、鎢、鋁或其類似者。接著,移除光阻層及其上未形成導電材料之晶種層之部分。可藉由一可接受灰化或剝離程序(諸如,使用氧電漿或其類似者)來移除光阻層。一旦已移除光阻層,則(諸如)藉由使用一可接受蝕刻程序(諸如,藉由濕式或乾式蝕刻)來移除晶種層之曝露部分。晶種層之剩餘部分及導電材料形成金屬化圖案146及通路。通路經形成於貫穿介電層140而至(例如)金屬化圖案138之部分的開口中。 在圖12中,介電層148經沈積於金屬化圖案146及介電層140上。在一些實施例中,介電層148由一聚合物形成,該聚合物可為可使用一微影光罩來圖案化之一光敏材料,諸如PBO、聚醯亞胺、BCB或其類似者。在其他實施例中,介電層148由氮化物(諸如氮化矽)、氧化物(諸如氧化矽、PSG、BSG、BPSG)或其類似者形成。可藉由旋塗、層疊、CVD、類似者或其等之一組合來形成介電層148。 接著,在圖13中,圖案化介電層148。圖案化形成開口以曝露金屬化圖案146之部分。圖案化可藉由一可接受程序,諸如:當介電層係一光敏材料時,藉由使介電層148曝光;或藉由使用(例如)一各向異性蝕刻之蝕刻。若介電層148係一光敏材料,則可在曝露之後使介電層148顯影。 在圖14中,具有通路之金屬化圖案154經形成於介電層148上。作為形成金屬化圖案154之一實例,一晶種層(圖中未展示)經形成於介電層148上方及貫穿介電層148之開口中。在一些實施例中,晶種層係一金屬層,其可為一單一層或包括由不同材料形成之複數個子層的一複合層。在一些實施例中,晶種層包括一鈦層及該鈦層上方之一銅層。可使用(例如) PVD或其類似者來形成晶種層。接著,一光阻層經形成且圖案化於晶種層上。光阻層可藉由旋塗或其類似者來形成且可經曝光以圖案化。光阻層之圖案對應於金屬化圖案154。圖案化形成貫穿光阻層以曝露晶種層之開口。一導電材料經形成於光阻層之開口中及晶種層之曝露部分上。可藉由鍍覆(諸如電鍍或無電電鍍或其類似者)來形成導電材料。導電材料可包括一金屬,如銅、鈦、鎢、鋁或其類似者。接著,移除光阻層及其上未形成導電材料之晶種層之部分。可藉由一可接受灰化或剝離程序(諸如,使用氧電漿或其類似者)來移除光阻層。一旦已移除光阻層,則(諸如)藉由使用一可接受蝕刻程序(諸如,藉由濕式或乾式蝕刻)來移除晶種層之曝露部分。晶種層之剩餘部分及導電材料形成金屬化圖案154及通路。通路經形成於貫穿介電層148而至(例如)金屬化圖案146之部分的開口中。 在圖15中,介電層156經沈積於金屬化圖案154及介電層148上。在一些實施例中,介電層156由一聚合物形成,該聚合物可為可使用一微影光罩來圖案化之一光敏材料,諸如PBO、聚醯亞胺、BCB或其類似者。在其他實施例中,介電層156由氮化物(諸如氮化矽)、氧化物(諸如氧化矽、PSG、BSG、BPSG)或其類似者形成。可藉由旋塗、層疊、CVD、類似者或其等之一組合來形成介電層156。 接著,在圖16中,圖案化介電層156。圖案化形成開口以曝露金屬化圖案154之部分。圖案化可藉由一可接受程序,諸如:當介電層係一光敏材料時,藉由使介電層156曝光;或藉由使用(例如)一各向異性蝕刻之蝕刻。若介電層156係一光敏材料,則可在曝露之後使介電層156顯影。 前側重佈結構160係一實例展示。更多或更少介電層及金屬化圖案可經形成於前側重佈結構160中。若要形成更少介電層及金屬化圖案,則可省略上文所討論之步驟及程序。若要形成更多介電層及金屬化圖案,則可重複上文所討論之步驟及程序。一般技術者將輕易瞭解,將省略或重複何種步驟及程序。 在圖17中,襯墊162經形成於前側重佈結構160之一外側上。襯墊162用於耦合至導電連接器166 (參閱圖21)且可指稱凸塊下金屬(UBM) 162。在所繪示實施例中,形成貫穿開口(其貫穿介電層156而至金屬化圖案154)之襯墊162。作為形成襯墊162之一實例,一晶種層(圖中未展示)經形成於介電層156上方。在一些實施例中,晶種層係一金屬層,其可為一單一層或包括由不同材料形成之複數個子層的一複合層。在一些實施例中,晶種層包括一鈦層及該鈦層上方之一銅層。可使用(例如) PVD或其類似者來形成晶種層。接著,一光阻層經形成且圖案化於晶種層上。光阻層可藉由旋塗或其類似者來形成且可經曝光以圖案化。光阻層之圖案對應於襯墊162。圖案化形成貫穿光阻層以曝露晶種層之開口。一導電材料經形成於光阻層之開口中及晶種層之曝露部分上。可藉由鍍覆(諸如電鍍或無電電鍍或其類似者)來形成導電材料。導電材料可包括一金屬,如銅、鈦、鎢、鋁或其類似者。接著,移除光阻層及其上未形成導電材料之晶種層之部分。可藉由一可接受灰化或剝離程序(諸如,使用氧電漿或其類似者)來移除光阻層。一旦已移除光阻層,則(諸如)藉由使用一可接受蝕刻程序(諸如,藉由濕式或乾式蝕刻)來移除晶種層之曝露部分。晶種層之剩餘部分及導電材料形成襯墊162。在其中依不同方式形成襯墊162之實施例中,可利用更多光阻層及圖案化步驟。 在圖18中,導電連接器166經形成於UBM 162上。導電連接器166可為BGA連接器、焊球、金屬柱、受控倒疊晶片連接(C4)凸塊、微凸塊、無電鍍鎳-無電鍍鈀-浸金技術(ENEPIG)形成凸塊或其類似者。導電連接器166可包含一導電材料,諸如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似者或其等之一組合。在一些實施例中,藉由首先透過常用方法(諸如蒸鍍、電鍍、印刷、銲料轉移、植球或其類似者)形成一焊料層來形成導電連接器166。一旦一焊料層已形成於結構上,則可執行一回焊以將材料塑形成所要凸塊形狀。在另一實施例中,導電連接器166係藉由濺鍍、印刷、電鍍、無電電鍍、CVD或其類似者所形成之金屬柱(諸如一銅柱)。金屬柱可不含焊料且具有實質上垂直側壁。在一些實施例中,一金屬罩蓋層(圖中未展示)經形成於金屬柱連接器166之頂部上。金屬罩蓋層可包含鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、類似者或其等之一組合且可藉由一鍍覆程序來形成。 在圖19中,執行一載體基板脫離以自後側重佈結構(例如介電層104)拆離(脫離)載體基板100。根據一些實施例,脫離包含:將一光(諸如一雷射光或一UV光)投射至離型層102上,使得離型層102在光之加熱下分解且可移除載體基板100。接著,翻轉結構且將其放置於一膠帶190上。 如圖19中所進一步繪示,形成貫穿介電層104之開口以曝露金屬化圖案106之部分。可(例如)使用雷射鑽孔、蝕刻或其類似者來形成開口。 在圖20中,藉由沿(例如)相鄰區域600與602之間的切割道區域鋸切184來執行一單粒化程序。鋸切184將第一封裝區域600與第二封裝區域602分割。 圖20繪示一所得單粒化封裝200,其可來自第一封裝區域600或第二封裝區域602之一者。封裝200亦可指稱一整合式扇出(InFO)封裝200。 圖21A繪示包含封裝200 (可指稱一第一封裝200)及一第二封裝300之一封裝結構500。第二封裝300包含一基板302及經耦合至基板302之一或多個堆疊晶粒308 (308A及308B)。雖然圖中繪示晶粒308 (308A及308B)之一單一堆疊,但在其他實施例中,可將複數個堆疊晶粒308 (各具有一或多個堆疊晶粒)安置成並排耦合至基板302之一相同表面(例如,參閱圖21B)。返回參考圖21A,基板302可由一半導體材料(諸如矽、鍺、金剛石或其類似者)製成。在一些實施例中,亦可使用化合物材料,諸如矽鍺、碳化矽、鎵砷、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、此等之組合及其類似者。另外,基板302可為一絕緣體上覆矽(SOI)基板。一般而言,一SOI基板包含一半導體材料層,諸如磊晶矽、鍺、矽鍺、SOI、絕緣體上覆矽鍺(SGOI)或其等之組合。在一替代實施例中,基板302係基於諸如玻璃纖維增強樹脂核心之一絕緣核心。一實例性核心材料係諸如FR4之玻璃纖維樹脂。核心材料之替代物包含雙馬來醯亞胺三嗪(BT)樹脂或替代地,其他印刷電路板(PCB)材料或膜。諸如味素堆積層(ABF)或其他層疊物之堆積膜可用於基板302。 基板302可包含主動裝置及被動裝置(圖21中未展示)。一般技術者將認識到,諸如電晶體、電容器、電阻器、此等之組合及其類似者之各種裝置可用於產生半導體封裝300之設計之結構及功能要求。可使用任何適合方法來形成裝置。 基板302亦可包含金屬化層(圖中未展示)及貫穿通路306。金屬化層可經形成於主動裝置及被動裝置上方且經設計以連接各種裝置而形成功能電路。金屬化層可由介電材料(例如低介電係數材料)及導電材料(例如銅)之交替層及使導電材料層互連之通路形成且可透過任何適合程序(諸如沈積、鑲嵌、雙鑲嵌或其類似者)來形成。在一些實施例中,基板302實質上不含主動裝置及被動裝置。 基板302可在基板302之一第一側上具有耦合至堆疊晶粒308之接合襯墊303且在基板302之一第二側上具有耦合至功能連接器314之接合襯墊304,第二側與基板302之第一側對置。在一些實施例中,藉由使凹口(圖中未展示)形成至基板302之第一側及第二側上之介電層(圖中未展示)中來形成接合襯墊303及304。凹口可經形成以允許接合襯墊303及304嵌入至介電層中。在其他實施例中,省略凹口,此係因為接合襯墊303及304可經形成於介電層上。在一些實施例中,接合襯墊303及304包含由銅、鈦、鎳、金、鈀、類似者或其等之一組合製成的一薄晶種層(圖中未展示)。接合襯墊303及304之導電材料可經沈積於薄晶種層上方。可藉由一電化學電鍍程序、一無電電鍍程序、CVD、ALD、PVD、類似者或其等之一組合來形成導電材料。在一實施例中,接合襯墊303及304之導電材料係銅、鎢、鋁、銀、金、類似者或其等之一組合。 在一實施例中,接合襯墊303及304係包含三個導電材料層(諸如一鈦層、一銅層及一鎳層)之UBM。然而,一般技術者將認識到,存在適合於形成UBM 303及304之材料及層之諸多適合配置,諸如鉻/鉻銅合金/銅/金之一配置、鈦/鈦鎢/銅之一配置或銅/鎳/金之一配置。可用於UBM 303及304之任何適合材料或材料層完全意欲包含於本申請案之範疇內。在一些實施例中,貫穿通路306延伸貫穿基板302且將至少一接合襯墊303耦合至至少一接合襯墊304。 在所繪示實施例中,堆疊晶粒308藉由接線310耦合至基板302,但可使用諸如導電凸塊之其他連接。在一實施例中,堆疊晶粒308係堆疊記憶體晶粒。例如,堆疊記憶體晶粒308可包含低功率(LP)雙倍資料速率(DDR)記憶體模組,諸如LPDDR1、LPDDR2、LPDDR3、LPDDR4或類似記憶體模組。 在一些實施例中,可由一模製材料312囊封堆疊晶粒308及接線310。可(例如)使用壓縮模製來將模製材料312模製於堆疊晶粒308及接線310上。在一些實施例中,模製材料312係一模製化合物、一聚合物、一環氧樹脂、氧化矽填充材料、類似者或其等之一組合。可執行一固化步驟以固化模製材料312,其中固化可為一熱固化、一UV固化、類似者或其等之一組合。 在一些實施例中,堆疊晶粒308及接線310經內埋於模製材料312中,且在固化模製材料312之後,執行一平坦化步驟(諸如一研磨)以移除模製材料312之過量部分且提供第二封裝300之一實質上平坦表面。 在形成第二封裝300之後,藉由功能連接器314、接合襯墊304及金屬化圖案106將封裝300機械及電接合至第一封裝200。在一些實施例中,可透過接線310、接合襯墊303及304、貫穿通路306、功能連接器314及貫穿通路112將堆疊記憶體晶粒308耦合至積體電路晶粒114。 功能連接器314可類似於上文所描述之導電連接器166且本文中不再重複描述,但功能連接器314及導電連接器166無需相同。功能連接器314可經安置於與堆疊記憶體晶粒308對置之基板302之一側上。在一些實施例中,一阻焊層318亦可形成於與堆疊記憶體晶粒308對置之基板302之側上。功能連接器314可經安置於阻焊層318之開口中以電及機械耦合至基板302中之導電構件(例如接合襯墊304)。阻焊層318可用於保護基板302之區域免受外部損害。 在一些實施例中,在接合功能連接器314之前,功能連接器314經塗覆有一助焊劑(圖中未展示),諸如一免清洗助焊劑。功能連接器314可經浸漬於助焊劑中或助焊劑可經噴射至功能連接器314上。在另一實施例中,助焊劑可經施加於金屬化圖案106之表面。 在一些實施例中,在使用將第二封裝300附著至第一封裝200之後剩餘之環氧樹脂助焊劑之至少一些環氧樹脂部分回焊功能連接器314之前,功能連接器314可具有形成於其上之一選用環氧樹脂助焊劑(圖中未展示)。此剩餘環氧樹脂部分可充當一底膠以減小應力且保護由回焊功能連接器314所致之接頭。 第二封裝300與第一封裝200之間的接合可為一焊料接合。在一實施例中,第二封裝300藉由一回焊程序接合至第一封裝200。在此回焊程序期間,功能連接器314與接合襯墊304及金屬化圖案106接觸以將第二封裝300實體及電耦合至第一封裝200。在接合程序之後,一金屬間化合物(IMC,圖中未展示)可形成於金屬化圖案106與功能連接器314之界面處且亦形成於功能連接器314與接合襯墊304之間的界面處(圖中未展示)。 第二封裝300可進一步包含經安置於相同於功能連接器314之基板302之一表面上的虛設連接器316。例如,虛設連接器316可經安置於與堆疊記憶體晶粒308對置之基板302之一表面上,且虛設連接器可經安置於阻焊層318之開口320中。虛設連接器316可實質上類似於功能連接器314及導電連接器166。例如,虛設連接器316及功能連接器314可具有一相同材料組合物,但在其他實施例中,虛設連接器316及功能連接器314可包括不同材料。 在一些實施例中,虛設連接器316可為焊球(例如圖21A及圖21B所繪示)、安置於一導電柱上之焊料區域或實質上不含焊料之導電柱(例如,參閱將虛設連接器316繪示為導電柱402之圖30)。在其中虛設連接器316係由導電柱402製成之實施例中,導電柱402可包括任何適合材料,諸如銅、金、鎳或其類似者。例如,導電柱402可由實質上純銅、實質上純金、實質上純鎳或其類似者製成。在其他實施例中,導電柱402可包括不同物質之一合金。此外,在其中虛設連接器316係由導電柱402製成之實施例中,導電柱402可具有任何適合形狀,諸如一圓柱(參閱圖31A)、在一端(例如遠離基板302之一端)上具有一截頭圓錐之一圓柱(參閱圖31B)、一橢圓柱(例如,參閱圖31C)或任何其他適合形狀。 在各種實施例中,虛設連接器316不被用於將第二封裝300機械或電接合至第一封裝200。例如,虛設連接器316可不實體接觸或完全橋接第二封裝300與第一封裝200之間的一距離。在一些實施例中,一間隙經安置於虛設連接器316與第一封裝200之間,且虛設連接器316與第一封裝200之間的一距離D1可為約10 μm或更小。在其他實施例中,虛設連接器316之部分或全部可實體接觸第一封裝200。虛設連接器316可與第一封裝200中之功能電路(例如積體電路晶粒114)電隔離,且虛設連接器316可或可不與第二封裝300中之功能電路(例如堆疊記憶體晶粒308及/或基板302中之電組件)電隔離。 如圖21A中所繪示,功能連接器314經安置於基板302之一周邊區域處(例如,圍繞一外邊緣),而虛設連接器316經安置於基板302之一中央區域中。圖22中所展示之第二封裝300之俯視圖中另外詳細展示此組態。在圖22中,功能連接器314由虛線314A及314B框定,而虛設連接器316由虛線316A框定。功能連接器314可經安置成一M×N陣列,其中「M」指定鄰近於第二封裝300之一外邊緣的功能連接器314之全部行之數目且「N」指定鄰近於第二封裝300之一外邊緣的功能連接器314之全部列之數目。「M」及「N」可為任何正整數。例如,圖23A至圖23D繪示功能連接器314之不同組態之俯視圖。為簡單起見,圖23A至圖23D中省略虛設連接器316。圖23A繪示呈一1×1陣列組態之功能連接器314,圖23B繪示呈一1×2陣列組態之功能連接器314,圖23C繪示呈一1×3陣列組態之功能連接器314,及圖23D繪示呈一2×3陣列組態之功能連接器314。圖23A至圖23D中之組態僅為例示且功能連接器314之其他組態(例如,具有不同數目個行及/或列)係可行的。 返回參考圖22,在一俯視圖中,功能連接器314可環繞虛設連接器316。虛設連接器316可經配置為任何適合組態。例如,圖24A至圖24I繪示虛設連接器316之一些實例性組態。類似於圖22,在圖24A至圖24I中,功能連接器314由虛線314A及314B框定,而虛設連接器316由虛線316A框定。雖然圖24A至圖24I繪示與功能連接器314之一1×3陣列組態組合之虛設連接器316,但應瞭解,虛設連接器316可與功能連接器314之任何組態(例如具有不同數目個行及/或列之一陣列)組合。 在一些實施例中,虛設連接器316可經安置成包括複數個列及行之一陣列。例如,虛設連接器316可經安置成一R×S陣列,其中「R」係陣列中虛設連接器316之行數且「S」係陣列中虛設連接器316之列數。在各種實施例中,「R」及「S」可為任何正整數,且R可大於S (例如圖24A中所繪示)、等於S (未明確繪示)或小於S (例如由圖24B所繪示)。 在一些實施例中,功能連接器314可環繞虛設連接器316之複數個陣列。例如由圖24C及圖24D所繪示,功能連接器314可環繞虛設連接器316之兩個陣列。虛設連接器316之各陣列可包含R×S個虛設連接器316,且R可大於S (例如由圖24C所繪示)、等於S (未明確繪示)或小於S (例如由圖24D所繪示)。如由圖24C及圖24D所繪示,兩個不同陣列中之兩個最靠近虛設連接器316之間的距離D2可大於一相同陣列中之相鄰虛設連接器316之間的一間距。 在一些實施例中,虛設連接器316可經安置成一圖案(例如一陣列),在一俯視圖(例如圖22中所繪示)中,該圖案相對於第二封裝300之一外周邊居中。在其他實施例中,虛設連接器316可經安置成一圖案(例如一陣列),在一俯視圖(參閱圖24E)中,該圖案自第二封裝300之一中心偏移。在此等實施例中,當虛設連接器316之圖案未居中時,不同數目個功能連接器314可經安置於虛設連接器316之圖案之對置側上。例如圖24E中所繪示,與虛設連接器316之陣列之右側相比,更大數目個功能連接器314經安置於虛設連接器316之陣列之左側上。在其他實施例中,相等數目個功能連接器314可經安置於虛設連接器316之對置側上。 如圖22及圖24A至圖24E中所描述,虛設連接器316經安置成一陣列之行及列。在其他實施例中,虛設連接器316可經安置成一不同圖案。例如,虛設連接器316可經安置成一同心環圖案,其中虛設連接器316之一外環環繞虛設連接器316之一或多個內環(例如,參閱圖24F)。作為另一實例,虛設連接器316可經安置成一X圖案(例如,參閱圖24G)。作為又一實例,虛設連接器316可經安置成一隨機分佈(例如,參閱圖24H)。虛設連接器316之其他圖案亦係可行的。 此外,在一些實施例中,虛設連接器316之相鄰者之間的一間距可相同於功能連接器314之相鄰者之間的一間距(參閱圖22)。在其他實施例中,虛設連接器316之相鄰者之間的一間距可不同於功能連接器314之相鄰者之間的一間距。例如,虛設連接器316之相鄰者之間的間距可為功能連接器314之相鄰者之間的間距的一倍數。圖24I繪示其中虛設連接器316之相鄰者之間的一間距係功能連接器314之相鄰者之間的一間距的兩倍的一實例性實施例。本文中所討論之實例性間距可與虛設連接器316之任何圖案組合使用(例如上文相對於圖22及圖24A至圖24H所描述)。 圖25繪示一虛設連接器316及一功能連接器314 (其等可經安置成上文所描述之任何組態)之一俯視圖。虛設連接器316之一直徑經指定為D3,且功能連接器314之一直徑經指定為D4。在一些實施例中,虛設連接器316之直徑D3可小於或等於功能連接器314之直徑D4。例如,在其中功能連接器314之直徑D4係約210 µm之一實施例中,虛設連接器316之直徑D3可為約210 µm或更小。此外,功能連接器314及虛設連接器316可各安置於延伸貫穿阻焊層318之一阻焊層開口(SRO)中。在圖25中,功能連接器314下方之SRO 320A之一輪廓及虛設連接器316下方之SRO 320B之一輪廓經展示為重影。虛設連接器316下方之SRO 320B之一直徑經指定為D5,且功能連接器314下方之SRO 320A之一直徑經指定為D6。在一些實施例中,虛設連接器316下方之SRO 320B之直徑D5可大於或等於功能連接器314下方之SRO 320A之直徑D6。例如,在其中功能連接器314下方之SRO 320A之直徑D6係約190 µm之一實施例中,虛設連接器316下方之SRO 320B之直徑D5可為約190 µm或更大。亦可考量功能連接器314、虛設連接器316、SRO 320A及/或SRO 320B之其他直徑。 接著參考圖26,一底膠322可經形成於第二封裝300與第一封裝200之間且包圍功能連接器314及虛設連接器316。在一些實施例中,底膠322可沿第二封裝300之側壁(例如,沿基板302及模製材料312之側壁)進一步延伸。底膠322可在附著第二封裝300之後藉由一毛細管流動程序來形成或可在附著第二封裝300之前藉由一適合沈積方法來形成。在各種實施例中,底膠322可在虛設連接器316下方流動且可跨越虛設連接器316與第一封裝200之間的一距離。例如,底膠322可沿垂直於基板302之一主表面的一線安置於虛設連接器316與第一封裝200之間。 歸因於製程之缺陷,會在第二封裝300中發生翹曲。例如,在一橫截面圖(未明確繪示)中,第二封裝300可具有一「笑臉」或「哭臉」輪廓。在一實施例笑臉輪廓(未明確繪示)中,第二封裝300之周邊區域可經安置成比第二封裝300之中央區域更遠離第一封裝200。在一實施例哭臉輪廓(未明確繪示)中,第二封裝300之周邊區域可經安置成比第二封裝300之中央區域更接近於第一封裝200。經觀察,此翹曲特性可導致施配期間底膠322之一非所要波前(有時指稱一前緣),此可導致非所要空隙受困於第一封裝200與第二封裝300之間的底膠322中。此等空隙可進一步引起製造缺陷,諸如可靠性測試及負面影響之後的爆米花效應(其中第一封裝200及第二封裝300遠離彼此彎曲)。 在各種實施例中,可包含虛設連接器316以控制施配期間底膠322之波前之一輪廓。經觀察,若在相同於功能連接器314之第二封裝300之一表面上包含虛設連接器316,則可改良第二封裝300之哭臉輪廓及笑臉輪廓兩者之底膠施配波前。 例如,圖27A至圖27C繪示其中第二封裝300 (參閱圖26)具有一笑臉輪廓之實施例封裝中之底膠施配之模擬資料。為模擬一笑臉輪廓,將-50 µm設定為封裝之一中心處之第一封裝200與第二封裝300之間的一距離減去封裝之一邊緣處之第一封裝200與第二封裝300之間的一距離的一值。圖27A至圖27C繪示第二封裝300及第二封裝300下方之底膠322之流動的俯視圖。圖27A繪示虛設連接器316不包含於第二封裝300中時之底膠322之波前500A。圖27B及圖27C分別繪示虛設連接器316包含於第二封裝300中時之底膠322之波前500B及500C。圖27B繪示其中底膠322之一材料依一15°角接觸功能連接器314之一實施例,及圖27C繪示其中底膠322之一材料依一60°角接觸功能連接器314之一實施例。參考圖27A,波前500A之一中心502與波前500A之一邊緣504之間的一距離相對較大。在一笑臉輪廓翹曲封裝中,波前500A中之此相對較大距離可引起空隙506/508形成。經觀察,若包含虛設連接器316,則與不含虛設連接器316之封裝相比,波前500B/500C之各自中心502與波前500B/500C之各自邊緣504之間的一距離可減小。例如,與波前500A相比,波前500B及500C中之中心502與邊緣504之間的一距離可減小約50%。經進一步觀察,可藉由減小一笑臉輪廓翹曲封裝中之此距離(即,點502與點504之間的距離)來有利地減小底膠322中之空隙之大小及/或數量。 作為另一實例,圖28A至圖28C繪示其中第二封裝300 (參閱圖26)具有一哭臉輪廓之實施例封裝中之底膠施配之模擬資料。為模擬一哭臉輪廓,將20 µm設定為封裝之一中心處之第一封裝200與第二封裝300之間的一距離減去封裝之一邊緣處之第一封裝200與第二封裝300之間的一距離的一值。圖28A至圖28C繪示第二封裝300及第二封裝300下方之底膠322之流動的俯視圖。圖28A繪示虛設連接器316不包含於第二封裝300中時之底膠322之波前600A。圖28B及圖28C分別繪示虛設連接器316包含於第二封裝300中時之底膠322之波前600B及600C。圖28B繪示其中底膠322之一材料依一15°角接觸功能連接器314之一實施例,及圖28C繪示其中底膠322之一材料依一60°角接觸功能連接器314之一實施例。參考圖28A,波前600A之一中心602與波前600A之一邊緣604之間的一距離相對較小。在一哭臉輪廓翹曲封裝中,波前600A中之此相對較小距離可引起一或多個空隙606形成。經觀察,若包含虛設連接器316,則與不含虛設連接器316之封裝相比,波前600B/600C之各自中心602與波前600B/600C之各自邊緣604之間的一距離可增大。例如,與波前600A相比,波前600B及600C中之中心602與邊緣604之間的一距離可增大約230%、約500%或更大。經進一步觀察,可藉由增大一哭臉輪廓翹曲封裝中之此距離(即,點602與點604之間的距離)來有利地減小底膠322中之空隙之大小及/或數量。 圖29繪示將封裝200及300安裝至一基板400之後的半導體封裝500。基板400可指稱一封裝基板400。使用導電連接器166將封裝200安裝至封裝基板400。 封裝基板400可由一半導體材料(諸如矽、鍺、金剛石或其類似者)製成。替代地,亦可使用化合物材料,諸如矽鍺、碳化矽、鎵砷、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、此等之組合及其類似者。另外,封裝基板400可為一SOI基板。一般而言,一SOI基板包含一半導體材料層,諸如磊晶矽、鍺、矽鍺、SOI、SGOI或其等之組合。在一替代實施例中,封裝基板400係基於一絕緣核心,諸如玻璃纖維增強樹脂核心。一實例性核心材料係諸如FR4之玻璃纖維樹脂。核心材料之替代物包含雙馬來醯亞胺三嗪(BT)樹脂或替代地,其他PCB材料或膜。諸如ABF或其他層疊物之堆積膜可用於封裝基板400。 封裝基板400可包含主動裝置及被動裝置(圖29中未展示)。一般技術者將認識到,諸如電晶體、電容器、電阻器、此等之組合及其類似者之各種裝置可用於產生半導體封裝500之設計之結構及功能要求。可使用任何適合方法來形成裝置。 封裝基板400亦可包含金屬化層及通路(圖中未展示)及金屬化層及通路上方之接合襯墊402。金屬化層可經形成於主動裝置及被動裝置上方且經設計以連接各種裝置而形成功能電路。金屬化層可由介電材料(例如低介電係數材料)及導電材料(例如銅)之交替層及使導電材料層互連之通路形成且可透過任何適合程序(諸如沈積、鑲嵌、雙鑲嵌或其類似者)來形成。在一些實施例中,封裝基板400實質上不含主動裝置及被動裝置。 在一些實施例中,導電連接器166可經回焊以將封裝200附著至接合襯墊402。導電連接器166將基板400 (其包含基板400中之金屬化層)電及/或實體耦合至第一封裝200。在一些實施例中,被動裝置(例如表面安裝裝置(SMD),圖中未繪示)可在安裝於基板400上之前附著至封裝200 (例如,接合至接合襯墊402)。在此等實施例中,被動裝置可經接合至相同於導電連接器166之封裝200之一表面。 在使用將封裝200附著至基板400之後剩餘之環氧樹脂助焊劑之至少一些環氧樹脂部分來回焊導電連接器166之前,導電連接器166可具有形成於其上之一環氧樹脂助焊劑(圖中未展示)。此剩餘環氧樹脂部分可充當一底膠以減小應力且保護由回焊導電連接器166所致之接頭。在一些實施例中,一底膠(圖中未展示)可經形成於第一封裝200與基板400之間且包圍導電連接器166。底膠可在附著封裝200之後藉由一毛細管流動程序來形成或可在附著封裝200之前藉由一適合沈積方法來形成。 亦可包含其他構件及程序。例如,可包含測試結構來輔助3D封裝或3DIC裝置之驗證測試。測試結構可包含(例如)經形成於一重佈層中或一基板上之測試襯墊,其允許測試3D封裝或3DIC,使用探針及/或探針卡,等等。可對中間結構及最終結構執行驗證測試。另外,本文中所揭露之結構及方法可與併入已知良好晶粒之中間驗證的測試方法結合使用以提高良率且降低成本。 本揭露中之裝置及方法之實施例具有諸多優點。特定而言,虛設連接器經安置於一PoP結構之一第一封裝與一第二封裝之間。該等虛設連接器可經安置於相同於功能連接器之該第二封裝之一表面上,該等功能連接器電及機械接合該第一封裝及該第二封裝。在一些實施例中,該等虛設連接器可與該第一封裝實體及/或電斷接。該等虛設連接器可用於改良經施配於該第一封裝與該第二封裝之間的一底膠之一波前之一輪廓。藉由改良該底膠之該波前輪廓,該底膠可困住較少及/或較小空隙,藉此改良可靠性且減少封裝可靠性測試前及封裝可靠性測試後之缺陷(例如爆米花效應)。 根據一實施例,一種封裝包含一第一封裝。該第一封裝包含:一第一積體電路晶粒;一囊封劑,其圍繞該第一積體電路晶粒;及重佈層,其等位於該囊封劑及該第一積體電路晶粒上方。該封裝亦包含一第二封裝,其藉由複數個功能連接器接合至該第一封裝。該等功能連接器及該等重佈層將該第二封裝之一第二積體電路晶粒電連接至該第一積體電路晶粒。該封裝亦包含複數個虛設連接器,其等經安置於該第一封裝與該第二封裝之間。面向該第一封裝之該複數個虛設連接器之各者之一端與該第一封裝實體分離。 根據一實施例,一種封裝包含一第一封裝組件,其具有:一第一半導體晶粒,其經囊封於一囊封劑中;一導電通路,其延伸貫穿該囊封劑;及一重佈層,其經電連接至該第一半導體晶粒及該導電通路。該封裝進一步包含一第二封裝組件,其藉由經安置於該第二封裝組件之一底面上的第一複數個連接器來實體接合至該第一封裝組件。該封裝進一步包含經安置於該第二封裝組件之該底面上的第二複數個連接器,其中該第二複數個連接器與該第一半導體晶粒電隔離;且其中該第一複數個連接器及該第二複數個連接器具有不同大小。 根據一實施例,一種方法包含:將一第一積體電路晶粒囊封於一囊封劑中;形成經電連接至該第一積體電路晶粒之一重佈層(RDL);及使用複數個功能連接器將一基板接合至該RDL。該複數個功能連接器將一第二積體電路晶粒電連接至該第一積體電路晶粒,且該第一積體電路晶粒及該第二積體電路晶粒經安置於該基板之對置側上。該方法進一步包含:將複數個虛設連接器安置於該基板與該RDL之間。該複數個功能連接器在該複數個虛設連接器下方延伸,且在一俯視圖中,該複數個功能連接器至少部分環繞該複數個虛設連接器。該方法進一步包含:將一底膠施配於該基板與該RDL之間。 上文已概述若干實施例之特徵,使得熟習技術者可較佳理解本揭露之態樣。熟習技術者應瞭解,其可容易地將本揭露用作用於設計或修改其他程序及結構的一基礎以實施相同目的及/或達成本文中所引入之實施例之相同優點。熟習技術者亦應意識到,此等等效構造不應背離本揭露之精神及範疇,且其可在不背離本揭露之精神及範疇之情況下對本文作出各種改變、置換及變更。
100‧‧‧載體基板
102‧‧‧離型層
104‧‧‧介電層
106‧‧‧金屬化圖案/重佈層(RDL)/重佈線
108‧‧‧介電層
110‧‧‧後側重佈結構
112‧‧‧貫穿通路
114‧‧‧積體電路晶粒
116‧‧‧黏著劑
118‧‧‧半導體基板
120‧‧‧互連結構
122‧‧‧襯墊
124‧‧‧鈍化膜
126‧‧‧晶粒連接器
128‧‧‧介電材料
130‧‧‧囊封劑
132‧‧‧介電層
138‧‧‧金屬化圖案/RDL/重佈線
140‧‧‧介電層
146‧‧‧金屬化圖案/RDL/重佈線
148‧‧‧介電層
154‧‧‧金屬化圖案/RDL/重佈線
156‧‧‧介電層
160‧‧‧前端重佈結構
162‧‧‧襯墊/凸塊下金屬(UBM)
166‧‧‧導電連接器
184‧‧‧鋸切
190‧‧‧膠帶
200‧‧‧第一封裝
300‧‧‧第二封裝
302‧‧‧基板
303‧‧‧接合襯墊/UBM
304‧‧‧接合襯墊/UBM
306‧‧‧貫穿通路
308‧‧‧堆疊晶粒
308A‧‧‧晶粒
308B‧‧‧晶粒
310‧‧‧接線
312‧‧‧模製材料
314‧‧‧功能連接器
314A‧‧‧虛線
314B‧‧‧虛線
316‧‧‧虛設連接器
316A‧‧‧虛線
318‧‧‧阻焊層
320‧‧‧開口
320A‧‧‧阻焊層開口(SRO)
320B‧‧‧SRO
322‧‧‧底膠
400‧‧‧基板
402‧‧‧導電柱/接合襯墊
500‧‧‧封裝結構/半導體封裝
500A‧‧‧波前
500B‧‧‧波前
500C‧‧‧波前
502‧‧‧中心
504‧‧‧邊緣
506‧‧‧空隙
508‧‧‧空隙
600‧‧‧第一封裝區域
600A‧‧‧波前
600B‧‧‧波前
600C‧‧‧波前
602‧‧‧第二封裝區域/中心
604‧‧‧邊緣
606‧‧‧空隙
D1‧‧‧距離
D2‧‧‧距離
D3‧‧‧直徑
D4‧‧‧直徑
D5‧‧‧直徑
D6‧‧‧直徑
自結合附圖閱讀之以下詳細描述最佳理解本揭露之態樣。應注意,根據工業標準慣例,各種構件未按比例繪製。實際上,為使討論清楚,可任意增大或減小各種構件之尺寸。 圖1、圖2、圖3、圖4、圖5、圖6、圖7、圖8、圖9、圖10、圖11、圖12、圖13、圖14、圖15、圖16、圖17、圖18、圖19、圖20、圖21A及圖21B繪示根據一些實施例之用於形成一第一封裝結構及將其他封裝結構附著至該第一封裝之一程序期間之中間步驟之橫截面圖。 圖22、圖23A、圖23B、圖23C、圖23D、圖24A、圖24B、圖24C、圖24D、圖24E、圖24F、圖24G、圖24H、圖24I及圖25繪示根據一些實施例之連接器組態之俯視圖。 圖26繪示根據一些實施例之用於施配一底膠之一程序期間之一中間步驟之一橫截面圖。 圖27A、圖27B、圖27C、圖28A、圖28B及圖28C繪示根據一些實施例之模擬測試期間之底膠波前之俯視圖。 圖29繪示根據一些實施例之用於將其他封裝結構附著至第一封裝之一程序期間之一中間步驟之一橫截面圖。 圖30繪示根據一些實施例之半導體封裝之一橫截面圖。 圖31A、圖31B及圖31C繪示根據一些實施例之虛設連接器之透視圖。
Claims (20)
- 一種封裝,其包括: 一第一封裝,其包括: 一第一積體電路晶粒; 一囊封劑,其圍繞該第一積體電路晶粒;及 一重佈層,其位於該囊封劑及該第一積體電路晶粒上方; 一第二封裝,其藉由複數個功能連接器接合至該第一封裝,其中該等功能連接器及該重佈層將該第二封裝之一第二積體電路晶粒電連接至該第一積體電路晶粒;及 複數個虛設連接器,其等經安置於該第一封裝與該第二封裝之間,其中面向該第一封裝之該複數個虛設連接器之各者之一端與該第一封裝實體分離。
- 如請求項1之封裝,其進一步包括介於該第一封裝與該第二封裝之間的一底膠,其中該底膠經安置成圍繞該複數個功能連接器及該複數個虛設連接器,且其中該底膠經安置於該複數個虛設連接器之各者之底部與該第一封裝之間。
- 如請求項1之封裝,其中在一俯視圖中,該複數個功能連接器環繞該複數個虛設連接器。
- 如請求項1之封裝,其中該複數個虛設連接器之一者之一直徑小於或等於該複數個功能連接器之一者之一直徑。
- 如請求項1之封裝,其中該第二封裝進一步包括一阻焊層,其中該複數個功能連接器經安置於延伸貫穿該阻焊層之數個第一開口中,且其中該複數個虛設連接器經安置於延伸貫穿該阻焊層之數個第二開口中。
- 如請求項5之封裝,其中該等第二開口之各者之一直徑大於或等於該等第一開口之各者之一直徑。
- 如請求項1之封裝,其中在一俯視圖中,該複數個虛設連接器經安置成一圖案,其中該圖案包含虛設連接器之一陣列、虛設連接器之同心圓、虛設連接器之一x形狀或虛設連接器之一隨機分佈。
- 如請求項1之封裝,其中該複數個虛設連接器之相鄰者之間的一間距等於或大於該複數個功能連接器之相鄰者之間的一間距。
- 如請求項1之封裝,其中該複數個虛設連接器之各者係由一焊球、經安置於一導電柱上之一焊料區域或實質上不含任何焊料之一導電柱製成。
- 一種封裝,其包括: 一第一封裝組件,其包括: 一第一半導體晶粒,其經囊封於一囊封劑中; 一導電通路,其延伸貫穿該囊封劑;及 一重佈層,其經電連接至該第一半導體晶粒及該導電通路; 一第二封裝組件,其藉由經安置於該第二封裝組件之一底面上的第一複數個連接器來實體接合至該第一封裝組件; 第二複數個連接器,其等經安置於該第二封裝組件之該底面上,其中該第二複數個連接器與該第一半導體晶粒電隔離;且其中該第一複數個連接器及該第二複數個連接器具有不同大小。
- 如請求項10之封裝,其進一步包括圍繞該第一複數個連接器及該第二複數個連接器之一底膠,其中該底膠沿垂直於該第二封裝組件之該底面的一線安置於該第二複數個連接器之至少一者與該第一封裝組件之間。
- 如請求項10之封裝,其中該第一複數個連接器之至少一者之一高度大於該第二複數個連接器之至少一者之一高度。
- 如請求項10之封裝,其中在一俯視圖中,該第一複數個連接器包圍該第二複數個連接器。
- 如請求項10之封裝,其中該第二複數個連接器之至少一者接觸該第一封裝組件之一介電層。
- 一種方法,其包括: 將一第一積體電路晶粒囊封於一囊封劑中; 形成經電連接至該第一積體電路晶粒之一重佈層(RDL); 使用複數個功能連接器將一基板接合至該RDL,其中該複數個功能連接器將一第二積體電路晶粒電連接至該第一積體電路晶粒,且其中該第一積體電路晶粒及該第二積體電路晶粒經安置於該基板之對置側上; 將複數個虛設連接器安置於該基板與該RDL之間,其中該複數個功能連接器在該複數個虛設連接器下方延伸,且其中在一俯視圖中,該複數個功能連接器至少部分環繞該複數個虛設連接器;及 將一底膠施配於該基板與該RDL之間。
- 如請求項15之方法,其進一步包括:將一封裝基板安裝至與該RDL對置之該第一積體電路晶粒之一側上。
- 如請求項15之方法,其中該底膠沿垂直於該基板之一主表面的一線延伸於該RDL與該複數個虛設連接器之間。
- 如請求項15之方法,其中在一俯視圖中,該複數個虛設連接器經安置成一圖案,其中該圖案包含虛設連接器之一陣列、虛設連接器之同心圓、虛設連接器之一x形狀或虛設連接器之一隨機分佈。
- 如請求項15之方法,其中該複數個虛設連接器之相鄰者之間的一間距等於或大於該複數個功能連接器之相鄰者之間的一間距。
- 如請求項15之方法,其中在一俯視圖中,與該複數個虛設連接器之一第二側上相比,該複數個虛設連接器之一第一側上安置更多功能連接器,且其中該複數個虛設連接器之該第一側與該複數個虛設連接器之該第二側對置。
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Also Published As
Publication number | Publication date |
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US20190115326A1 (en) | 2019-04-18 |
CN107818974A (zh) | 2018-03-20 |
KR102060624B1 (ko) | 2019-12-30 |
US10510734B2 (en) | 2019-12-17 |
TWI654726B (zh) | 2019-03-21 |
US10276548B2 (en) | 2019-04-30 |
US20180076184A1 (en) | 2018-03-15 |
US20200118984A1 (en) | 2020-04-16 |
KR20180030391A (ko) | 2018-03-22 |
CN107818974B (zh) | 2020-03-31 |
US10867976B2 (en) | 2020-12-15 |
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