CN109427730A - 集成扇出型封装 - Google Patents

集成扇出型封装 Download PDF

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Publication number
CN109427730A
CN109427730A CN201810545563.7A CN201810545563A CN109427730A CN 109427730 A CN109427730 A CN 109427730A CN 201810545563 A CN201810545563 A CN 201810545563A CN 109427730 A CN109427730 A CN 109427730A
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CN
China
Prior art keywords
conductive
layer
tube core
encapsulated member
rewiring
Prior art date
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CN201810545563.7A
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English (en)
Inventor
郑心圃
刘献文
洪士庭
林仪柔
方子睿
庄博尧
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN109427730A publication Critical patent/CN109427730A/zh
Pending legal-status Critical Current

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Abstract

一种集成扇出型封装包括第一重布线结构、管芯、包封体、多个导电结构及第二重布线结构。所述第一重布线结构具有第一表面及与所述第一表面相对的第二表面。所述管芯设置在所述第一重布线结构的所述第一表面上且与所述第一重布线结构电连接。所述包封体包封所述管芯。所述导电结构设置在所述第一重布线结构的所述第一表面上且穿透所述包封体。所述导电结构环绕所述管芯。所述第二重布线结构设置在所述包封体上且通过所述导电结构与所述第一重布线结构电连接。所述第二重布线结构包括实体接触所述包封体的至少一个导电图案层。

Description

集成扇出型封装
技术领域
本发明实施例涉及一种集成扇出型封装。更具体来说，本发明实施例涉及一种具有重布线结构的导电图案层与包封体实体接触的集成扇出型封装。
背景技术
由于各种电子组件(即，晶体管、二极管、电阻器、电容器等)的集成密度的持续提高，半导体行业已经历快速增长。在很大程度上，集成密度的提高来自于最小特征大小(minimum feature size)的重复减小，此使得更多较小的组件能够集成到给定区域中。这些较小的电子组件也需要使用与先前的封装相比占用较小面积的较小的封装。
当前，集成扇出型封装因其紧凑性(compactness)而正变得日益流行。在集成扇出型封装中，形成重布线结构的步骤在封装工艺期间扮演着重要的角色。
发明内容
一种集成扇出型封装包括第一重布线结构、管芯、包封体、多个导电结构及第二重布线结构。所述第一重布线结构具有第一表面及与所述第一表面相对的第二表面。所述管芯设置在所述第一重布线结构的所述第一表面上且与所述第一重布线结构电连接。所述包封体包封所述管芯。所述导电结构设置在所述第一重布线结构的所述第一表面上且穿透所述包封体。所述导电结构环绕所述管芯。所述第二重布线结构设置在所述包封体上且通过所述导电结构与所述第一重布线结构电连接。所述第二重布线结构包括实体接触(physical contact)所述包封体的至少一个导电图案层。
附图说明
结合附图阅读以下详细说明，会最好地理解本公开的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为论述清晰起见，可任意增大或减小各种特征的尺寸。
图1A至图1J是根据本公开一些实施例的制造叠层封装(package-on-package，PoP)结构的工艺流程的示意性剖视图。
图2是根据本公开一些替代实施例的叠层封装结构的示意性剖视图。
附图标号说明
10、20：叠层封装结构
10a、10a’：第一封装结构
10b：第二封装结构
100：载板
102：剥离层
200：第一重布线结构
200a：第一表面
200b：第二表面
202：重布线导电层
204、604a、604b：介电层
206、606a、606b：导电通孔
300：管芯
300a：有源表面
300b：后表面
302：导电凸块
304、900：底部填充层
400：导电结构
400a、500a：顶表面
500：包封体
600、600’：第二重布线结构
602、602a、602b、602c：导电图案层
700：导电端子
800a：封装本体
800b：连接端子
6022：球接垫
6024：布线图案
DI：最底部介电层
DR：管芯贴合区
OP：接触开口
PR：周边区
t1、t1’、t2、t3：厚度
t4：厚度
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例以简化本公开。当然，这些仅为实例而不旨在进行限制。例如，以下说明中将第一特征形成在第二特征“之上”或第二特征“上”可包括其中第一特征及第二特征被形成为直接接触的实施例，且也可包括其中第一特征与第二特征之间可形成有附加特征、以使得所述第一特征与所述第二特征可能不直接接触的实施例。另外，本公开可在各种实例中重复使用附图标号及/或字母。这种重复使用是出于简洁及清晰的目的，而不是自身表示所论述的各种实施例及/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“在...之下(beneath)”、“在...下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括装置在使用或操作中的不同取向。装置可具有其他取向(旋转90度或其他取向)，且本文中所用的空间相对性用语可同样相应地进行解释。
本公开也可包括其他特征及工艺。举例来说，可包括测试结构，以帮助对三维(three-dimensional，3D)封装或三维集成电路(three-dimensional integratedcircuit，3DIC)装置进行验证测试。所述测试结构可例如包括在重布线层中或在衬底上形成的测试垫(test pad)，以便能够对三维封装或三维集成电路进行测试、对探针及/或探针卡(probe card)进行使用等。可对中间结构以及最终结构执行验证测试。另外，可将本文中所公开的结构及方法与包括对已知良好管芯(known good die)进行中间验证的测试方法结合使用，以提高良率并降低成本。
图1A至图1J是根据本公开一些实施例的制造叠层封装(package-on-package，PoP)结构10的工艺流程的示意性剖视图。参照图1A，提供上面形成有剥离层102的载板100。在一些实施例中，载板100是玻璃衬底。然而，其他材料也可作为载板100的材料，只要所述材料能够在承载形成在其上的封装结构的同时承受后续工艺即可。在一些实施例中，剥离层102是形成在玻璃衬底上的光热转换(light-to-heat conversion，LTHC)释放层。剥离层102可使在后续工艺中形成在载板100上的结构能够被从载板100剥除。
在载板100及剥离层102上形成第一重布线结构200。第一重布线结构200具有第一表面200a及与第一表面200a相对的第二表面200b。在一些实施例中，第二表面200b面对载板100。在一些实施例中，第二表面200b贴附到剥离层102。第一重布线结构200也包括管芯贴合区DR及环绕管芯贴合区DR的周边区PR。在一些实施例中，第一重布线结构200包括交替堆叠的多个重布线导电层202与多个介电层204。重布线导电层202通过嵌置在介电层204中的导电通孔206而彼此互连。在一些实施例中，介电层204的最底部的层(最底部介电层DI)接触剥离层102。在一些实施例中，重布线导电层202的最顶部的层被介电层204的最顶部的层暴露出。换句话说，重布线导电层202被暴露出的最顶部的层可包括多个接垫以用于与随后形成的其他组件进行电连接。在一些实施例中，上述接垫包括重布线接垫(布线接垫)及/或凸块接垫(bump pad)。在一些实施例中，重布线导电层202及导电通孔206的材料包括铝、钛、铜、镍、钨及/或其合金。重布线导电层202可通过例如电镀、沉积及/或光刻及刻蚀形成。在一些实施例中，介电层204的材料包括聚酰亚胺、环氧树脂、丙烯酸树脂、酚醛树脂、苯并环丁烯(benzocyclobutene，BCB)、聚苯并恶唑(polybenzooxazole，PBO)或任何其他合适的聚合物系介电材料。除了以上列出的材料之外，最底部介电层DI也可包含周期性介孔有机硅(periodic mesoporous organosilica，PMO)、低温聚酰亚胺(low temperaturepolyimide，LTPI)等。介电层204可通过例如旋转涂布(spin-on coating)、化学气相沉积(chemical vapor deposition，CVD)、等离子体增强型化学气相沉积(plasma-enhancedchemical vapor deposition，PECVD)等合适的制作技术来形成。
应注意的是，尽管在图1A中示出了四层重布线导电层202及五层介电层204，然而这些层的数目在本公开中并非仅限于此。在一些替代实施例中，第一重布线结构200可根据电路设计而由更多或更少层的重布线导电层202及介电层204构成。类似地，重布线导电层202中最顶部的层中的接垫的数目也不受本文所公开的实施例限制。
参照图1B，在第一重布线结构200的第一表面200a上形成多个导电结构400。导电结构400位于第一重布线结构200的周边区PR内。在一些实施例中，导电结构400是通过光刻、镀覆、光刻胶剥落工艺或任何其他合适的方法形成的导电柱。在一些实施例中，导电结构400可通过以下步骤来形成。首先，形成掩模图案(图中未示出)以覆盖第一重布线结构200的第一表面200a。掩模图案具有暴露出位于周边区PR中的最顶部的重布线导电层202的开口。之后，通过电镀或沉积将金属材料填充到所述开口中。接着，移除掩模图案以获得导电结构400。然而，本公开并非仅限于此。也可利用其他合适的方法来形成导电结构400。在一些实施例中，导电结构400的材料可包含金属材料，例如铜、铜合金等。在一些实施例中，导电结构400形成在最顶部的重布线导电层202上且接触最顶部的重布线导电层202以实现与第一重布线结构200的电连接。应注意的是，出于例示目的在图1C中仅呈现出两个导电结构400。然而，在一些替代实施例中可形成多于两个导电结构400。可根据需求来选择导电结构400的数目。
参照图1C，在第一重布线结构200的第一表面200a上设置管芯300。管芯300被放置在第一重布线结构200的管芯贴合区DR内。由于周边区PR环绕管芯贴合区DR，因此导电结构400可被排列成环绕管芯300。在一些实施例中，通过倒装芯片(flip chip)接合将管芯300耦合至第一重布线结构200的第一表面200a。举例来说，管芯300具有面对第一重布线结构200的第一表面200a的有源表面300a及与有源表面300a相对的后表面300b。在一些实施例中，可通过位于管芯300的有源表面300a与重布线导电层202的最顶部的层(最顶部的重布线导电层202)之间的多个导电凸块302将管芯300与第一重布线结构200电连接。在一些实施例中，导电凸块302是焊料凸块、银球、铜球或任何其他合适的金属球。在一些实施例中，可在导电凸块302上涂抹助焊剂(soldering flux，图中未示出)以实现更好的粘合。在一些实施例中，可利用底部填充层304填充管芯300、第一重布线结构200及导电凸块302之间的间隙以增强可靠性。在一些替代实施例中，可省略底部填充层304。在一些替代实施例中，不在管芯300与第一重布线结构200之间提供底部填充。尽管图1B及图1C示出在形成管芯300之前形成导电结构400，然而本公开并非仅限于此。在一些替代实施例中，可在形成管芯300之后提供导电结构400。参照图1A及图1C，由于第一重布线结构200是在放置管芯300之前形成，因此在一些实施例中，可将上述工艺视为“先重布线层方法(RDL first method)”。此外，由于管芯300是通过倒装芯片接合而耦合到第一重布线结构200的第一表面200a，因此可省略在传统的封装结构中用于对管芯进行粘合的管芯贴合膜(die attach film，DAF)或导线上膜(film on wire，FOW)。因此，随后形成的封装结构的总厚度可明显减小。
参照图1D，在第一重布线结构200上形成包封体500。包封体500覆盖且包封管芯300及导电结构400。在一些实施例中，包封体500是通过包覆模塑(over-molding)工艺形成的模塑化合物。在一些替代实施例中，包封体500的材料包括环氧树脂或其他合适的树脂。在这一阶段期间，管芯300及导电结构400不会露出且会受到包封体500的良好保护。
参照图1E，将包封体500平坦化直到暴露出导电结构400的顶表面400a为止。在一些实施例中，在暴露出导电结构400的顶表面400a之后，进一步对包封体500及导电结构400进行研磨以减小封装结构的总厚度。然而，包封体500及导电结构400是采用使得管芯300的后表面300b仍受到包封体500的良好保护而不会被包封体500露出的方式来进行研磨。参照图1E，在平坦化工艺之后，包封体500的顶表面500a与导电结构400的顶表面400a实质上共面。由于导电结构400穿透过包封体500，因此在一些实施例中，导电结构400可被称为层间穿孔(through interlayer via，TIV)或集成扇出型(integrated fan-out，InFO)穿孔。包封体500可通过例如研磨工艺或化学机械抛光(chemical mechanical polishing，CMP)工艺进行平坦化。在平坦化或研磨工艺之后，可以可选地执行清洁步骤以移除所产生的残渣。然而，本公开并非仅限于此，且可通过任何其他合适的方法来执行平坦化工艺。
参照图1F，在将包封体500平坦化以暴露出导电结构400之后，在包封体500及导电结构400上形成第二重布线结构600。在一些实施例中，导电结构400与第二重布线结构600相连。第二重布线结构600通过导电结构400与第一重布线结构200进行电连接。在一些实施例中，第二重布线结构600包括至少一个导电图案层602，且导电图案层602实体接触(physical contact)包封体500。换句话说，导电结构400直接接触导电图案层602且在所述导电图案层602与包封体500之间未夹置有介电层。举例来说，参照图1F，在一些实施例中，第二重布线结构600是由单层导电图案层602形成的结构，且所述单层导电图案层602直接接触包封体500。导电图案层602还可包括布线图案(routing pattern)6024以及用于与其他电子元件电连接的多个球接垫(ball pad)6022。在一些实施例中，球接垫6022对应于位于球接垫6022下面的导电结构400设置。举例来说，每一个球接垫6022可对应于一个导电结构400。在一些实施例中，导电图案层602从周边区PR延伸到管芯贴合区DR中。在一些实施例中，球接垫6022位于周边区PR中，而布线图案6024位于管芯贴合区DR中。在一些替代实施例中，球接垫6022同时位于周边区PR与管芯贴合区DR二者中，以使得位于管芯300上方的空间可有效地被用于电连接。在一些实施例中，第二重布线结构600(导电图案层602)被形成为具有1μm到30μm的厚度t1。应注意的是，图1F中所呈现的单层式第二重布线结构600仅为第二重布线结构600的例示性实例，且本公开并非仅限于此。在一些替代实施例中，第二重布线结构600可为多层式结构。随后将与图2一同更详细地论述所述多层式重布线结构。
再次参照图1F，导电图案层602的材料包括例如铝、钛、铜、镍、钨及/或其合金。在一些实施例中，第二重布线结构600的导电图案层602可通过以下步骤来形成。首先，在包封体500及导电结构400上溅镀晶种层(图中未示出)。晶种层可包括钛层、铜层、钛/铜复合层或任何其他合适的导电材料层。接着，可在晶种层上设置具有开口的图案化光刻胶层(图中未示出)以形成第二重布线结构600的导电图案层602的轮廓。之后，可执行镀覆工艺以将导电图案层602沉积到被图案化光刻胶层的开口暴露出的晶种层上。最后，将图案化光刻胶层以及被图案化光刻胶层遮蔽的晶种层一同移除以形成图1F所示的第二重布线结构600。
在一些实施例中，由于工艺步骤的顺序，在形成第一重布线结构200之后，在包封体500上直接形成第二重布线结构600的导电图案层602而不在包封体500上形成一个或多个介电层。在某些实施例中，由于第二重布线结构600的导电图案层602直接实体接触导电结构400且在导电图案层602与导电结构400之间不存在有介电层，因此可省略用于移除介电层并暴露出导电结构的激光钻孔步骤。因此，可降低总生产成本。另外，由于在包封体500与导电图案层602之间未形成介电层且在管芯300与导电图案层602之间未形成管芯贴合膜层/导线上膜层，因此可消除在传统的介电层及传统的粘合层中所见的空隙问题(voidissue)，从而进一步改善封装结构的平整性(planarity)。因此，可充分消除重布线结构中导电迹线/布线图案的破裂，从而增强封装结构的可靠性。此外，在一些实施例中，由于第二重布线结构600的导电图案层602直接形成在包封体500上而在导电图案层602与包封体500之间不存在有介电层，因此第二重布线结构600的厚度t1可有效地减小到1μm到30μm。此外，如上所述，由于管芯300是通过倒装芯片接合而耦合到第一重布线结构200，因此可省略在传统的封装结构中用于对管芯进行粘合的管芯贴合膜或导线上膜。由于省略了各个层(例如，第二重布线结构600中的某些介电层以及管芯贴合膜/导线上膜)，因此可有效地减小后续形成的封装结构的总厚度以满足轻薄及紧凑(compact)要求。
参照图1G，将第一重布线结构200从载板100分离以使第一重布线结构200的第二表面200b被暴露出。举例来说，可暴露出最底部介电层DI。在一些实施例中，剥离层102是光热转换释放层。在利用紫外(ultraviolet，UV)激光进行照射时，可剥除并移除剥离层102及载板100。应注意的是，剥离工艺并非仅限于此。在一些替代实施例中可使用其他合适的方法。在一些实施例中，图1G所示结构具有为100μm到550μm的厚度t2。
参照图1H，在移除剥离层102及载板100之后，将最底部介电层DI图案化以形成多个接触开口OP来局部地暴露出重布线导电层202的最底部的层(最底部的重布线导电层202)以用作电连接。在一些实施例中，通过激光钻孔工艺、机械钻孔工艺、光刻工艺或其他合适的工艺形成最底部介电层DI的接触开口OP。在一些实施例中，在最底部的重布线导电层202上及第一重布线结构200的第二表面200b上形成多个导电端子700，以形成第一封装结构10a。在一些实施例中，第一封装结构10a被形成为具有介于150μm与600μm之间的厚度t3。如上所述，第二重布线结构600具有为1μm到30μm的厚度t1。因此，在一些实施例中，第二重布线结构600的厚度t1对第一封装结构10a的厚度t3的比率介于1:5与1:600之间。换句话说，第二重布线结构600就厚度而言是第一封装结构10a的0.17％到20％。在某些实施例中，最底部的重布线导电层202从最底部介电层DI暴露出，且被暴露出的最底部的重布线导电层202包括用于安装球的球下金属(under-ball metallurgy，UBM)图案。导电端子700形成在相应的球下金属图案上。在一些实施例中，导电端子700的一部分通过第一重布线结构200以及位于管芯300下面的导电凸块302与管芯300电连接。另一方面，导电端子700的另一部分通过第一重布线结构200及导电结构400与第二重布线结构600电连接。在一些实施例中，导电端子700通过助焊剂(图中未示出)贴合到球下金属图案。在一些实施例中，导电端子700是例如焊料球或球栅阵列(ball grid array，BGA)球。在一些实施例中，导电端子700可通过植球工艺或回焊工艺设置在球下金属图案上。
参照图1I，在第一封装结构10a上堆叠第二封装结构10b。在一些实施例中，第二封装结构10b包括封装本体(package body)800a以及贴合到封装本体800a的多个连接端子800b。在一些实施例中，第二封装结构10b的封装本体800a包括例如至少存储器装置。然而，本公开并非仅限于此。基于叠层封装结构的功能需求，可采用其他封装结构作为第二封装结构10b。第二封装结构10b的连接端子800b可类似于第一封装结构10a的导电端子700。举例来说，连接端子800b是焊料球或球栅阵列(BGA)球。在一些实施例中，连接端子800b可通过植球工艺或回焊工艺贴合到封装本体800a。在一些实施例中，连接端子800b设置在位于周边区PR中的球接垫6022上。在一些替代实施例中，连接端子800b设置在同时位于周边区PR及管芯贴合区DR二者中的球接垫6022上。在一些实施例中，第二封装结构10b的封装本体800a通过连接端子800b与第一封装结构10a电连接。换句话说，可利用位于管芯300上方的空间进行球安装，从而实现电路设计的灵活性。
参照图1J，在第一封装结构10a上堆叠第二封装结构10b之后，形成底部填充层900来获得叠层封装结构10。在一些实施例中，底部填充层900填充到第一封装结构10a、封装本体800a及连接端子800b之间的间隙中。在一些替代实施例中，底部填充层900是可选地形成的且可被省略。在一些实施例中，底部填充层900可类似于第一封装结构10a的底部填充层304以增强贴合工艺的可靠性。在一些实施例中，叠层封装结构10的厚度t4介于730μm到1000μm的范围内。
如上所述，由于省略了各个层(例如，第二重布线结构600中的某些介电层以及管芯贴合膜/导线上膜)，因此与传统的封装结构相比，可有效地减小第一封装结构10a的总厚度。由于叠层封装结构10是通过在第一封装结构10a上堆叠第二封装结构10b来形成，通过第一封装结构10a的轻薄特征，叠层封装结构10的总厚度t4也可得到充分减小。举例来说，与传统的封装结构或传统的叠层封装结构相比，在厚度上可取得10％到35％的减小。
图2是根据本公开一些替代实施例的叠层封装结构20的示意性剖视图。参照图2，图2的叠层封装结构20类似于图1J所示的叠层封装结构10，而不同之处在于在图2所示的叠层封装结构20中，第一封装结构10a’的第二重布线结构600’是多层式结构。在一些实施例中，第二重布线结构600’包括交替堆叠的多个导电图案层602a、602b、602c及多个介电层604a、604b。介电层604a、604b分别夹置在两相邻的导电图案层602a、602b、602c之间。举例来说，介电层604a夹置在导电图案层602a与导电图案层602b之间。另一方面，介电层604b夹置在导电图案层602b与导电图案层602c之间。导电图案层602a、602b、602c通过穿透过介电层604a、604b/嵌置在介电层604a、604b中的导电通孔606a、606b电性互连。在一些实施例中，第二重布线结构600’被形成为具有1μm到30μm的厚度t1’。
在一些实施例中，最顶部的导电图案层(导电图案层602c)的至少一部分及最底部的导电图案层(导电图案层602a)的至少一部分分别被最顶部的介电层(介电层604b)及最底部的介电层(介电层604a)暴露出。最底部的导电图案层(导电图案层602a)实体接触包封体500及导电结构400。另一方面，最顶部的导电图案层(导电图案层602c)可包括多个球接垫且可用于与随后形成的其他组件进行电连接。在一些实施例中，上述接垫被称为用于安装球的球下金属(UBM)图案。在一些实施例中，导电图案层602a、602b、602c的材料及导电通孔606a、606b的材料包括铝、钛、铜、镍、钨及/或其合金。导电图案层602a、602b、602c可通过例如电镀、沉积及/或光刻及刻蚀形成。在一些实施例中，介电层604a、604b的材料包括聚酰亚胺、环氧树脂、丙烯酸树脂、酚醛树脂、苯并环丁烯(BCB)、聚苯并恶唑(PBO)或任何其他合适的聚合物系介电材料。介电层604a、604b可通过例如旋转涂布、化学气相沉积(CVD)、等离子体增强型化学气相沉积(PECVD)等合适的制作技术来形成。应注意的是，图2所呈现的导电图案层及介电层的数目仅用作示例性例示且不旨在限制本公开。在一些替代实施例中，基于电路设计要求，导电图案层及介电层的数目与图2所提供的例示相比可更多或更少。
在一些实施例中，由于工艺步骤的顺序，在形成第一重布线结构200之后，在包封体500上直接形成第二重布线结构600’的导电图案层602a而不在导电图案层602a与包封体500之间形成一个或多个介电层。在某些实施例中，由于第二重布线结构600’的导电图案层602a直接实体接触导电结构400且在导电图案层602a与导电结构400之间不存在有介电层，因此可省略用于移除介电层并暴露出导电结构的激光钻孔步骤。因此，可降低总生产成本。另外，由于在包封体500与导电图案层602a之间未形成介电层且在管芯300与导电图案层602a之间未形成管芯贴合膜层/导线上膜层，因此可消除在传统的介电层及传统的粘合层中所见的空隙问题，从而进一步改善封装结构的平整性。因此，可充分消除重布线结构中导电迹线/布线图案的破裂，从而增强封装结构的可靠性。此外，在一些实施例中，由于第二重布线结构600的导电图案层602a直接形成在包封体500上而在导电图案层602a与包封体500之间不存在有介电层，因此第二重布线结构600’的厚度t1’可有效地减小到1μm到30μm。此外，如上所述，由于管芯300是通过倒装芯片接合而耦合到第一重布线结构200，因此可省略在传统的封装结构中用于对管芯进行粘合的管芯贴合膜或导线上膜。由于省略了各个层(例如，第二重布线结构600’中的某些介电层以及管芯贴合膜/导线上膜)，因此可有效地减小叠层封装结构20的总厚度以满足轻薄及紧凑要求。
根据本公开的一些实施例，一种集成扇出型封装包括第一重布线结构、管芯、包封体、多个导电结构及第二重布线结构。所述第一重布线结构具有第一表面及与所述第一表面相对的第二表面。所述管芯设置在所述第一重布线结构的所述第一表面上且与所述第一重布线结构电连接。所述包封体包封所述管芯。所述导电结构设置在所述第一重布线结构的所述第一表面上且穿透所述包封体。所述导电结构环绕所述管芯。所述第二重布线结构设置在所述包封体上且通过所述导电结构与所述第一重布线结构电连接。所述第二重布线结构包括实体接触(physical contact)所述包封体的至少一个导电图案层。
根据本公开的一些实施例，所述集成扇出型封装还包括设置在所述第一重布线结构的所述第二表面上的多个导电端子。
根据本公开的一些实施例，所述管芯通过多个导电凸块与所述第一重布线结构电连接。
根据本公开的一些实施例，所述第二重布线结构的厚度对所述集成扇出型封装的厚度的比率介于1:5到1:600的范围内。
根据本公开的一些实施例，所述第二重布线结构包括多个导电图案层及夹置在两相邻的导电图案层之间的多个介电层，且所述多个导电图案层中的最底部的导电图案层实体接触所述包封体。
根据本公开的一些实施例，所述多个导电结构包括层间穿孔(throughinterlayer via)且所述最底部的导电图案层实体接触所述多个导电结构。
根据本公开的一些实施例，所述多个导电图案层中的最顶部的导电图案层包括多个球接垫(ball pad)及多个布线图案(routing patterns)。
根据本公开的一些替代实施例，一种叠层封装(package-on-package，PoP)结构包括第一封装结构以及堆叠在所述第一封装结构上的第二封装结构。所述第一封装结构包括第一重布线结构、管芯、多个导电结构、包封体及导电图案层。所述第一重布线结构具有管芯贴合区及环绕所述管芯贴合区的周边区。所述管芯设置在所述第一重布线结构的所述管芯贴合区上。所述导电结构设置在所述第一重布线结构的所述周边区上。所述包封体包封所述管芯及所述导电结构。导电图案层设置在所述包封体上且实体接触所述包封体。所述导电图案层通过所述导电结构与所述第一重布线结构电连接，且包括多个球接垫及多个布线图案。
根据本公开的一些替代实施例，所述叠层封装结构还包括设置在所述第一重布线结构上的多个导电端子。
根据本公开的一些替代实施例，所述第二封装结构包括封装本体(package body)及贴合到所述封装本体的多个连接端子，且所述封装本体通过所述多个连接端子与所述第一封装结构电连接。
根据本公开的一些替代实施例，所述叠层封装结构还包括底部填充层，所述底部填充层填充所述第一封装结构、所述封装本体及所述多个连接端子之间的间隙。
根据本公开的一些替代实施例，所述连接端子设置在位于所述周边区及所述管芯贴合区二者中的所述多个球接垫上。
根据本公开的一些替代实施例，所述管芯通过多个导电凸块与所述第一重布线结构电连接。
根据本公开的一些替代实施例，所述导电图案层的厚度对所述第一封装结构的厚度的比率介于1:5到1:600的范围内。
根据本公开的一些实施例，一种制造叠层封装结构的方法包括至少以下步骤。首先提供载板。接着，形成第一封装结构。之后，将第二封装结构堆叠在所述第一封装结构上。所述第一封装结构是通过至少以下步骤形成。首先，在载板上形成第一重布线结构。所述第一重布线结构具有第一表面及与所述第一表面相对的第二表面，且所述第二表面面对所述载板。接着，在所述重布线结构的所述第一表面上提供/形成管芯及多个导电结构。所述导电结构环绕所述管芯。使用包封体包封所述管芯及所述导电结构。之后，在包封体上形成第二重布线结构。所述第二重布线结构通过所述导电结构与所述第一重布线结构电连接。所述第二重布线结构包括实体接触所述包封体的至少一个导电图案层。然后，将所述载板从所述第一重布线结构分离及移除。
根据本公开的一些实施例，制造叠层封装结构的方法还包括在将所述载板从所述第一重布线结构移除后，在所述第一重布线结构的所述第二表面上形成多个导电端子。
根据本公开的一些实施例，形成所述第二重布线结构包括形成多个导电图案层及形成夹置在两相邻的导电图案层之间的多个介电层，且所述多个导电图案层中的最底部的导电图案层实体接触所述包封体。
根据本公开的一些实施例，所述多个导电图案层中的最顶部的导电图案层包括多个球接垫及多个布线图案。
根据本公开的一些实施例，所述第二封装结构包括封装本体及贴合到所述封装本体的多个连接端子，且所述多个连接端子设置在所述多个球接垫上以使所述封装本体通过所述多个连接端子与所述第一封装结构电连接。
根据本公开的一些实施例，制造叠层封装结构的方法还包括形成底部填充层，以填充所述第一封装结构、所述封装本体及所述多个连接端子之间的间隙。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本公开的各个方面。所属领域中的技术人员应知，他们可容易地使用本公开作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的及/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本公开的精神及范围，而且他们可在不背离本公开的精神及范围的条件下对其作出各种改变、代替及变更。

Claims (1)

1.一种集成扇出型封装，其特征在于，包括：
第一重布线结构，具有第一表面及与所述第一表面相对的第二表面；
管芯，设置在所述第一重布线结构的所述第一表面上，其中所述管芯与所述第一重布线结构电连接；
包封体，包封所述管芯；
多个导电结构，设置在所述第一重布线结构的所述第一表面上且穿透所述包封体，其中所述多个导电结构环绕所述管芯；以及
第二重布线结构，设置在所述包封体上，其中所述第二重布线结构通过所述多个导电结构与所述第一重布线结构电连接，所述第二重布线结构包括实体接触所述包封体的至少一个导电图案层。
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US20190067144A1 (en) 2019-02-28
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US20210358824A1 (en) 2021-11-18

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