CN109659292A - 集成扇出型封装 - Google Patents

集成扇出型封装 Download PDF

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Publication number
CN109659292A
CN109659292A CN201810031594.0A CN201810031594A CN109659292A CN 109659292 A CN109659292 A CN 109659292A CN 201810031594 A CN201810031594 A CN 201810031594A CN 109659292 A CN109659292 A CN 109659292A
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CN
China
Prior art keywords
layer
conductive
dielectric layer
tube core
dielectric
Prior art date
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CN201810031594.0A
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English (en)
Inventor
游济阳
陈衿良
陈海明
何冠霖
梁裕民
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN109659292A publication Critical patent/CN109659292A/zh
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Abstract

一种集成扇出型封装包括管芯、包封体、重布线结构、多个导电柱、晶种层、及多个导电凸块。所述包封体包封所述管芯。所述重布线结构位于所述管芯及所述包封体上。所述重布线结构与所述管芯电连接且包括依序堆叠的多个介电层以及夹置在所述介电层之间的多个导电图案。距所述管芯最远的所述介电层的杨氏模量高于所述介电层中其余介电层中的每一者的杨氏模量。所述导电图案彼此电连接。所述导电柱设置在所述重布线结构上且与所述重布线结构电连接。所述晶种层位于所述导电柱与所述重布线结构之间。所述导电凸块设置在所述多个导电柱上。

Description

集成扇出型封装
技术领域
本发明实施例涉及一种集成扇出型封装。更具体来说，本发明实施例涉及一种具有抗应力层的集成扇出型封装。
背景技术
由于各种电子组件(即，晶体管、二极管、电阻器、电容器等)的集成密度的持续提高，半导体行业已经历快速发展。在很大程度上，集成密度的此种提高来自于最小特征大小(minimum feature size)的重复减小，此使得更多较小的组件能够集成到给定区域中。当前，集成扇出型封装因其紧密性而正变得日渐流行。集成扇出型封装通常包括位于模塑的集成电路装置上的重布线路结构，以使得所述集成电路装置可被存取。为满足更小大小及更高封包密度的要求，重布线路结构的制造方法已成为本领域中的重要议题。
发明内容
一种集成扇出型封装包括管芯、包封体、重布线结构、多个导电柱、晶种层、及多个导电凸块。所述包封体包封所述管芯。所述重布线结构位于所述管芯及所述包封体上。所述重布线结构与所述管芯电连接且包括依序堆叠的多个介电层以及夹置在所述介电层之间的多个导电图案。距所述管芯最远的所述介电层的杨氏模量高于所述介电层中其余介电层中的每一者的杨氏模量。所述导电图案彼此电连接。所述导电柱设置在所述重布线结构上且与所述重布线结构电连接。所述晶种层位于所述导电柱与所述重布线结构之间。所述导电凸块设置在所述导电柱上。
附图说明
结合附图阅读以下详细说明，会最好地理解本发明的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为论述清晰起见，可任意增大或减小各种特征的尺寸。
图1A至图1F示出根据本发明一些实施例的制造集成扇出型封装的方法的各工艺的示意性剖视图。
图2A至图2K是以区R为着重点示出根据本发明一些实施例的示例性封装的制造方法的各工艺的示意性放大剖视图。
图3A至图3J是以区R为着重点示出根据本发明一些替代性实施例的示例性封装的制造方法的各工艺的示意性放大剖视图。
图4A至图4J是以区R为着重点示出根据本发明一些替代性实施例的示例性封装的制造方法的各工艺的示意性放大剖视图。
图5A是以区R为着重点示出根据本发明一些替代性实施例的示例性封装的示意性放大剖视图。
图5B示出图5A中所示的缓冲层及导电柱的示意性俯视图。
图6A至图6I是以区R为着重点示出根据本发明一些替代性实施例的示例性封装的制造方法的各工艺的示意性放大剖视图。
图7A是以区R为着重点示出根据本发明一些替代性实施例的示例性封装的示意性放大剖视图。
图7B示出图7A中所示的缓冲层及导电柱的示意性俯视图。
图8示出包括图1F中的集成扇出型封装的堆叠封装结构的示意图。
附图标号说明
10：集成扇出型封装
20：衬底
30：印刷电路板
100、100a：管芯
110：半导体衬底
120：导电接垫
130：钝化层
140：后钝化层
150、150a：导电柱体
160、160a：保护层
200：包封材料
200a：包封体
300：重布线结构
310、316：介电材料层
310a：第一介电层
312a：第二介电层
314a：第三介电层
316a：第四介电层
320a：第一导电图案
322a：第二导电图案
324a：第三导电图案
410、410a：晶种层
412、412a：第二晶种层
420：导电柱
420a：第一导电材料
420b：第二导电材料
430：焊料材料
500：导电凸块
600、600a：缓冲层
C：载体衬底
DB：剥离层
O310a、O316a、O600a：开口
P1：第一部分
P2：第二部分
PR：光刻胶图案层
PR1：第一光刻胶图案层
PR2：第二光刻胶图案层
R：区
SW316a：侧壁
W1：最大直径
W2：距离
具体实施方式
以下公开内容提供用于实作所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例以简化本公开内容。当然，这些仅为实例且不旨在进行限制。举例来说，以下说明中将第一特征形成在第二特征“之上”或第二特征“上”可包括其中第一特征及第二特征被形成为直接接触的实施例，且也可包括其中第一特征与第二特征之间可形成有附加特征、进而使得所述第一特征与所述第二特征可能不直接接触的实施例。另外，本公开内容可能在各种实例中重复使用参考编号及/或字母。这种重复使用是出于简洁及清晰的目的，而不是自身表示所论述的各种实施例及/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括装置在使用或操作中的不同取向。设备可具有其他取向(旋转90度或处于其他取向)，且本文中所使用的空间相对性描述语可同样相应地进行解释。
也可包括其他特征及工艺。举例来说，可包括测试结构，以帮助对三维(three-dimensional，3D)封装或三维集成电路(3D integrated circuit，3DIC)装置进行验证测试。所述测试结构可例如包括在重布线层中或在衬底上形成的测试接垫，以容许对三维封装或三维集成电路进行测试、对探针及/或探针卡(probe card)进行使用等。可对中间结构以及最终结构执行验证测试。另外，本文中所公开的结构及方法可结合包括对已知良好管芯(known good die)进行中间验证的测试方法而使用，以提高良率并降低成本。
图1A至图1F示出根据本发明一些实施例的制造集成扇出型封装10的方法的各工艺的示意性剖视图。参照图1A，提供上面形成有剥离层DB的载体衬底C。在一些实施例中，载体衬底C可为玻璃衬底，且剥离层DB可为形成在所述玻璃衬底上的光热转换(light-to-heat conversion，LTHC)释放层。在一些实施例中，可在剥离层DB上可选地形成介电层(图中未示出)。
如图1A中所示，在载体衬底C上提供及放置多个管芯100。在一些实施例中，可通过拾取及放置工艺(pick and place process)将管芯100放置在剥离层DB上。可将管芯100通过管芯贴合膜(die attach film，DAF)、粘合膏(adhesion paste)等贴合或粘合在剥离层DB上。为简洁起见，在图1A中仅示出一个管芯100。然而，可提供多于一个管芯且可将所述管芯排列成阵列。应理解，本发明的范围不受所公开实例限制。在一些实施例中，可将当前工艺步骤视作晶片级封装工艺(wafer level packaging process)的一部分。
在一些实施例中，如图1A中所示，每一管芯100包括半导体衬底110、多个导电接垫120、钝化层(passivation layer)130、后钝化层(post-passivation layer)140、多个导电柱体150、及保护层160。在一些实施例中，半导体衬底110可为硅衬底，所述硅衬底包括形成在所述硅衬底中的有源组件(例如，晶体管等)及可选地形成在所述硅衬底中的无源组件(例如，电阻器、电容器、电感器等)。导电接垫120形成在半导体衬底110上且可为铝接垫、铜接垫、或其他适合的金属接垫。导电柱体150设置在导电接垫120上且与导电接垫120电连接。在一些实施例中，导电柱体150是通过导电材料的镀覆工艺(plating process)形成在导电接垫120上。在一些实施例中，导电柱体150可为镀铜柱或其他适合的金属柱。在一些替代性实施例中，导电柱体150为被焊料顶盖(例如，不含铅的焊料顶盖)覆盖的铜柱或其他适合的金属柱。在一些实施例中，保护层160可为具有足以包封及保护导电柱体150的厚度的聚合物层。在一些实施例中，保护层160的材料包括聚苯并恶唑(polybenzoxazole，PBO)、聚酰亚胺(polyimide，PI)、或其他适合的聚合材料。在一些替代性实施例中，保护层160可由无机材料制成。在一些实施例中，后钝化层140是可选的。
参照图1B，在剥离层DB上形成包封材料200以包封管芯100。换句话说，将所有管芯100(在图1B中仅示出一个管芯)模塑及嵌置在包封材料200中。在一些实施例中，通过模塑工艺(molding process)来形成包封材料200。管芯100的导电柱体150及保护层160被包封材料200完全覆盖。换句话说，管芯100的导电柱体150及保护层160不会被显露出且被包封材料200很好地保护。在一些替代性实施例中，包封材料200的材料包括环氧树脂(epoxyresin)或其他适合的介电材料。
参照图1C，接着对包封材料200进行研磨直到暴露出导电柱体150为止，以形成包封体200a。在一些实施例中，通过机械研磨工艺(mechanical grinding process)及/或化学机械抛光(chemical mechanical polishing，CMP)工艺来研磨包封材料200。在包封材料200的研磨工艺期间，对保护层160的部分及导电柱体150的部分进行研磨以形成保护层160a及导电柱体150a。如图1C中所示，包封体200a环绕管芯100a且在侧向上包封管芯100a的侧壁。换句话说，包封体200a环绕且包裹管芯100a(在图1C中仅示出一个管芯)的侧壁。在一些实施例中，包封体200a的顶表面、导电柱体150a的顶表面、及保护层160a的顶表面实质上共面且彼此齐平。
参照图1D，在包封体200a上形成覆盖管芯100a的重布线结构300。在一些实施例中，晶种层410a及多个导电柱420随后形成在重布线结构300上。此后，在导电柱420上形成多个导电凸块500。在一些实施例中，导电柱420与导电凸块500统称为受控塌陷芯片连接(controlled collapse chip connect，C4)凸块。在图1D中，区R是由虚线所包围，且区R会在之后进一步示出，以阐述重布线结构300、导电柱420、及导电凸块500之间的连接。可在示意性放大图中示出此种区R以在以下段落中进一步阐述制造工艺及可能的结构性变更。在一些实施例中，重布线结构300包括依序堆叠的第一介电层310a、第二介电层312a、第三介电层314a、及第四介电层316a。在一些实施例中，重布线结构300还包括彼此电连接的多个第一导电图案320a、多个第二导电图案322a、及多个第三导电图案324a。第一导电图案320a夹置在第一介电层310a与第二介电层312a之间。相似地，第二导电图案322a及第三导电图案324a分别夹置在第二介电层312a与第三介电层314a之间及第三介电层314a与第四介电层316a之间。在一些实施例中，重布线结构300与管芯100a电连接。举例来说，第一导电图案320a可接触管芯100a的导电柱体150a以在所述二者之间实现电连接。在一些实施例中，对于具有四个介电层的重布线结构来说，第四介电层316a被称作在与管芯100a(在图1D中仅示出一个管芯)的顶表面垂直的方向上距管芯100a最远的介电层。在特定实施例中，距管芯100a最远的介电层或用于接纳(receiving)导电柱420的介电层的杨氏模量(Young'smodulus)(弹性模量)高于重布线结构300的其他介电层。相似地，第三导电图案324a被称作在与管芯100a的顶表面垂直的方向上距管芯100a最远的导电图案。在一些实施例中，第四介电层316a的杨氏模量高于第一介电层310a的杨氏模量、第二介电层312a的杨氏模量、及第三介电层314a的杨氏模量。在一些实施例中，第四介电层316a的杨氏模量介于0.5GPa至150GPa的范围内。另一方面，第一介电层310a的杨氏模量、第二介电层312a的杨氏模量、及第三介电层314a的杨氏模量介于0.1GPa至100GPa的范围内。在特定实施例中，第四介电层316a的杨氏模量对第一介电层310a、第二介电层312a、或第三介电层314a的杨氏模量的比率介于1.05至100的范围内。当杨氏模量的比率低于1.05时，第四介电层316a不能够承受住从导电柱420所产生的应力，而使重布线结构300中的导电图案变形。另一方面，当杨氏模量的比率超过100时，第四介电层316a将呈现与纯硅的硬度相似的硬度，由此增大加工难度。在一些实施例中，第四介电层316a的厚度大于第一介电层310a的厚度、第二介电层312a的厚度、或第三介电层314a的厚度。在一些实施例中，较高的杨氏模量使得第四介电层316a能够减轻或阻挡从导电柱420施加到下伏重布线结构300的应力，从而保护重布线结构300中的导电图案不因在装配工艺及/或热工艺期间产生的应力而损坏。换句话说，具有较高杨氏模量的第四介电层316a有助于减轻重布线结构300中的精细线变形(fine linedeformation)问题。因此，在一些实施例中，可将重布线结构300的第四介电层316a称作抗应力层(anti-stress layer)。应注意，尽管图1D绘示四个介电层及三个导电图案层，然而此配置仅充当实例。在一些替代性实施例中，重布线结构300可包括更多层或更少层的介电层及导电图案层。
如图1D中所示，在一些实施例中，在形成导电柱420之前形成晶种层410a且晶种层410a夹置在导电柱420与重布线结构300之间。在一些实施例中，导电柱420与重布线结构300电连接。举例来说，导电柱420可与第三导电图案324a电连接。随后将结合图2A至图2K、图3A至图3J、图4A至图4J、图5A、图6A至图6I、及图7A来更详细地论述与重布线路结构300、晶种层410a、导电柱420、及导电凸块500的形成相关的说明。
参照图1E，将包括导电凸块500、导电柱420、重布线结构300、包封体200a、及管芯100a(在图1F中仅示出一个管芯)的集成扇出型封装阵列从剥离层DB剥离，以使得管芯100a及包封体200a与载体衬底C分离。在一些实施例中，可对剥离层DB(例如，光热转换释放层)照射紫外光激光(UV laser)，以将剥离层DB从管芯100a及包封体200a剥离而获得集成扇出型封装阵列。
参照图1F，对集成扇出型封装阵列进行切割或单体化以形成多个集成扇出型封装10。在一些实施例中，切割工艺或单体化工艺通常涉及使用旋转刀片或激光束来进行切割。换句话说，切割工艺或单体化工艺为例如激光切削工艺(laser cutting process)、机械切削工艺(mechanical cutting process)、或其他适合的工艺。
图2A至图2K是以区R为着重点示出根据本发明一些实施例的示例性封装的制造方法的各工艺的示意性放大剖视图。图2A至图2K示出用于在与图1C至图1D中所绘示的结构相似的包封体200a及管芯100a上形成重布线结构300、导电柱420、及导电凸块500的详细工艺步骤。参照图2A，在保护层160a、导电柱体150a、及包封体200a上形成介电材料层310。在一些实施例中，介电材料层310的材料包括聚酰亚胺、环氧树脂、丙烯酸树脂、酚醛树脂、苯并环丁烯(benzocyclobutene，BCB)、聚苯并恶唑(PBO)或任何其他适合的聚合物系介电材料。在一些实施例中，介电材料层310的杨氏模量介于0.1GPa至100GPa的范围内且厚度介于1微米(μm)至50μm的范围内。举例来说，可通过例如旋转涂布(spin-on coating)、化学气相沉积(chemical vapor deposition，CVD)、等离子体增强型化学气相沉积(plasma-enhancedchemical vapor deposition，PECVD)等适合的制作技术来形成介电材料层310。
参照图2B，在一些实施例中，将介电材料层310图案化以形成具有多个开口O310a的第一介电层310a。在一些实施例中，开口O310a暴露出位于第一介电层310a下的导电柱体150a。可通过光刻工艺(photolithography process)及刻蚀工艺(etching process)来将介电材料层310图案化。此后，在第一介电层310a上形成第一导电图案320a。在一些实施例中，第一导电图案320a延伸到开口O310a中从而接触导电柱体150a。第一导电图案320a可通过例如电镀(electroplating)、沉积(deposition)、及/或光刻及刻蚀等来形成。在一些实施例中，第一导电图案320a的材料包括铝、钛、铜、镍、钨、及/或其合金。
参照图2C，重复进行在与图2B有关的上下文中阐述的工艺步骤以依序形成第二介电层312a、第二导电图案322a、第三介电层314a、及第三导电图案324a。在一些实施例中，第一介电层310a的材料、第二介电层312a的材料、及第三介电层314a的材料可为相同的。在一些实施例中，第一介电层310a的材料、第二介电层312a的材料、及第三介电层314a的材料可为不同的，只要其各自的杨氏模量落于0.1GPa至100GPa的范围内即可。相似地，第一导电图案320a的材料、第二导电图案322a的材料、及第三导电图案324a的材料可为相同的或不同的。
参照图2D及图2E，在第三介电层314a及第三导电图案324a上形成第四介电层316a。在一些实施例中，可首先在第三介电层314a及第三导电图案324a上形成介电材料层316。随后，将介电材料层316图案化以形成具有多个开口O316a的第四介电层316a。开口O316a暴露出位于第四介电层316a下的第三导电图案324a。在一些实施例中，可通过光刻工艺及刻蚀工艺来将介电材料层316图案化。在一些实施例中，第四介电层316a的材料不同于第一介电层310a的材料、第二介电层312a的材料、及第三介电层314a的材料。举例来说，第四介电层316a的材料可包括例如环氧树脂或酚醛树脂等模塑化合物材料。在一些实施例中，第四介电层316a还可包括填充物(filler)。在一些实施例中，第四介电层316a的材料可包括聚酰亚胺、环氧树脂、丙烯酸树脂、酚醛树脂、苯并环丁烯(BCB)、聚苯并恶唑(PBO)或任何其他适合的聚合物系介电材料。在一些实施例中，第四介电层316a的杨氏模量高于第一介电层310a的杨氏模量、第二介电层312a的杨氏模量、及第三介电层314a的杨氏模量。举例来说，第四介电层316a的杨氏模量可介于0.5GPa至150GPa的范围内。
参照图2F，在一些实施例中，在第四介电层316a上形成覆盖开口O316a的晶种层410。如图2F中所示，以覆盖开口O316a的轮廓的共形方式形成晶种层410。也就是说，晶种层410延伸到开口O316a中从而覆盖开口O316a的底表面及侧壁。晶种层410可通过例如溅镀工艺(sputtering process)、物理气相沉积(physical vapor deposition，PVD)工艺等来形成。在一些实施例中，晶种层410可包含例如铜、钛铜合金、或其他适合的材料选择。
参照图2G，在晶种层410上形成光刻胶图案层PR。在一些实施例中，光刻胶图案层PR暴露出位于开口O316a中的晶种层410且暴露出晶种层410的位于第四介电层316a上及开口O316a周围的至少一部分。
参照图2H，在一些实施例中，在开口O316a内的晶种层410上形成导电柱420。在一些实施例中，将导电材料(图中未示出)沉积到被暴露出的晶种层410上以形成导电柱420。随后，将焊料材料430沉积到导电柱420上。导电柱420及焊料材料430位于光刻胶图案层PR的开口内。换句话说，导电柱420及焊料材料430是使用光刻胶图案层PR作为掩模而形成。在一些实施例中，导电材料及焊料材料430可通过镀覆工艺来形成。所述镀覆工艺为例如电镀、无电镀覆(electroless-plating)、浸镀(immersion plating)等。在一些实施例中，导电材料包括例如铜、铜合金等。
参照图2I，移除光刻胶图案层PR且暴露出晶种层410的未被导电柱420及焊料材料430覆盖的部分。可通过例如刻蚀工艺、灰化工艺(ashing process)、或其他适合的移除工艺来移除/剥除光刻胶图案层PR。
参照图2J，移除未被导电柱420及焊料材料430覆盖的晶种层410，以得到夹置在导电柱420与第四介电层316a之间及导电柱420与第三导电图案324a之间的晶种层410a。可通过刻蚀工艺来移除晶种层410的被暴露出的部分。在一些实施例中，导电柱420的材料可不同于晶种层410的材料，因而可通过选择性刻蚀(selective etching)来移除晶种层410的被暴露出的部分。在一些实施例中，可将导电柱420划分成第一部分P1及第二部分P2。第一部分P1嵌置在第四介电层316a中，且第二部分P2位于第四介电层316a上。如图2J中所示，晶种层410a位于第二部分P2与第四介电层316a之间、第一部分P1与第四介电层316a之间、及第一部分P1与第三导电图案324a之间。参照图2K，对焊料材料430执行回焊工艺(reflowprocess)以使焊料材料430转变成导电凸块500。如图2K中所示，在回焊工艺之后导电凸块500呈现半球体形状。然而，本发明实施例并非仅限于此。在一些替代性实施例中，在回焊工艺之后导电凸块500可呈其他形状。
图3A至图3J是以区R为着重点示出根据本发明一些替代性实施例的示例性封装的制造方法的各工艺的示意性放大剖视图。图3A至图3J示出用于在包封体200a及管芯100a上形成与图1C至图1D中所绘示结构相似的重布线结构300、导电柱420、及导电凸块500的详细工艺步骤。参照图3A，在管芯100a及包封体200a上依序形成第一介电层310a、第一导电图案320a、第二介电层312a、第二导电图案322a、第三介电层314a、及第三导电图案324a。用于形成这些元件的工艺步骤与图2A至图2C中所示的工艺步骤相似，因而本文中不再对其予以赘述。
参照图3B，在第三介电层314a及第三导电图案324a上形成第一晶种层410。第一晶种层410可通过例如溅镀工艺、物理气相沉积(PVD)工艺等来形成。在一些实施例中，第一晶种层410可包含例如铜、钛铜合金、或其他适合的材料选择。
参照图3C，在第一晶种层410上形成第一光刻胶图案层PR1。在一些实施例中，第一光刻胶图案层PR1暴露出第一晶种层410的位于第三导电图案324a上的至少一部分。
参照图3D，使用第一光刻胶图案层PR1作为掩模将第一导电材料420a沉积到被暴露出的第一晶种层410上。在一些实施例中，第一导电材料420a可通过镀覆工艺来形成。所述镀覆工艺为例如电镀、无电镀覆、浸镀等。在一些实施例中，第一导电材料420a包括例如铜、铜合金等。
参照图3D及图3E，移除第一光刻胶图案层PR1且暴露出第一晶种层410的未被第一导电材料420a覆盖的部分。可通过例如刻蚀工艺、灰化工艺、或其他适合的移除工艺来移除/剥除第一光刻胶图案层PR1。随后，移除未被第一导电材料420a覆盖的第一晶种层410，以得到夹置在第一导电材料420a与第三导电图案324a之间的第一晶种层410a。可通过刻蚀工艺来移除第一晶种层410的被暴露出的部分。
参照图3F，在第一晶种层410a及第一导电材料420a周围形成第四介电层316a。与图2A至图2K所示的实施例相似，在一些实施例中，第四介电层316a的材料不同于第一介电层310a的材料、第二介电层312a的材料、及第三介电层314a的材料。举例来说，第四介电层316a的杨氏模量高于第一介电层310a的杨氏模量、第二介电层312a的杨氏模量、及第三介电层314a的杨氏模量。在一些实施例中，基于较高的杨氏模量，可将重布线结构300的第四介电层316a称作抗应力层。
参照图3G，可在第四介电层316a及第一导电材料420a上形成第二晶种层412。随后，在第二晶种层412上形成第二光刻胶图案层PR2。在一些实施例中，第二光刻胶图案层PR2暴露出第二晶种层412的位于第一导电材料420a上的至少一部分。第二晶种层412可相似于第一晶种层410且第二光刻胶图案层PR2可相似于第一光刻胶图案层PR1，因而本文中不再对其予以赘述。
参照图3H，使用第二光刻胶图案层PR2作为掩模将第二导电材料420b及焊料材料430沉积到被暴露出的第二晶种层412上。第二导电材料420b可相似于第一导电材料410b，因而本文中不再对其予以赘述。
参照图3H及图3I，移除第二光刻胶图案层PR2且暴露出第二晶种层412的未被第二导电材料420b及焊料材料430覆盖的部分。可通过例如刻蚀工艺、灰化工艺、或其他适合的移除工艺来移除/剥除第二光刻胶图案层PR2。随后，移除未被第二导电材料420b及焊料材料430覆盖的第二晶种层412，以得到夹置在第二导电材料420b与第一导电材料420a之间及第二导电材料420b与第四介电层316a之间的第二晶种层(附加晶种层)412a。可通过刻蚀工艺来移除第二晶种层412的被暴露出的部分。参照图3I，第一导电材料420a及第二导电材料420b构成导电柱420。在一些实施例中，可将第一导电材料420a称作导电柱420的嵌置在第四介电层316a中的第一部分P1。另一方面，可将第二导电材料420b称作导电柱420的位于第四介电层316a上的第二部分P2。第一晶种层410a位于第一部分P1与第三导电图案324a之间。第二晶种层412a位于第一部分P1与第二部分P2之间及第四介电层316a与第二部分P2之间。参照图3J，对焊料材料430执行回焊工艺以使焊料材料430转变成导电凸块500。
图4A至图4J是以图1C中的区R为着重点示出根据本发明一些替代性实施例的示例性封装的制造方法的各工艺的示意性放大剖视图。图4A至图4J示出用于在包封体200a及管芯100a上形成与图1C至图1D中所绘示结构相似的重布线结构300、缓冲层600a、导电柱420、及导电凸块500的详细工艺步骤。参照图4A，在管芯100a及包封体200a上依序形成第一介电层310a、第一导电图案320a、第二介电层312a、第二导电图案322a、第三介电层314a、及第三导电图案324a。用于形成这些元件的工艺步骤与图2A至图2C中所示工艺步骤相似，因而本文中不再对其予以赘述。
参照图4B及图4C，在第三介电层314a及第三导电图案324a上形成第四介电层316a。可首先在第三介电层314a及第三导电图案324a上形成介电材料层316。随后，将介电材料层316图案化以形成具有多个开口O316a的第四介电层316a。开口O316a暴露出位于第四介电层316a下的第三导电图案324a的至少一部分。在一些实施例中，可通过光刻工艺及刻蚀工艺来将介电材料层316图案化。在一些实施例中，第四介电层316a的材料相同于第一介电层310a的材料、第二介电层312a的材料、及第三介电层314a的材料。在一些实施例中，第四介电层316a被称作在与管芯100a的顶表面垂直的方向上距管芯100a最远的介电层。相似地，第三导电图案324a被称作在与管芯100a的顶表面垂直的方向上距管芯100a最远的导电图案。在一些实施例中，第一介电层310a、第二介电层312a、第三介电层314a、第四介电层316a、第一导电图案320a、第二导电图案322a、及第三导电图案324a构成重布线结构300。
参照图4D，在第四介电层316a及第三导电图案324a上形成缓冲层600。在一些实施例中，缓冲层600的材料不同于第一介电层310a的材料、第二介电层312a的材料、第三介电层314a的材料、及第四介电层316a的材料。举例来说，缓冲层600的材料可包括例如环氧树脂或酚醛树脂等模塑化合物材料。在一些实施例中，缓冲层600还可包括填充物。在一些实施例中，缓冲层600的材料可包括聚酰亚胺、环氧树脂、丙烯酸树脂、酚醛树脂、苯并环丁烯(BCB)、聚苯并恶唑(PBO)或任何其他适合的聚合物系介电材料。在一些实施例中，缓冲层600的杨氏模量高于第一介电层310a的杨氏模量、第二介电层312a的杨氏模量、第三介电层314a的杨氏模量、及第四介电层316a的杨氏模量。举例来说，缓冲层600的杨氏模量介于0.5GPa至150GPa的范围内。另一方面，第一介电层310a的杨氏模量、第二介电层312a的杨氏模量、第三介电层314a的杨氏模量、及第四介电层316a的杨氏模量介于0.1GPa至100GPa的范围内。在特定实施例中，缓冲层600的杨氏模量对第一介电层310a、第二介电层312a、第三介电层314a、或第四介电层316a的杨氏模量的比率介于1.05至100的范围内。当杨氏模量的比率低于1.05时，缓冲层600不能够承受住从导电柱420所产生的应力，而使重布线结构300中的导电图案变形。另一方面，当杨氏模量的比率超过100时，缓冲层600将呈现与纯硅的硬度相似的硬度，由此增大加工难度。在一些实施例中，缓冲层600的厚度大于第一介电层310a的厚度、第二介电层312a的厚度、第三介电层314a的厚度、或第四介电层316a的厚度。在一些实施例中，较高的杨氏模量使得缓冲层600能够减轻或阻挡从导电柱420施加到下伏重布线结构300的应力，从而保护重布线结构300中的导电图案不因在装配工艺及/或热工艺期间产生的应力而损坏。换句话说，具有较高杨氏模量的缓冲层600有助于减轻重布线结构300中的精细线变形问题。因此，在一些实施例中，可将缓冲层600称作抗应力层。
参照图4E，将缓冲层600图案化以形成具有多个开口O600a的缓冲层600a。开口O600a大于开口O316a，以使得开口O600a暴露出第四介电层316a的开口O316a及第四介电层316a的至少一部分。
参照图4F，在一些实施例中，在缓冲层600a上形成覆盖开口O316a及开口O600a的晶种层410。如图4F中所示，以覆盖开口O316a及开口O600a的轮廓的共形方式形成晶种层410。也就是说，晶种层410延伸到开口O316a及开口O600a中从而覆盖开口O316a及开口O600a的底表面及侧壁。晶种层410可通过例如溅镀工艺、物理气相沉积(PVD)工艺等来形成。在一些实施例中，晶种层410可包含例如铜、钛铜合金、或其他适合的材料选择。
参照图4G，在晶种层410上形成光刻胶图案层PR。在一些实施例中，光刻胶图案层PR暴露出位于开口O316a及开口O600a中的晶种层410。光刻胶图案层PR还暴露出晶种层410的位于缓冲层600上及开口O600a周围的至少一部分。
参照图4H，在一些实施例中，在开口O316a及开口O600a内的晶种层410上形成导电柱420。在一些实施例中，将导电材料(图中未示出)沉积到被暴露出的晶种层410上以形成导电柱420。随后，将焊料材料430沉积到导电柱420上。在一些实施例中，导电材料及焊料材料430可通过镀覆工艺来形成。所述镀覆工艺为例如电镀、无电镀覆、浸镀等。在一些实施例中，导电材料包括例如铜、铜合金等。
参照图4H及图4I，移除光刻胶图案层PR且暴露出晶种层410的未被导电柱420及焊料材料430覆盖的部分。可通过例如刻蚀工艺、灰化工艺、或其他适合的移除工艺来移除/剥除光刻胶图案层PR。随后，移除未被导电柱420及焊料材料430覆盖的晶种层410，以得到夹置在导电柱420与缓冲层600a之间、导电柱420与第四介电层316a之间、及导电柱420与第三导电图案324a之间的晶种层410a。可通过刻蚀工艺来移除晶种层410的被暴露出的部分。参照图4J，对焊料材料430执行回焊工艺以使焊料材料430转变成导电凸块500。
图5A是以区R为着重点示出根据本发明一些替代性实施例的示例性封装的示意性放大剖视图。图5B示出图5A中的缓冲层600a及导电柱420的示意性俯视图。除缓冲层600a的位置或覆盖率(coverage)以外，图5A中所示结构相似于图4J中所示结构。换句话说，可通过与图4A至图4J中所示的工艺步骤相似的工艺步骤来获得图5A中所示的结构，因而本文中不再对其予以赘述。在一些实施例中，可执行移除缓冲层600a的位于第四介电层316a上的至少一部分的额外步骤，以获得环绕导电柱420的环形缓冲层600a。参照图5A及图5B，出于说明目的，将导电柱420绘示为圆形导电柱且将环绕每一导电柱420的环形缓冲层600a绘示为圆环形炸面圈结构以作实例，但并非旨在限制本发明实施例的范围。在一些实施例中，每一导电柱420均具有为W1的最大直径。另一方面，环形缓冲层600a的边缘与导电柱420的侧壁之间具有为W2的距离。在一些实施例中，W2对W1(W2/W1)的比率介于0.01至0.6的范围内。尽管图5B中导电柱420被绘示为圆柱体且环绕所述柱的缓冲层具有对应形状，然而可采用各种形状及不同的兼容形状，且本发明实施例并非仅限于此。在一些替代性实施例中，导电柱420可为椭圆柱体或甚至为正方形柱体或多边形柱体。此外，尽管图5A示出环形缓冲层600a的外侧壁为直的，然而本发明实施例并非仅限于此。在一些替代性实施例中，环形缓冲层600a的外侧壁可倾斜以进一步增强缓冲层600a的强度。
图6A至图6I是以图1C中的区R为着重点示出根据本发明一些替代性实施例的示例性封装的制造方法的各工艺的示意性放大剖视图。图6A至图6I示出用于在包封体200a及管芯100a上形成与图1C至图1D中所绘示结构相似的重布线结构300、缓冲层600a、导电柱420、及导电凸块500的详细工艺步骤。参照图6A至图6C，所示出的工艺步骤相似于图4A至图4C中的工艺步骤，因而本文中不再对其予以赘述。
参照图6D，在第四介电层316a及第三导电图案324a上形成缓冲层600a。在一些实施例中，缓冲层600a延伸到开口O316a中从而覆盖开口O316a的侧壁SW316a。缓冲层600a暴露出开口O316a的底表面的至少一部分。换句话说，缓冲层600a暴露出第三导电图案324a的至少一部分。在一些实施例中，缓冲层600的材料不同于第一介电层310a的材料、第二介电层312a的材料、第三介电层314a的材料、及第四介电层316a的材料。举例来说，缓冲层600a的材料可包括例如环氧树脂或酚醛树脂等模塑化合物材料。在一些实施例中，缓冲层600a还可包括填充物。在一些实施例中，缓冲层600a的材料可包括聚酰亚胺、环氧树脂、丙烯酸树脂、酚醛树脂、苯并环丁烯(BCB)、聚苯并恶唑(PBO)或任何其他适合的聚合物系介电材料。在一些实施例中，缓冲层600a的杨氏模量高于第一介电层310a的杨氏模量、第二介电层312a的杨氏模量、第三介电层314a的杨氏模量、及第四介电层316a的杨氏模量。举例来说，缓冲层600a的杨氏模量介于0.5GPa至150GPa的范围内。另一方面，第一介电层310a的杨氏模量、第二介电层312a的杨氏模量、第三介电层314a的杨氏模量、及第四介电层316a的杨氏模量介于0.1GPa至100GPa的范围内。在特定实施例中，缓冲层600a的杨氏模量对第一介电层310a、第二介电层312a、第三介电层314a、或第四介电层316a的杨氏模量的比率介于1.05至100的范围内。当杨氏模量的比率低于1.05时，缓冲层600a不能够承受住从导电柱420所产生的应力，而使重布线结构300中的导电图案变形。另一方面，当杨氏模量的比率超过100时，缓冲层600a将呈现与纯硅相似的硬度，由此增大加工难度。在一些实施例中，缓冲层600a的厚度大于第一介电层310a的厚度、第二介电层312a的厚度、第三介电层314a的厚度、或第四介电层316a的厚度。在一些实施例中，较高的杨氏模量使得缓冲层600a能够减轻或阻挡从导电柱420施加到下伏重布线结构300的应力，从而保护重布线结构300中的导电图案不因在装配工艺及/或热工艺期间产生的应力而损坏。换句话说，具有较高杨氏模量的缓冲层600a有助于减轻重布线结构300中的精细线变形问题。因此，在一些实施例中，可将缓冲层600a称作抗应力层。
参照图6E，在一些实施例中，在缓冲层600a上及被暴露出的第三导电图案324a上形成晶种层410。如图6E中所示，以共形方式形成晶种层410。也就是说，晶种层410延伸到开口O316a中以覆盖位于开口O316a中的缓冲层600a及覆盖被暴露出的第三导电图案324a。晶种层410可通过例如溅镀工艺、物理气相沉积(PVD)工艺等来形成。在一些实施例中，晶种层410可包含例如铜、钛铜合金、或其他适合的材料选择。
参照图6F，在晶种层410上形成光刻胶图案层PR。在一些实施例中，光刻胶图案层PR暴露出位于开口O316a中的晶种层410。光刻胶图案层PR还暴露出晶种层410的位于缓冲层600a上的至少一部分。在一些实施例中，光刻胶图案层PR可包含感光性树脂。
参照图6G，在一些实施例中，在缓冲层600a上的晶种层410上形成导电柱420。在一些实施例中，将导电材料(图中未示出)沉积到被暴露出的晶种层410上以形成导电柱420。导电柱420接触位于第三导电图案324a上的晶种层410，以实现与重布线结构300的电连接。随后，将焊料材料430沉积到导电柱420上。在一些实施例中，导电材料及焊料材料430可通过镀覆工艺来形成。所述镀覆工艺为例如电镀、无电镀覆、浸镀等。在一些实施例中，导电材料包括例如铜、铜合金等。
参照图6G及图6H，移除光刻胶图案层PR且暴露出晶种层410的未被导电柱420及焊料材料430覆盖的部分。可通过例如刻蚀工艺、灰化工艺、或其他适合的移除工艺来移除/剥除光刻胶图案层PR。随后，移除未被导电柱420及焊料材料430覆盖的晶种层410，以得到夹置在导电柱420与缓冲层600a之间及导电柱420与第三导电图案324a之间的晶种层410a。可通过刻蚀工艺来移除晶种层410的被暴露出的部分。参照图6I，对焊料材料430执行回焊工艺以使焊料材料430转变成导电凸块500。
图7A是以区R为着重点示出根据本发明一些替代性实施例的示例性封装的示意性放大剖视图。图7B示出图7A中的缓冲层600a及导电柱420的示意性俯视图。除缓冲层600a的位置或覆盖率以外，图7A中所示结构相似于图6I中所示结构。换句话说，可通过与图6A至图6I中所示的工艺步骤相似的工艺步骤来获得图7A中所示的结构，因而本文中不再对其予以赘述。在一些实施例中，可执行移除缓冲层600a的位于第四介电层316a上的至少一部分的额外步骤，以获得环绕导电柱420的环形缓冲层600a。参照图7A及图7B，出于说明目的，将导电柱420绘示为圆形导电柱且将环绕每一导电柱420的环形缓冲层600a绘示为圆环形炸面圈结构以作实例，但并非旨在限制本发明实施例的范围。在一些实施例中，每一导电柱420均具有为W1的最大直径。另一方面，环形缓冲层600a的边缘与导电柱420的侧壁之间具有为W2的距离。在一些实施例中，W2对W1(W2/W1)的比率介于0.01至0.6的范围内。尽管图7B中导电柱420被绘示为圆柱体且环绕所述柱的缓冲层具有对应形状，然而可采用各种形状及不同的兼容形状，且本发明实施例并非仅限于此。在一些替代性实施例中，导电柱420可为椭圆柱体或甚至为正方形柱体或多边形柱体。此外，尽管图7A说明环形缓冲层600a的外侧壁为直的，然而本发明实施例并非仅限于此。在一些替代性实施例中，环形缓冲层600a的外侧壁可倾斜以进一步增强缓冲层600a的强度。
图8示出包括图1F中的集成扇出型封装10的堆叠封装结构的示意图。参照图8，可在衬底20上堆叠集成扇出型封装10。在一些实施例中，衬底20可为上面形成有无源装置或微机电系统(micro-electro-mechanical system，MEMS)装置的半导体衬底。在一些替代性实施例中，衬底20可为插板(interposer)。集成扇出型封装10可通过导电柱420及导电凸块500与衬底20电连接。在一些实施例中，上面形成有集成扇出型封装10的衬底20可进一步设置在印刷电路板30上以形成半导体装置。集成扇出型封装10可通过衬底20电连接到印刷电路板30。
根据本发明的一些实施例，一种集成扇出型封装包括管芯、包封体、重布线结构、多个导电柱、晶种层、及多个导电凸块。所述包封体包封所述管芯。所述重布线结构位于所述管芯及所述包封体上。所述重布线结构与所述管芯电连接且包括依序堆叠的多个介电层以及夹置在所述介电层之间的多个导电图案。距所述管芯最远的所述介电层的杨氏模量高于所述介电层中其余介电层中的每一者的杨氏模量。所述导电图案彼此电连接。所述导电柱设置在所述重布线结构上且与所述重布线结构电连接。所述晶种层位于所述导电柱与所述重布线结构之间。所述导电凸块设置在所述导电柱上。
根据本发明的一些实施例，距所述管芯最远的所述介电层包含模塑化合物材料。
根据本发明的一些实施例，所述导电柱中的每一者包括第一部分及第二部分，所述第一部分嵌置在距所述管芯最远的所述介电层中，所述第二部分位于距所述管芯最远的所述介电层上。
根据本发明的一些实施例，所述集成扇出型封装进一步包括位于所述第一部分与所述第二部分之间以及位于距所述管芯最远的所述介电层与所述第二部分之间的附加晶种层。
根据本发明的一些实施例，所述晶种层位于所述第二部分与距所述管芯最远的所述介电层之间、所述第一部分与距所述管芯最远的所述介电层之间、以及所述第一部分与距所述管芯最远的所述导电图案之间。
根据本发明的一些实施例，距所述管芯最远的所述介电层的所述杨氏模量对所述介电层中所述其余介电层的所述杨氏模量的比率介于1.05至100的范围内。
根据本发明的一些替代性实施例，一种集成扇出型封装包括管芯、包封体、重布线结构、缓冲层、多个导电柱、晶种层、及多个导电凸块。所述包封体包封所述管芯。所述重布线结构位于所述管芯及所述包封体上。所述重布线结构与所述管芯电连接且包括依序堆叠的多个介电层以及夹置在所述介电层之间的多个导电图案。所述缓冲层位于所述重布线结构上。所述缓冲层的杨氏模量高于所述重布线结构的所述介电层中的每一者的杨氏模量。所述导电柱设置在所述缓冲层上且与所述重布线结构电连接。所述晶种层位于所述导电柱与所述缓冲层之间以及所述导电柱与所述重布线结构之间。所述导电凸块设置在所述导电柱上。
根据本发明的一些实施例，距所述管芯最远的所述介电层具有多个第一开口，所述多个第一开口暴露出距所述管芯最远的所述导电图案的至少一部分，所述缓冲层具有多个第二开口，所述多个第二开口暴露出所述多个第一开口，且所述多个第二开口大于所述多个第一开口。
根据本发明的一些实施例，所述缓冲层是环绕所述多个导电柱的环形结构且暴露出距所述管芯最远的所述介电层的至少一部分。
根据本发明的一些实施例，所述环形缓冲层的边缘与所述多个导电柱的侧壁之间的距离对所述多个导电柱的最大直径的比率介于0.01至0.6的范围内。
根据本发明的一些实施例，距所述管芯最远的所述介电层具有多个第一开口，所述多个第一开口暴露出距所述管芯最远的所述导电图案的至少一部分，且所述缓冲层延伸到所述多个第一开口中以覆盖所述多个第一开口的侧壁。
根据本发明的一些实施例，所述多个导电柱接触位于距所述管芯最远的所述导电图案上的所述晶种层。
根据本发明的一些实施例，所述缓冲层是环绕所述多个导电柱的环形结构且暴露出距所述管芯最远的所述介电层的至少一部分。
根据本发明的一些实施例，所述缓冲层的边缘与所述多个导电柱的侧壁之间的距离对所述多个导电柱的最大直径的比率介于0.01至0.6的范围内。
根据本发明的一些实施例，一种集成扇出型封装的制造方法至少包括以下步骤。提供管芯。以包封体包封所述管芯。在所述管芯及所述包封体上形成多个介电层。形成多个导电图案。所述导电图案的至少一部分夹置在所述介电层之间。所述导电图案彼此电连接。在所述介电层上形成抗应力层。所述抗应力层的杨氏模量高于所述介电层中的每一者的杨氏模量。在所述抗应力层上形成多个导电柱。在所述导电柱上形成多个导电凸块。
根据本发明的一些实施例，所述形成所述多个导电柱的步骤至少包括以下步骤。在所述抗应力层中形成多个开口，以暴露出距所述管芯最远的所述导电图案。在所述多个开口中及所述抗应力层上形成晶种层。在所述晶种层上形成光刻胶图案层，其中所述光刻胶图案层暴露出位于所述多个开口中的所述晶种层以及位于所述抗应力层上的所述晶种层的至少一部分。使用所述光刻胶图案层作为掩模在所述晶种层上形成导电材料。移除所述光刻胶图案层。移除被所述导电材料暴露出的所述晶种层。
根据本发明的一些实施例，所述形成所述多个导电柱的步骤以及所述形成所述抗应力层的步骤至少包括以下步骤。在距所述管芯最远的所述介电层上以及在距所述管芯最远的所述导电图案上形成第一晶种层。在所述第一晶种层上形成第一光刻胶图案层，其中所述第一光刻胶图案层暴露出位于距所述管芯最远的所述导电图案上的所述第一晶种层的至少一部分。使用所述第一光刻胶图案层作为掩模在所述第一晶种层上形成第一导电材料。移除所述第一光刻胶图案层。移除被所述第一导电材料暴露出的所述第一晶种层。形成围绕所述第一晶种层及所述第一导电材料的所述抗应力层。在所述第一导电材料及所述抗应力层上形成第二晶种层。在所述第二晶种层上形成第二光刻胶图案层，其中所述第二光刻胶图案层暴露出位于所述第一导电材料上的所述第二晶种层的至少一部分。使用所述第二光刻胶图案层作为掩模在所述第二晶种层上形成第二导电材料。移除所述第二光刻胶图案层。移除被所述第二导电材料暴露出的所述第二晶种层。
根据本发明的一些实施例，所述形成所述多个导电柱的步骤至少包括以下步骤。在距所述管芯最远的所述介电层中形成多个第一开口，其中所述多个第一开口暴露出距所述管芯最远的所述导电图案的至少一部分。在所述抗应力层中形成多个第二开口，其中所述多个第二开口暴露出所述多个第一开口及距所述管芯最远的所述介电层的至少一部分。在所述多个第一开口及所述多个第二开口中以及所述抗应力层上形成晶种层。在所述晶种层上形成光刻胶图案层，其中所述光刻胶图案层暴露出位于所述多个第一开口及所述多个第二开口中的所述晶种层且暴露出位于所述抗应力层上的所述晶种层的至少一部分。使用所述光刻胶图案层作为掩模在所述晶种层上形成导电材料。移除所述光刻胶图案层。移除被所述导电材料暴露出的所述晶种层。
根据本发明的一些实施例，所述形成所述多个导电柱的步骤以及所述形成所述抗应力层的步骤至少包括以下步骤。在距所述管芯最远的所述介电层中形成多个第一开口，其中所述多个第一开口暴露出距所述管芯最远的所述导电图案的至少一部分。在距所述管芯最远的所述介电层上以及在所述多个第一开口中形成所述抗应力层，以使得所述抗应力层覆盖所述多个第一开口的侧壁。在所述抗应力层上及距所述管芯最远的被暴露出的所述导电图案上形成晶种层。在所述晶种层上形成光刻胶图案层，其中所述光刻胶图案层暴露出位于所述多个第一开口中的所述晶种层且暴露出位于所述抗应力层上的所述晶种层的至少一部分。使用所述光刻胶图案层作为掩模在所述晶种层上形成导电材料。移除所述光刻胶图案层。移除被所述导电材料暴露出的所述晶种层。
根据本发明的一些实施例，所述集成扇出型封装的制造方法进一步包括移除所述抗应力层的至少一部分，以使得所述抗应力层是环绕所述多个导电柱的环形结构。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本发明的各个方面。所属领域中的技术人员应知，其可容易地使用本发明作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的及/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本发明的精神及范围，而且他们可在不背离本发明的精神及范围的条件下对其作出各种改变、代替、及变更。

Claims (1)

1.一种集成扇出型封装，其特征在于，包括：
管芯；
包封体，包封所述管芯；
重布线结构，位于所述管芯及所述包封体上，其中所述重布线结构与所述管芯电连接且包括：
依序堆叠的多个介电层，其中距所述管芯最远的所述介电层的杨氏模量高于所述介电层中其余介电层中的每一者的杨氏模量；以及
多个导电图案，夹置在所述多个介电层之间，其中所述多个导电图案彼此电连接；
多个导电柱，设置在所述重布线结构上且与所述重布线结构电连接；
晶种层，位于所述多个导电柱与所述重布线结构之间；以及
多个导电凸块，设置在所述多个导电柱上。
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US20200328173A1 (en) 2020-10-15
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