KR20220031414A - 반도체 패키지 - Google Patents

반도체 패키지 Download PDF

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Publication number
KR20220031414A
KR20220031414A KR1020200113292A KR20200113292A KR20220031414A KR 20220031414 A KR20220031414 A KR 20220031414A KR 1020200113292 A KR1020200113292 A KR 1020200113292A KR 20200113292 A KR20200113292 A KR 20200113292A KR 20220031414 A KR20220031414 A KR 20220031414A
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KR
South Korea
Prior art keywords
redistribution
insulating layer
insulating
semiconductor chip
layer
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KR1020200113292A
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English (en)
Inventor
정태성
이두환
김홍원
최정곤
Original Assignee
삼성전자주식회사
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Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1020200113292A priority Critical patent/KR20220031414A/ko
Priority to US17/241,875 priority patent/US11676915B2/en
Publication of KR20220031414A publication Critical patent/KR20220031414A/ko

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    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking

Abstract

본 발명의 일 실시예는, 제1 절연층과, 상기 제1 절연층 상의 적어도 한층 이상의 제2 절연층과, 복수의 재배선층들을 포함하는 재배선 기판, 제1 절연층은 제1 감광성 수지를 포함하되, 상기 제1 감광성 수지는 신율(elongation)이 60% 이상 및 인성(toughness)이 70mJ/m2 이상이고, 적어도 한층 이상의 제2 절연층은 제2 감광성 수지를 포함하되, 상기 제2 감광성 수지는 신율이 10% 내지 40% 범위 및 인성이 10mJ/m2 내지 40mJ/m2 범위인 반도체 패키지를 제공한다.

Description

반도체 패키지{SEMICONDUCTOR PACKAGE}
본 발명은 반도체 패키지에 관한 것이다.
반도체 패키지는 솔더 볼 등의 연결 범프를 통해서 기판(예, 메인 보드 등)에 실장된다. 반도체 패키지의 신뢰성은 연결 범프와 반도체 패키지의 접속 상태에 영향을 받는다. 반도체 패키지의 신뢰성을 보장하기 위해서, 연결 범프 주변의 절연 물질층에서 발생하는 크랙을 방지할 수 있는 기술이 요구된다.
본 발명이 해결하고자 하는 과제 중 하나는, 신뢰성이 향상된 반도체 패키지를 제공하는 것이다.
전술한 과제의 해결 수단으로서, 본 발명의 일 실시예는, 제1 절연층과, 상기 제1 절연층 상의 적어도 한층 이상의 제2 절연층과, 각각의 상기 제1 절연층 및 상기 적어도 한층 이상의 제2 절연층 상에 또는 내에 배치되며 서로 전기적으로 연결된 복수의 재배선층들을 포함하는 재배선 기판, 상기 재배선 기판 상에 배치되며, 상기 복수의 재배선층들과 전기적으로 연결된 접속 패드를 포함하는 반도체 칩, 상기 재배선 기판 상에 배치되며, 상기 반도체 칩을 덮는 봉합재, 상기 반도체 칩과 반대의 상기 재배선 기판 상에 배치되며, 상기 복수의 재배선층들과 전기적으로 연결된 제1 연결 범프 및 상기 재배선 기판과 상기 반도체 칩 사이에 배치되며, 상기 복수의 재배선층들과 상기 접속 패드를 전기적으로 연결하는 제2 연결 범프를 포함하고, 상기 제1 절연층은 제1 감광성 수지를 포함하되, 상기 제1 감광성 수지는 신율(elongation)이 60% 이상 및 인성(toughness)이 70mJ/m2 이상이고, 상기 적어도 한층 이상의 제2 절연층은 제2 감광성 수지를 포함하되, 상기 제2 감광성 수지는 신율이 10% 내지 40% 범위 및 인성이 10mJ/m2 내지 40mJ/m2 범위인 반도체 패키지를 제공한다.
또한, 수직 방향으로 적층된 제1 절연층 및 제2 절연층과, 상기 제1 절연층 및 상기 제2 절연층 내에 배치된 재배선층을 포함하는 재배선 기판, 접속 패드가 배치된 제1 면을 가지며, 상기 제1 면이 상기 제2 절연층을 마주하도록 상기 재배선 기판 상에 배치된 반도체 칩, 및 상기 재배선 기판 및 상기 반도체 칩을 덮는 봉합재를 포함하고, 상기 제1 절연층은 제1 절연성 수지를 포함하고, 상기 제2 절연층은 제2 절연성 수지를 포함하고, 상기 제1 절연성 수지는 신율 및 인성이 상기 제2 절연성 수지 보다 큰 반도체 패키지를 제공한다.
또한, 적어도 한층 이상의 제1 절연층, 상기 적어도 한층 이상의 제1 절연층 상에 적층된 적어도 한층 이상의 제2 절연층과, 상기 적어도 한층 이상의 제1 및 제2 절연층 내에 배치된 복수의 재배선층들을 포함하는 재배선 기판, 및 상기 재배선 기판 상에 배치되며, 상기 복수의 재배선층들에 전기적으로 연결된 제1 접속 패드를 포함하는 제1 반도체 칩을 포함하고, 상기 적어도 한층 이상의 제1 절연층은 제1 절연성 수지를 포함하고, 상기 적어도 한층 이상의 제2 절연층은 제2 절연성 수지를 포함하고, 상기 제1 절연성 수지는 신율이 60% 이상 및 인성이 70mJ/m2 이상인 반도체 패키지를 제공한다.
본 발명의 실시예들에 따르면, 패키지의 최외측 절연층에 특정 물성을 갖는 절연성 수지를 도입함으로써, 신뢰성이 향상된 반도체 패키지를 제공할 수 있다.
도 1a은 본 발명의 일 실시예에 따른 반도체 패키지를 나타낸 단면도이다.
도 1b은 도 1a의 I-I' 절단면을 나타낸 단면도이다.
도 2a 내지 2d는 도 1b의 반도체 패키지의 제조 방법을 개략적으로 나타낸 단면도들이다.
도 3a 및 3b는 각각 본 발명의 일 실시예에 따른 반도체 패키지를 나타낸 단면도이다.
도 4는 본 발명의 일 실시예에 따른 반도체 패키지를 나타낸 단면도이다.
도 5는 도 4의 반도체 패키지의 변형예를 나타낸 부분 확대도이다.
도 6a 내지 6e는 도 4의 반도체 패키지의 제조 방법을 개략적으로 나타낸 단면도들이다.
도 7은 본 발명의 일 실시예에 따른 반도체 패키지를 나타낸 단면도이다.
도 8은 본 발명의 일 실시예에 따른 반도체 패키지를 나타낸 단면도이다.
도 9는 본 발명의 일 실시예에 따른 반도체 패키지를 나타낸 단면도이다.
도 10는 본 발명의 일 실시예에 따른 반도체 패키지를 나타낸 단면도이다.
도 11은 최외측 절연층의 물성에 따른 신뢰성 테스트 결과를 나타낸 그래프이다.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예들을 다음과 같이 설명한다.
도 1a은 본 발명의 일 실시예에 따른 반도체 패키지(100A)를 나타낸 단면도이고, 도 1b은 도 1a의 I-I' 절단면을 나타낸 단면도이다.
도 1a 및 1b를 참조하면, 반도체 패키지(100A)는 재배선 기판(110), 반도체 칩(120), 및 봉합재(130)를 포함할 수 있다. 반도체 패키지(100A)는 제1 및 제2 연결 범프들(141, 142), 언더필 수지(143)를 더 포함할 수 있다.
재배선 기판(110)은 재배선 기판(110)은 반도체 칩(120)이 실장되는 지지 기판으로서, 절연층(111), 재배선층(112), 및 재배선 비아(113)를 포함할 수 있다.
절연층(111)은 수직 방향(Z 방향)으로 적층된 복수의 절연층들(111)을 포함할 수 있다. 예를 들어, 절연층(111)은 제1 절연층(111a) 및 제1 절연층(111a) 상에 적층된 적어도 한층 이상의 제2 절연층(111b)을 포함할 수 있다. 절연층(111)은 절연성 수지를 포함할 수 있다. 절연성 수지는 에폭시 수지와 같은 열경화성 수지, 폴리이미드와 같은 열가소성 수지, 또는 이들 수지에 무기필러 또는/및 유리섬유(Glass Fiber, Glass Cloth, Glass Fabric)가 함침된 수지, 예를 들어, 프리프레그(prepreg), ABF(Ajinomoto Build-up Film), FR-4, BT(Bismaleimide Triazine)를 포함할 수 있다. 절연층(111)은 PID(Photoimageable Dielectric) 수지와 같은 감광성 수지를 포함할 수 있다. 이 경우, 절연층(111)을 보다 얇게 형성할 수 있으며, 미세한 재배선층(112) 및 재배선 비아(113)를 형성할 수 있다. 예를 들어, 제1 절연층(111a)과 제2 절연층(111b)은 모두 감광성 수지를 포함할 수 있다. 공정에 따라서 서로 다른 레벨의 절연층들(111) 간의 경계가 불분명할 수도 있다.
일 실시예에서, 재배선 기판(110)의 최외측 절연층(111a)은 그 상부에 적층된 절연층들(111b) 보다 큰 신율(elongation) 및 인성(toughness)을 갖는 절연성 수지를 포함하며, 연결 범프(141) 주위의 크랙(crack) 발생을 저지함으로써, 반도체 패키지(100A)의 신뢰성을 개선할 수 있다. 예를 들어, 제1 절연층(111a)은 반도체 패키지(100A)의 최외측 절연층이며, 제1 절연층(111a) 및 제1 절연층(111a) 상에 적층된 적어도 한층 이상의 제2 절연층(111b)은 각각 제1 절연성 수지와 제2 절연성 수지를 포함할 수 있다. 이때, 제2 절연성 수지의 신율 및 인성은 제1 절연성 수지의 신율 및 인성 보다 작을 수 있다. 예를 들어, 제1 절연성 수지는 신율(elongation)이 60% 이상 및 인성(toughness)이 70mJ/m2 이상이고, 제2 절연성 수지는 신율이 10% 내지 40% 범위 및 인성이 10mJ/m2 내지 40mJ/m2 범위일 수 있다. 예를 들어, 제1 절연성 수지는 신율이 60% 내지 85% 범위 및 인성이 70mJ/m2 내지 95mJ/m2 범위일 수 있다. 제1 절연성 수지 및 제2 절연성 수지는 모두 감광성 수지를 포함할 수 있다.
재배선층(112)은 절연층(111) 상에 또는 내에 배치는 서로 다른 레벨에 위치한 복수의 재배선층들(112)을 포함할 수 있다. 예를 들어, 복수의 재배선층들(112)은 제1 절연층(111a) 및 적어도 한층 이상의 제2 절연층(111b) 상에 또는 내에 배치되며 서로 전기적으로 연결될 수 있다. 복수의 재배선층들(112) 중 최하측 재배선층(112a)은 제1 연결 범프(141)와 연결되는 제1 패드(112P1)을 포함할 수 있고, 복수의 재배선층들(112) 중 최상측 재배선층(112c)은 제2 연결 범프(142)와 연결되며, 적어도 한층 이상의 제2 절연층(111b) 중 최상측 제2 절연층 상에 돌출된 제2 패드(112P2)를 포함할 수 있다. 일 실시예에서, 제1 패드(112P1)는 적어도 한층 이상의 제2 절연층(111b) 중 최하측 제2 절연층에 매립되고, 제1 절연층(111a)은 제1 패드(112P1)의 적어도 일부를 노출시키는 개구부(h1)를 가질 수 있다.
재배선층(112)은 반도체 칩(120)의 접속 패드(120P)를 재배선할 수 있다. 재배선층(112)은, 예를 들어, 구리(Cu), 알루미늄(Al), 은(Ag), 주석(Sn), 금(Au), 니켈(Ni), 납(Pb), 티타늄(Ti), 또는 이들의 합금을 포함하는 금속 물질을 포함할 수 있다. 재배선층(112)은 설계 디자인에 따라 다양한 기능을 수행할 수 있다. 예를 들어, 그라운드(GrouND: GND) 패턴, 파워(PoWeR: PWR) 패턴, 신호(Signal: S) 패턴을 포함할 수 있다. 신호(S) 패턴은 그라운드(GND) 패턴, 파워(PWR) 패턴 등을 제외한 각종 신호, 예를 들면, 데이터 신호 등을 포함할 수 있다.
재배선 비아(113)는 절연층(111)을 관통하여 복수의 재배선층들(112)을 상호 연결할 수 있다. 예를 들어, 재배선 비아(113)는 제1 절연층(111a) 및 적어도 한층 이상의 제2 절연층(111b) 중 적어도 일부를 관통하여 서로 다른 레벨에 위치한 복수의 재배선층들(112)을 전기적으로 연결할 수 있다. 재배선 비아(113)는 신호용 비아, 그라운드용 비아, 파워용 비아를 포함할 수 있다. 재배선 비아(113)는 예를 들어, 구리(Cu), 알루미늄(Al), 은(Ag), 주석(Sn), 금(Au), 니켈(Ni), 납(Pb), 티타늄(Ti), 또는 이들의 합금을 포함하는 금속 물질을 포함할 수 있다. 재배선 비아(113)는 비아홀의 내부에 금속 물질이 충전된 필드(filled) 비아 또는 비아홀의 내벽을 따라 금속 물질이 형성된 컨포멀(conformal) 비아 형태를 가질 수 있다.
반도체 칩(120)은 재배선 기판(110)의 상면 상에 배치되며, 재배선층(112) 과 전기적으로 연결된 접속 패드(120P)를 포함할 수 있다. 반도체 칩(120)은 플립-칩 본딩(flip-chip bonding) 방식으로 재배선 기판(110) 상에 실장될 수 있다. 예를 들어, 반도체 칩(120)은 접속 패드(120P)가 배치된 제1 면(S1)이 재배선 기판(110)의 상면을 향하도록 배치되고, 접속 패드(120P)는 제2 연결 범프(142)를 통해 재배선층(112)의 제2 패드(112P2)와 연결될 수 있다. 제2 연결 범프(142)는 랜드(land), 볼(ball), 또는 핀(pin) 형태를 가질 수 있다. 제2 연결 범프(142)는 예를 들어, 주석(Sn)이나 주석(Sn)을 포함하는 합금(예, Sn-Ag-Cu)을 포함할 수 있다. 접속 패드(120P)는 예를 들어, 알루미늄(Al) 등의 금속 물질을 포함할 수 있다.
반도체 칩(120)은 로직(Logic) 칩 또는 메모리(Memory) 칩일 수 있다. 로직 칩은, 예를 들어, 중앙 처리 장치(central processing unit, CPU), 그래픽 처리 장치 (graphics processing unit, GPU), 필드 프로그램어블 게이트 어레이(field programmable gate array, FPGA), 디지털 신호 처리 장치(digital signal processor, DSP), 암호화 프로세서, 마이크로 프로세서, 마이크로 컨트롤러, 아날로그-디지털 컨버터, 주문형 반도체(application-specific integrated circuit, ASIC) 등을 포함할 수 있다. 메모리 칩은, 예를 들어, DRAM(dynamic RAM), SRAM(static RAM) 등과 같은 휘발성 메모리 소자 또는 PRAM(phase change RAM), MRAM(magnetic RAM), RRAM(Resistive RAM), 플래시 메모리 등과 같은 비휘발성 메모리 소자를 포함할 수 있다. 이와 달리, 반도체 칩(130)은 재배선 구조(110) 상에 와이어 본딩(wire bonding) 방식으로 실장될 수도 있다.
봉합재(130)는 재배선 기판(110) 상에 배치되며, 반도체 칩(120)의 적어도 일부를 덮을 수 있다. 봉합재(130)는 절연 물질, 예를 들어, 에폭시 수지와 같은 열경화성 수지, 폴리이미드와 같은 열가소성 수지, 또는 무기필러 또는/및 유리섬유를 포함하는 프리프레그(prepreg), ABF(Ajinomoto Build-up Film), FR-4, BT(Bismaleimide Triazine), EMC(Epoxy Molding Compound), 등을 포함할 수 있다.
제1 및 제2 연결 범프들(141, 142)은 랜드(land), 볼(ball), 또는 핀(pin) 형태를 가질 수 있다. 제1 및 제2 연결 범프들(141, 142)은 예를 들어, 주석(Sn)이나 주석(Sn)을 포함하는 합금(예, Sn-Ag-Cu)을 포함할 수 있다. 제1 연결 범프(141)는 반도체 칩(120)과 반대의 재배선 기판(110) 하면 상에 배치되며, 재배선층(112)과 전기적으로 연결될 수 있다. 제1 연결 범프(141)는 반도체 패키지(100A)를 외부와 물리적 및/또는 전기적으로 연결시킬 수 있다. 제1 연결 범프(141)는 예를 들어, 솔더볼(solder ball)을 포함할 수 있다. 제2 연결 범프(142)는 재배선 기판(110)의 상면과 반도체 칩(120) 사이에 배치되며, 재배선층(112)과 접속 패드(120P)를 전기적으로 연결할 수 있다. 제2 연결 범프는(142)는 제1 연결 범프(141)와 같이 다양한 형태를 가질 수 있드며, 주석 등을 포함하는 저융점 금속을 포함할 수 있다. 언더필 수지(143)는 재배선 기판(110)과 반도체 칩(120) 사이를 채우며, 제2 연결 범프(142)를 감싸도록 형성될 수 있다. 언더필 수지(143)는 에폭시 수지 등의 절연성 수지를 포함할 수 있다. 언더필 수지(143)는 MUF(Molded Under-fill) 방식으로 형성된 봉합재(130)의 일부분일 수 있다.
도 2a 내지 2d는 도 1b의 반도체 패키지(100A)의 제조 방법을 개략적으로 나타낸 단면도들이다.
도 2a를 참조하면, 먼저, 캐리어(C) 상에 제1 절연층(111a) 및 패터닝된 재배선층(112a)을 형성할 수 있다. 예를 들어, 제1 절연층(111a)은 신율이 60% 이상이고 인성이 70mJ/m2 이상인 제1 감광성 수지를 포함할 수 있다. 제1 절연층(111a) 패키지의 최외곽 절연층으로서, 내부 절연층들 보다 높은 신율 및 인성을 가질 수 있다. 제1 절연층(111a)은 감광성 수지를 도포 및 경화하여 형성될 수 있다. 재배선층(112a)은 포토 공정, 에칭 공정, 및 도금 공정을 이용하여 형성될 수 있다.
도 2b를 참조하면, 제1 절연층(111a) 상에 복수의 제2 절연층들(111b)과 재배선층(112) 및 재배선 비아(113)를 형성하여, 재배선 기판(110)을 완성할 수 있다. 예를 들어, 제2 절연층들(111b)은 신율이 10% 내지 40% 범위이고, 인성이 10mJ/m2 내지 40mJ/m2 범위인 제2 감광성 수지를 포함할 수 있다. 제2 절연층들(111b)은 제1 절연층(111a) 보다 상대적으로 작은 인성 및 신율을 갖는 감광성 수지를 포함할 수 있다. 따라서, 제조 비용 상승을 최소화하면서, 최외곽 절연층의 크랙 발생을 저지하여, 패키지의 신뢰성을 개선할 수 있다. 제2 절연층들(111b)과 재배선층(112)은 도 2a에서 설명한 공정을 반복하여 형성될 수 있다. 재배선 비아(113)는 포토 공정 및 에칭 공정에 의해 형성된 비아홀에 도금 공정으로 금속 물질을 충진하여 형성될 수 있다. 재배선 비아(113)는 인접한 재배선층(112)과 동일한 도금 공정으로 형성될 수 있다.
도 2c를 참조하면, 재배선 기판(110) 상에 반도체 칩(120)을 실장하고, 봉합재(130)를 형성할 수 있다. 반도체 칩(120)은 제2 연결 범프(142)를 통해 제2 패드(112P2)에 연결될 수 있다. 제2 연결 범프(142)는 리플로우(reflow) 공정을 통해 형성될 수 있다. 봉합재(130)는 액상의 전구체를 라미네이션 후 경화하거나, 필름형의 전구체를 가열 및 경화하여 형성될 수 있다. 언더필 수지(143)는 봉합재(130) 형성 전에 반도체 칩(120)과 재배선 기판(110) 사이에 형성될 수 있다. 언더필 수지(143)는 생략되거나, 봉합재(130)와 일체로 형성되어 그 경계가 불분명할 수 있다.
도 2d를 참조하면, 도 2c의 캐리어(C)를 제거한 후 제1 절연층(111a)을 관통하는 복수의 개구부들(h1)을 형성할 수 있다. 개구부(h1)는 최하측 재배선층(112a)의 적어도 일부를 노출시킬 수 있다. 이후, 개구부(h1) 내에 솔더볼 또는/및 언더범프금속을 형성하여 재배선층(112)과 전기적으로 연결시킬 수 있다.
도 3a 및 3b는 각각 본 발명의 일 실시예에 따른 반도체 패키지(100B, 100C)를 나타낸 단면도이다.
도 3a를 참조하면, 반도체 패키지(100B)는 적어도 한층 이상의 제2 절연층(111b) 상의 제3 절연층(111c)을 더 포함하는 재배선 기판(110)을 포함할 수 있다. 또한, 복수의 재배선층들(112) 중 최상측 재배선층(112c)은 제2 연결 범프(142)와 연결되고 제3 절연층(111c) 상에 돌출된 제2 패드(112P2)를 포함할 수있다. 일 실시예에서, 제3 절연층(111c)은 제1 절연층(111a)과 동일한 절연성 수지를 포함할 수 있다. 예를 들어, 제1 절연층(111a) 및 제3 절연층(111c)은 신율이 60% 이상이고 인성이 70mJ/m2 이상인 감광성 수지를 포함할 수 있다. 따라서, 재배선 기판(110)의 최상측 및 최하측의 절연층에서 크랙이 발생하는 것을 방지할 수 있다.
도 3b를 참조하면, 반도체 패키지(100C)에서 재배선 기판(110)은 적어도 한층 이상의 제1 절연층(111a), 적어도 한층 이상의 제1 절연층(111a) 상에 적층된 적어도 한층 이상의 제2 절연층(111b)과, 제1 및 제2 절연층(111a, 111b) 내에 배치된 복수의 재배선층들(112)을 포함할 수 있다. 예를 들어, 제1 절연층(111a) 및 제2 절연층(111b)는 각각 수직(Z 방향)으로 적층된 복수(예, 2층)의 제1 절연층들(111a) 및 제2 절연층들(111b)을 포함할 수 있다. 일 실시예에서, 상대적으로 높은 신율과 인성을 갖는 제1 절연층(111a)을 복수층으로 구비함으로써, 크랙 발생을 더 효과적으로 저지할 수 있다.
도 4는 본 발명의 일 실시예에 따른 반도체 패키지(100D)를 나타낸 단면도이고, 도 5는 도 4의 반도체 패키지의 변형예를 나타낸 부분 확대도이다. 도 5는 도 4의 “A” 영역에 대응하는 일부 구성요소들를 도시한다.
도 4를 참조하면, 반도체 패키지(100D)에서 복수의 재배선층들(112) 중 최하측 재배선층(112a)은 제1 연결 범프(141)와 연결되는 제1 패드(112P1)를 포함하되, 제1 패드(112P1)는 제1 절연층(111a)에 매립되고, 제1 절연층(111a)의 하면은 제1 패드(112P1)의 하면과 실질적으로 동일한 레벨에 위치하거나 제1 패드(111a)의 상면과 상기 하면 사이에 위치할 수 있다. 예를 들어, 제1 패드(112P1)는 그 하면이 제1 절연층(111a)의 하면과 실질적으로 코플래너(coplanar)하도록 제1 절연층(111a)에 매립될 수 있다. 제1 패드(112P1)는 제1 절연층(111a)을 관통하는 재배선 비아(113)를 통해 제1 절연층(111a) 상의 재배선층(112)과 연결될 수 있다.
또한, 도 5를 참조하면, 변형예에서, 제1 절연층(111a)의 하면은 제1 패드(112P1)의 하면과 단차(d)를 가질 수 있다. 예를 들어, 제1 절연층(111a)의 하면은 제1 패드(112P1)의 하면과 상면 사이의 레벨에 위치할 수 있다. 일 실시예에서, 제1 패드(112P1)의 하면이 제1 절연층(111a)으로부터 완전히 노출됨으로써, 제1 연결 범프(141)와 제1 패드(112P1)의 접속 신뢰성을 보장할 수 있다.
도 6a 내지 6e는 도 4의 반도체 패키지(100D)의 제조 방법을 개략적으로 나타낸 단면도들이다.
도 6a를 참조하면, 먼저, 캐리어(C) 상에 제1 하부 절연층(111a_1) 및 패터닝된 재배선층(112a)을 형성할 수 있다. 제1 하부 절연층(111a_1)은 도 4의 제1 절연층(111a)과 동일한 절연성 수지를 포함할 수 있으나, 이와 달리 도 4의 제2 절연층(111b) 또는 이들과 다른 종류의 절연성 수지를 포함할 수도 있다. 예를 들어, 제1 하부 절연층(111a_1)은 신율이 60% 이상이고 인성이 70mJ/m2 이상인 제1 감광성 수지를 포함할 수 있다. 제1 하부 절연층(111a_1)은 감광성 수지를 도포 및 경화하여 형성될 수 있다. 재배선층(112a)은 포토 공정, 에칭 공정, 및 도금 공정을 이용하여 형성될 수 있다.
도 6b를 참조하면, 다음으로, 제1 하부 절연층(111a_1) 및 패터닝된 재배선층(112a)를 덮는 제1 상부 절연층(111a_2)을 형성할 수 있다. 제1 상부 절연층(111a_2)은 도 4의 제1 절연층(111a)에 대응하는 패키지의 최외곽 절연층으로서, 내부 절연층들 보다 높은 신율 및 인성을 가질 수 있다. 예를 들어, 제1 상부 절연층(111a_2)은 신율이 60% 이상이고 인성이 70mJ/m2 이상인 제1 감광성 수지를 포함할 수 있다.
도 6c를 참조하면, 제1 상부 절연층(111a_2) 상의 재배선층(112)과 제1 상부 절연층(111a_2)을 관통하는 재배선 비아(113)를 형성할 수 있다. 재배선 비아(113)는 포토 공정 및 에칭 공정에 의해 형성된 비아홀에 도금 공정으로 금속 물질을 충진하여 형성될 수 있다. 재배선 비아(113)는 인접한 재배선층(112)과 동일한 도금 공정으로 형성될 수 있다.
도 6d를 참조하면, 도 6c의 공정을 반복하여, 제1 상부 절연층(111a_2) 상에 복수의 제2 절연층(111b)과, 복수의 재배선층(112) 및 복수의 재배선 비아(113)를 형성하여 재배선 기판(110)을 완성할 수 있다. 이후, 재배선 기판(110)에 반도체 칩(120)을 실장하고 봉합재(130)를 형성할 수 있다. 이는, 도 2b 및 2c에서 설명한 바와 실질적으로 동일한 방법으로 형성될 수 있다.
도 6e를 참조하면, 도 6d의 캐리어(C)를 제거한 후 제1 하부 절연층(111a_1)을 에칭하여, 최하측 재배선층(112a) 또는 제1 패드(112P1)를 노출시킬 수 있다. 제1 패드(112P1)는 그 하면이 제1 상부 절연층(111a_2)의 하면과 실질적으로 동일한 레벨에 있거나 제1 상부 절연층(111a_2)의 하면과 상면 사이의 레벨에 위치하도록 제1 상부 절연층(111a_2)에 매립될 수 있다. 이후, 제1 패드(112P1) 상에 솔더볼 등의 연결 범프를 형성할 수 있다.
도 7은 본 발명의 일 실시예에 따른 반도체 패키지(100E)를 나타낸 단면도이다.
도 7을 참조하면, 반도체 패키지(100E)에서 접속 패드(120P)가 배치된 반도체 칩(120)의 제1 면(S1)은 재배선 기판(110)의 상면(S2)과 접할 수 있다. 또한, 재배선 기판(110)은 복수의 제2 절연층들(111b) 중 최상측 제2 절연층을 관통하여 접속 패드(120P)와 재배선층(112)을 연결하는 재배선 비아(113)를 포함할 수 있다. 예를 들어, 재배선 기판(112)은 수직 방향(Z 방향)으로 적층된 제1 절연층(111a) 및 제2 절연층(111b)과, 제1 절연층(111a) 및 제2 절연층(111b) 내에 배치된 재배선층(112)을 포함할 수 있다. 반도체 칩(120)은 제1 면(S1)이 제2 절연층(111b)을 마주하도록 재배선 기판(110) 상에 배치되며, 접속 패드(120P)는 제2 절연층(112b)을 관통하는 재배선 비아(113)와 직접 연결될 수 있다. 일 실시예에서, 복수의 재배선 비아들(113)은 반도체 칩(120)의 적층 방향으로 그 가로 방향(X 방향) 폭이 작아지는 테이퍼(taper) 형상을 가질 수 있다.
제1 절연층(111a) 및 제2 절연층(111b)은 각각 제1 절연성 수지 및 제2 절연성 수지를 포함할 수 있다. 제1 절연성 수지는 신율이 60% 이상 및 인성이 70mJ/m2 이상이고, 제2 절연성 수지는 신율이 10% 내지 40% 범위 및 인성이 10mJ/m2 내지 40mJ/m2 범위일 수 있다. 일 실시예에서, 복수의 재배선층들(112) 중 최하측 재배선층(112a)은 최하측 제2 절연층(111b) 상에 배치되며, 제1 절연층(111a)에 매립될 수 있다. 제1 절연층(111a)은 최하측 재배선층(112a)의 적어도 일부를 노출시키는 복수의 개구부들(h1)을 가질 수 있다. 제1 절연층(111a)의 복수의 개구부들(h1) 내에는 각각 복수의 연결 범프들(141)이 배치될 수 있다.
복수의 연결 범프들(141)은 제1 절연층(111a)으로부터 노출된 재배선층(112a)의 적어도 일부와 전기적으로 연결될 수 있다. 일 실시예에서, 복수의 연결 범프들(141) 중 적어도 일부는 팬-아웃(fan-out) 영역에 배치될 수 있다. 예를 들어, 재배선 기판(110)의 가로(X 또는 Y 방향) 폭은 반도체 칩(120)의 가로(X 또는 Y 방향) 폭 보다 크고, 복수의 연결 범프들(141) 중 적어도 일부는 반도체 칩(120)의 제1 면에(S1) 수직한 방향(Z 방향)으로 반도체 칩(120)과 중첩되지 않을 수 있다. 일 실시예에서, 재배선층(112)은 반도체 칩(120)의 접속 패드(112P)를 팬-아웃 영역으로 재배선할 수 있다.
도 8은 본 발명의 일 실시예에 따른 반도체 패키지(100F)를 나타낸 단면도이다.
도 8을 참조하면, 반도체 패키지(100F)에서 복수의 연결 범프들(141)은 팬-인(fan-in) 영역에 배치될 수 있다. 예를 들어, 재배선 기판(110)의 가로(X 방향 또는 Y 방향) 폭은 반도체 칩(120)의 가로(X 방향 또는 Y 방향) 폭과 실질적으로 동일하고, 복수의 연결 범프들(141)은 반도체 칩(120)의 제1 면(S1)에 수직한 방향(Z 방향)으로 반도체 칩(120)과 중첩될 수 있다.
일 실시예에서, 반도체 패키지(100F)는 도 7의 반도체 패키지(100E)와 유사한 재배선 구조를 가질 수 있다. 예를 들어, 반도체 칩(120)의 제1 면(S1)은 재배선 기판(110)의 상면(S2)과 접할 수 있다. 또한, 재배선 기판(112)은 수직 방향(Z 방향)으로 적층된 제1 절연층(111a) 및 제2 절연층(111b)과, 제1 절연층(111a) 및 제2 절연층(111b) 내에 배치된 재배선층(112)을 포함할 수 있다. 반도체 칩(120)은 제1 면(S1)이 제2 절연층(111b)을 마주하도록 재배선 기판(110) 상에 배치되며, 접속 패드(120P)는 제2 절연층(112b)을 관통하는 재배선 비아(113)와 직접 연결될 수 있다. 복수의 재배선 비아들(113)은 반도체 칩(120)의 적층 방향으로 그 가로 방향(X 방향) 폭이 작아지는 테이퍼(taper) 형상을 가질 수 있다.
도 9는 본 발명의 일 실시예에 따른 반도체 패키지(100G)를 나타낸 단면도이다.
도 9를 참조하면, 반도체 패키지(100G)는 재배선 기판(110)에 실장된 복수의 반도체 칩들(121, 122)을 포함할 수 있다. 복수의 반도체 칩들(121, 122)은 수평 방향(X 또는 Y 방향)으로 인접하게 배치되거나, 수직 방향(Z 방향)으로 적층될 수도 있다. 예를 들어, 반도체 패키지(100G)는 재배선 기판(110) 상에 배치되며, 재배선층(112)에 전기적으로 연결된 제1 접속 패드(121P)를 포함하는 제1 반도체 칩(121)과, 재배선 기판(110) 상에서 제1 반도체 칩(121)과 인접하게 배치되며, 재배선층(112)에 전기적으로 연결된 제2 접속 패드(122P)를 포함하는 제2 반도체 칩(122)을 포함할 수 있다. 제1 접속 패드(121P)와 제2 접속 패드(122P)는 재배선층(122)을 통해 서로 전기적으로 연결될 수 있다.
제1 및 제2 반도체 칩(121, 122)은 서로 다른 종류의 반도체 칩을 포함할 수 있다. 예를 들어, 제1 반도체 칩(121)은 예를 들어, 센트랄 프로세서(CPU), 그래픽 프로세서(GPU), 필드 프로그램어블 게이트 어레이(FPGA), 디지털 신호 프로세서(DSP), 암호화 프로세서, 마이크로 프로세서, 마이크로 컨트롤러, 아날로그-디지털 컨버터, 주문형 반도체(ASIC)와 같은 로직 칩을 포함할 수 있다. 제2 반도체 칩(122)은 예를 들어, DRAM, SRAM 등과 같은 휘발성 메모리 칩, PRAM, MRAM, RRAM, 플래시 메모리 칩 등의 비휘발성 메모리 칩, 또는 HBM(High bandwidth memory), HMC(Hybrid memory cubic) 등과 같은 고성능 메모리 장치를 포함할 수 있다.
도 10는 본 발명의 일 실시예에 따른 반도체 패키지(1000)를 나타낸 단면도이다.
도 10을 참조하면, 반도체 패키지(1000)는 제1 패키지(100) 및 제1 패키지(100) 상부에 결합된 제2 패키지(200)를 포함할 수 있다. 제1 패키지(100)는, 도 1b, 3a, 3b, 4, 7, 8, 9 등에 도시된 반도체 패키지(100A, 100B, 100C, 100D, 100E, 100F, 100G)에서, 재배선 기판(110) 상에 배치되는 수직 연결 구조(150)를 더 포함할 수 있다. 수직 연결 구조(150)는 적어도 일부의 표면이 봉합재(130)에 의해 커버될 수 있다. 수직 연결 구조(150)는 재배선층(112)에 전기적으로 연결될 수 있다. 수직 연결 구조(150)는 도전체가 봉합재(140)의 일부를 관통하는 포스트 형태이거나, 절연층과 도전층이 순차로 적층된 다층 기판 형태(예, PCB)를 가질 수 있다.
수직 연결 구조(150)는 제1 패키지(100)를 수직 방향(Z 방향)으로 지나는 전기 연결 경로를 제공할 수 있다. 수직 연결 구조(150)는 봉합재(130) 상부의 개구부를 통해서 금속 범프(240)와 연결될 수 있다. 봉합재(130)는 수직 연결 구조(150)의 측면을 감싸는 제1 봉합재(131)와 제1 봉합재(131) 상의 제2 봉합재(132)를 포함할 수 있다. 제1 봉합재(131)와 제2 봉합재(132)는 서로 다른 물질을 포함할 수 있다. 예를 들어, 제1 봉합재(131)는 EMC를 포함하고, 제2 봉합재(132)는 PID를 포함할 수 있다. 이와 달리, 제1 및 제2 봉합재(131, 132)는 서로 동일한 종류의 절연 물질을 포함할 수도 있다. 변형예에서, 제1 봉합재(131)의 상부를 연마하여 반도체 칩의 상면을 노출시킬 수도 있다. 또한, 제2 봉합재(132) 상에는 수직 연결 구조(150)와 금속 범프(240)를 물리적 및 전기적으로 연결하는 후면 재배선층이 더 형성될 수 있다.
제2 패키지(200)는 제2 재배선 기판(210), 제2 반도체 칩(220), 및 제2 봉합재(230)를 포함할 수 있다. 제2 재배선 기판(210)은 하면과 상면에 각각 외부와 전기적으로 연결될 수 있는 재배선 패드들(211a, 211b)을 포함할 수 있다. 또한, 제2 재배선 기판(210)은 내부에 재배선 패드들(211a, 211b)과 연결되는 재배선 회로(212)를 포함할 수 있다. 재배선 회로(212)는 제2 반도체 칩(220)의 접속 패드(220P)를 팬-아웃 영역으로 재배선할 수 있다.
제2 반도체 칩(220)은 내부의 집적 회로와 연결된 접속 패드(220P)을 포함하며, 접속 패드(220P)는 연결 부재를 통해서 제2 재배선 구조(210)와 전기적으로 연결될 수 있다. 연결 부재는 도전성 범프 또는 도전성 와이어를 포함할 수 있다. 예를 들어, 연결 부재는 솔더볼일 수 있다. 변형예에서 제2 반도체 칩(220)의 접속 패드(220P)는 제2 재배선 기판(210)의 상면에 직접 접촉하고, 제2 재배선 구조(210) 내부의 비아를 통해서 재배선 회로(212)에 전기적으로 연결될 수도 있다.
제2 봉합재(230)는 제1 패키지(100)의 제1 봉합재(140)와 동일하거나 유사한 재료를 포함할 수 있다. 제2 패키지(200)는 금속 범프(240)에 의해서 제1 패키지(100)와 물리적 및 전기적으로 연결될 수 있다. 금속 범프(240)는 제2 재배선 기판(210) 하면의 재배선 패드(211a)를 통하여 제2 재배선 기판(210) 내부의 재배선 회로(212)와 전기적으로 연결될 수 있다. 금속 범프(240)는 저융점 금속, 예를 들면, 주석(Sn)이나 또는 주석(Sn)을 포함하는 합금으로 구성될 수 있다.
일 실시예에서, 제1 재배선 기판(110)의 최하측 절연층(111a)은 신율이 60% 이상 및 인성이 70mJ/m2 이상인 감광성 수지를 포함할 수 있다. 또한, 제2 패키지(200)의 제2 재배선 기판(210) 역시 하부 재배선 패드(211a)를 노출시키는 최외측 절연층이 신율이 60% 이상 및 인성이 70mJ/m2 이상인 감광성 수지를 포함할 수 있다. 따라서, 솔더볼 등의 범프가 배치되는 최외곽 절연층에서 크랙이 발생하는 것을 방지할 수 있다.
도 11은 최외측 절연층의 물성에 따른 신뢰성 테스트 결과를 나타낸 그래프이다. 도 11은 최외측 절연층(예, 도 1b의 “111a”)으로 제1 감광성 수지(PID A)와 제2 감광성 수지(PID B)를 각각 포함하는 재배선 기판의 TC(Temperature Cycling) 신뢰성 테스트 결과를 나타낸다. 여기서, 제1 감광성 수지(PID A)는 신율이 약 40% 및 인성이 약 41.2mJ/m2 이고, 제2 감광성 수지(PID B)는 신율이 약 76% 및 인성이 약 86.5mJ/m2 이다. 도 11의 그래프에서 가로 축은 사이클 반복 횟수를 나타내고 세로 축은 크랙 발생 확률을 나타낸다. TC 신뢰성 테스트는 온도 조건 -55℃ 내지 +125℃로 수행되었다.
도 11을 참조하면, 제1 감광성 수지(PID A)를 포함하는 기판은 사이클링이 증가할수록 크랙 발생 확률이 급격히 증가하는 반면, 제2 감광성 수지(PID B)를 포함하는 기판은 크랙 발생 확률이 현저히 낮음을 알 수 있다.
본 발명은 상술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니며 첨부된 청구범위에 의해 한정하고자 한다. 따라서, 청구범위에 기재된 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 당 기술분야의 통상의 지식을 가진 자에 의해 다양한 형태의 치환, 변형 및 변경이 가능할 것이며, 이 또한 본 발명의 범위에 속한다고 할 것이다.

Claims (10)

  1. 제1 절연층과, 상기 제1 절연층 상의 적어도 한층 이상의 제2 절연층과, 각각의 상기 제1 절연층 및 상기 적어도 한층 이상의 제2 절연층 상에 배치되며 서로 전기적으로 연결된 복수의 재배선층들을 포함하는 재배선 기판;
    상기 재배선 기판 상에 배치되며, 상기 복수의 재배선층들과 전기적으로 연결된 접속 패드를 포함하는 반도체 칩;
    상기 재배선 기판 상에 배치되며, 상기 반도체 칩을 덮는 봉합재;
    상기 반도체 칩과 반대의 상기 재배선 기판 상에 배치되며, 상기 복수의 재배선층들과 전기적으로 연결된 제1 연결 범프; 및
    상기 재배선 기판과 상기 반도체 칩 사이에 배치되며, 상기 복수의 재배선층들과 상기 접속 패드를 전기적으로 연결하는 제2 연결 범프를 포함하고,
    상기 제1 절연층은 제1 감광성 수지를 포함하되, 상기 제1 감광성 수지는 신율(elongation)이 60% 이상 및 인성(toughness)이 70mJ/m2 이상이고,
    상기 적어도 한층 이상의 제2 절연층은 제2 감광성 수지를 포함하되, 상기 제2 감광성 수지는 신율이 10% 내지 40% 범위 및 인성이 10mJ/m2 내지 40mJ/m2 범위인 반도체 패키지.
  2. 제1 항에 있어서,
    상기 복수의 재배선층들 중 최하측 재배선층은 상기 제1 연결 범프와 연결되는 제1 패드를 포함하고,
    상기 제1 패드는 상기 적어도 한층 이상의 제2 절연층 중 최하측 제2 절연층에 매립되고,
    상기 제1 절연층은 상기 제1 패드의 적어도 일부를 노출시키는 개구부를 갖는 반도체 패키지.
  3. 제1 항에 있어서,
    상기 복수의 재배선층들 중 최하측 재배선층은 상기 제1 연결 범프와 연결되는 제1 패드를 포함하고,
    상기 제1 패드는 상기 제1 절연층에 매립되고,
    상기 제1 절연층의 하면은 상기 제1 패드의 하면과 동일한 레벨에 위치하거나 상기 제1 패드의 상면과 상기 하면 사이에 위치하는 반도체 패키지.
  4. 제1 항에 있어서,
    상기 제1 절연층은 상기 반도체 패키지의 최외측 절연층인 반도체 패키지.
  5. 수직 방향으로 적층된 제1 절연층 및 제2 절연층과, 상기 제1 절연층 및 상기 제2 절연층 내에 배치된 재배선층을 포함하는 재배선 기판;
    접속 패드가 배치된 제1 면을 가지며, 상기 제1 면이 상기 제2 절연층을 마주하도록 상기 재배선 기판 상에 배치된 반도체 칩; 및
    상기 재배선 기판 및 상기 반도체 칩을 덮는 봉합재를 포함하고,
    상기 제1 절연층은 제1 절연성 수지를 포함하고,
    상기 제2 절연층은 제2 절연성 수지를 포함하고,
    상기 제1 절연성 수지는 신율 및 인성이 상기 제2 절연성 수지 보다 큰 반도체 패키지.
  6. 제5 항에 있어서,
    상기 반도체 칩의 상기 제1 면은 상기 재배선 기판의 상면과 접하는 반도체 패키지.
  7. 제5 항에 있어서,
    상기 재배선 기판의 하면 상에 배치되는 복수의 연결 범프들을 더 포함하되,
    상기 재배선층의 적어도 일부는 상기 제1 절연층으로부터 노출되고,
    상기 복수의 연결 범프들은 상기 제1 절연층으로부터 노출된 상기 재배선층의 적어도 일부와 연결되는 반도체 패키지.
  8. 제7 항에 있어서,
    상기 재배선 기판의 가로 폭은 상기 반도체 칩의 가로 폭 보다 크고,
    상기 복수의 연결 범프들 중 적어도 일부는 상기 반도체 칩의 상기 제1 면에 수직한 방향으로 상기 반도체 칩과 중첩되지 않는 반도체 패키지.
  9. 제7 항에 있어서,
    상기 재배선 기판의 가로 폭은 상기 반도체 칩의 가로 폭과 동일하고,
    상기 복수의 연결 범프들은 상기 반도체 칩의 상기 제1 면에 수직한 방향으로 상기 반도체 칩과 중첩되는 반도체 패키지.
  10. 적어도 한층 이상의 제1 절연층, 상기 적어도 한층 이상의 제1 절연층 상에 적층된 적어도 한층 이상의 제2 절연층과, 상기 적어도 한층 이상의 제1 및 제2 절연층 내에 배치된 복수의 재배선층들을 포함하는 재배선 기판; 및
    상기 재배선 기판 상에 배치되며, 상기 복수의 재배선층들에 전기적으로 연결된 제1 접속 패드를 포함하는 제1 반도체 칩을 포함하고,
    상기 적어도 한층 이상의 제1 절연층은 제1 절연성 수지를 포함하고,
    상기 적어도 한층 이상의 제2 절연층은 제2 절연성 수지를 포함하고,
    상기 제1 절연성 수지는 신율이 60% 이상 및 인성이 70mJ/m2 이상인 반도체 패키지.
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US7553753B2 (en) * 2006-08-31 2009-06-30 Freescale Semiconductor, Inc. Method of forming crack arrest features in embedded device build-up package and package thereof
US9064936B2 (en) * 2008-12-12 2015-06-23 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US10204879B2 (en) * 2011-01-21 2019-02-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming wafer-level interconnect structures with advanced dielectric characteristics
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US10061967B2 (en) 2016-08-22 2018-08-28 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
US9741690B1 (en) 2016-09-09 2017-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution layers in semiconductor packages and methods of forming same
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US10515888B2 (en) 2017-09-18 2019-12-24 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and method for manufacturing the same
US10157871B1 (en) * 2017-10-12 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and manufacturing method thereof
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