TW201916297A - 積體扇出型封裝 - Google Patents

積體扇出型封裝 Download PDF

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Publication number
TW201916297A
TW201916297A TW106139793A TW106139793A TW201916297A TW 201916297 A TW201916297 A TW 201916297A TW 106139793 A TW106139793 A TW 106139793A TW 106139793 A TW106139793 A TW 106139793A TW 201916297 A TW201916297 A TW 201916297A
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Taiwan
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layer
conductive
dielectric layer
dielectric
modulus
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TW106139793A
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English (en)
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TWI735702B (zh
Inventor
游濟陽
陳衿良
陳海明
何冠霖
梁裕民
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台灣積體電路製造股份有限公司
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Publication of TWI735702B publication Critical patent/TWI735702B/zh

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Abstract

一種積體扇出型封裝包括晶粒、包封體、重佈線結構、多個導電柱、晶種層及多個導電凸塊。所述包封體包封所述晶粒。所述重佈線結構位於所述晶粒及所述包封體上。所述重佈線結構與所述晶粒電性連接且包括依序堆疊的多個介電層以及夾置在所述介電層之間的多個導電圖案。距所述晶粒最遠的所述介電層的楊氏模數高於所述介電層中其餘介電層中的每一者的楊氏模數。所述導電圖案彼此電性連接。所述導電柱設置在所述重佈線結構上且與所述重佈線結構電性連接。所述晶種層位於所述導電柱與所述重佈線結構之間。所述導電凸塊設置在所述多個導電柱上。

Description

積體扇出型封裝
本發明是有關於一種積體扇出型封裝，且特別是有關於一種具有抗應力層的積體扇出型封裝。
由於各種電子元件（即，電晶體、二極體、電阻器、電容器等）的積體密度的持續提高，半導體行業已經歷快速發展。在很大程度上，積體密度的此種提高來自於最小特徵大小（minimum feature size）的重複減小，此使得更多較小的元件能夠集成到給定區域中。當前，積體扇出型封裝因其緊密性而正變得日漸流行。積體扇出型封裝通常包括位於模塑的積體電路裝置上的重佈線路結構，以使得所述積體電路裝置可被存取。為滿足更小大小及更高封包密度的要求，重佈線路結構的製造方法已成為本領域中的重要議題。
一種積體扇出型封裝包括晶粒、包封體、重佈線結構、多個導電柱、晶種層、及多個導電凸塊。所述包封體包封所述晶粒。所述重佈線結構位於所述晶粒及所述包封體上。所述重佈線結構與所述晶粒電性連接且包括依序堆疊的多個介電層以及夾置在所述介電層之間的多個導電圖案。距所述晶粒最遠的所述介電層的楊氏模數高於所述介電層中其餘介電層中的每一者的楊氏模數。所述導電圖案彼此電性連接。所述導電柱設置在所述重佈線結構上且與所述重佈線結構電性連接。所述晶種層位於所述導電柱與所述重佈線結構之間。所述導電凸塊設置在所述導電柱上。
以下公開內容提供用於實作所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及排列的具體實例以簡化本公開內容。當然，這些僅為實例且不旨在進行限制。舉例來說，以下說明中將第一特徵形成在第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本公開內容可能在各種實例中重複使用參考編號及/或字母。這種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「之下（beneath）」、「下面（below）」、「下部的（lower）」、「上方（above）」、「上部的（upper）」等空間相對性用語來闡述圖中所示的一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括裝置在使用或操作中的不同取向。設備可具有其他取向（旋轉90度或處於其他取向），且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
也可包括其他特徵及製程。舉例來說，可包括測試結構，以説明對三維（three-dimensional；3D）封裝或三維積體電路（3D integrated circuit；3DIC）裝置進行驗證測試。所述測試結構可例如包括在重佈線層中或在基板上形成的測試接墊，以容許對三維封裝或三維積體電路進行測試、對探針及/或探針卡（probe card）進行使用等。可對中間結構以及最終結構執行驗證測試。另外，本文中所公開的結構及方法可結合包括對已知良好晶粒（known good die）進行中間驗證的測試方法而使用，以提高良率並降低成本。
圖1A至圖1F繪示根據本發明一些實施例的製造積體扇出型封裝10的方法的各製程的示意性剖面圖。參照圖1A，提供上面形成有剝離層DB的載板C。在一些實施例中，載板C可為玻璃基板，且剝離層DB可為形成在所述玻璃基板上的光熱轉換（light-to-heat conversion；LTHC）釋放層。在一些實施例中，可在剝離層DB上可選地形成介電層（圖中未繪示）。
如圖1A中所示，在載板C上提供及放置多個晶粒100。在一些實施例中，可通過拾取及放置製程（pick and place process）將晶粒100放置在剝離層DB上。可將晶粒100通過晶粒貼合膜（die attach film；DAF）、黏合膏（adhesion paste）等貼合或黏合在剝離層DB上。為簡潔起見，在圖1A中僅繪示一個晶粒100。然而，可提供多於一個晶粒且可將所述晶粒排列成陣列。應理解的是，本發明的範圍不受所公開實例限制。在一些實施例中，可將當前製程步驟視作晶圓級封裝製程（wafer level packaging process）的一部分。
在一些實施例中，如圖1A中所示，每一晶粒100包括半導體基板110、多個導電接墊120、鈍化層（passivation layer）130、後鈍化層（post-passivation layer）140、多個導電柱體150、及保護層160。在一些實施例中，半導體基板110可為矽基板，所述矽基板包括形成在所述矽基板中的主動元件（例如，電晶體等）及可選地形成在所述矽基板中的被動元件（例如，電阻器、電容器、電感器等）。導電接墊120形成在半導體基板110上且可為鋁接墊、銅接墊、或其他適合的金屬接墊。導電柱體150設置在導電接墊120上且與導電接墊120電性連接。在一些實施例中，導電柱體150是通過導電材料的鍍覆製程（plating process）形成在導電接墊120上。在一些實施例中，導電柱體150可為鍍銅柱或其他適合的金屬柱。在一些替代性實施例中，導電柱體150為被焊料頂蓋（例如，不含鉛的焊料頂蓋）覆蓋的銅柱或其他適合的金屬柱。在一些實施例中，保護層160可為具有足以包封及保護導電柱體150的厚度的聚合物層。在一些實施例中，保護層160的材料包括聚苯并噁唑（polybenzoxazole；PBO）、聚醯亞胺（polyimide；PI）、或其他適合的聚合材料。在一些替代性實施例中，保護層160可由無機材料製成。在一些實施例中，後鈍化層140是可選的。
參照圖1B，在剝離層DB上形成包封材料200以包封晶粒100。換句話說，將所有晶粒100（在圖1B中僅繪示一個晶粒）模塑及嵌置在包封材料200中。在一些實施例中，通過模塑製程（molding process）來形成包封材料200。晶粒100的導電柱體150及保護層160被包封材料200完全覆蓋。換句話說，晶粒100的導電柱體150及保護層160不會被顯露出且被包封材料200很好地保護。在一些替代性實施例中，包封材料200的材料包括環氧樹脂（epoxy resin）或其他適合的介電材料。
參照圖1C，接著對包封材料200進行研磨直到暴露出導電柱體150為止，以形成包封體200a。在一些實施例中，通過機械研磨製程（mechanical grinding process）及/或化學機械拋光（chemical mechanical polishing；CMP）製程來研磨包封材料200。在包封材料200的研磨製程期間，對保護層160的部分及導電柱體150的部分進行研磨以形成保護層160a及導電柱體150a。如圖1C中所示，包封體200a環繞晶粒100a且在側向上包封晶粒100a的側壁。換句話說，包封體200a環繞且包裹晶粒100a（在圖1C中僅繪示一個晶粒）的側壁。在一些實施例中，包封體200a的頂表面、導電柱體150a的頂表面及保護層160a的頂表面實質上共面且彼此齊平。
參照圖1D，在包封體200a上形成覆蓋晶粒100a的重佈線結構300。在一些實施例中，晶種層410a及多個導電柱420隨後形成在重佈線結構300上。此後，在導電柱420上形成多個導電凸塊500。在一些實施例中，導電柱420與導電凸塊500統稱為受控塌陷晶粒連接（controlled collapse chip connect；C4）凸塊。在圖1D中，區R是由虛線所包圍，且區R會在之後進一步繪示，以闡述重佈線結構300、導電柱420及導電凸塊500之間的連接。可在示意性放大圖中繪示此種區R以在以下段落中進一步闡述製造製程及可能的結構性變更。在一些實施例中，重佈線結構300包括依序堆疊的第一介電層310a、第二介電層312a、第三介電層314a及第四介電層316a。在一些實施例中，重佈線結構300還包括彼此電性連接的多個第一導電圖案320a、多個第二導電圖案322a及多個第三導電圖案324a。第一導電圖案320a夾置在第一介電層310a與第二介電層312a之間。類似地，第二導電圖案322a及第三導電圖案324a分別夾置在第二介電層312a與第三介電層314a之間及第三介電層314a與第四介電層316a之間。在一些實施例中，重佈線結構300與晶粒100a電性連接。舉例來說，第一導電圖案320a可接觸晶粒100a的導電柱體150a以在所述二者之間實現電性連接。在一些實施例中，對於具有四個介電層的重佈線結構來說，第四介電層316a被稱作在與晶粒100a（在圖1D中僅繪示一個晶粒）的頂表面垂直的方向上距晶粒100a最遠的介電層。在特定實施例中，距晶粒100a最遠的介電層或用於接納（receiving）導電柱420的介電層的楊氏模數（Young’s modulus）（彈性模量）高於重佈線結構300的其他介電層。類似地，第三導電圖案324a被稱作在與晶粒100a的頂表面垂直的方向上距晶粒100a最遠的導電圖案。在一些實施例中，第四介電層316a的楊氏模數高於第一介電層310a的楊氏模數、第二介電層312a的楊氏模數及第三介電層314a的楊氏模數。在一些實施例中，第四介電層316a的楊氏模數介於0.5 GPa至150 GPa的範圍內。另一方面，第一介電層310a的楊氏模數、第二介電層312a的楊氏模數及第三介電層314a的楊氏模數介於0.1 GPa至100 GPa的範圍內。在特定實施例中，第四介電層316a的楊氏模數對第一介電層310a、第二介電層312a或第三介電層314a的楊氏模數的比率介於1.05至100的範圍內。當楊氏模數的比率低於1.05時，第四介電層316a不能夠承受住從導電柱420所產生的應力，而使重佈線結構300中的導電圖案變形。另一方面，當楊氏模數的比率超過100時，第四介電層316a將呈現與純矽的硬度相似的硬度，由此增大加工難度。在一些實施例中，第四介電層316a的厚度大於第一介電層310a的厚度、第二介電層312a的厚度或第三介電層314a的厚度。在一些實施例中，較高的楊氏模數使得第四介電層316a能夠減輕或阻擋從導電柱420施加到下伏重佈線結構300的應力，從而保護重佈線結構300中的導電圖案不因在裝配製程及/或熱製程期間產生的應力而損壞。換句話說，具有較高楊氏模數的第四介電層316a有助於減輕重佈線結構300中的精細線變形（fine line deformation）問題。因此，在一些實施例中，可將重佈線結構300的第四介電層316a稱作抗應力層（anti-stress layer）。應注意的是，儘管圖1D繪示四個介電層及三個導電圖案層，然而此配置僅充當實例。在一些替代性實施例中，重佈線結構300可包括更多層或更少層的介電層及導電圖案層。
如圖1D中所示，在一些實施例中，在形成導電柱420之前形成晶種層410a且晶種層410a夾置在導電柱420與重佈線結構300之間。在一些實施例中，導電柱420與重佈線結構300電性連接。舉例來說，導電柱420可與第三導電圖案324a電性連接。隨後將結合圖2A至圖2K、圖3A至圖3J、圖4A至圖4J、圖5A、圖6A至圖6I及圖7A來更詳細地論述與重佈線路結構300、晶種層410a、導電柱420、及導電凸塊500的形成相關的說明。
參照圖1E，將包括導電凸塊500、導電柱420、重佈線結構300、包封體200a及晶粒100a（在圖1F中僅繪示一個晶粒）的積體扇出型封裝陣列從剝離層DB剝離，以使得晶粒100a及包封體200a與載板C分離。在一些實施例中，可對剝離層DB（例如，光熱轉換釋放層）照射紫外光雷射（UV laser），以將剝離層DB從晶粒100a及包封體200a剝離而獲得積體扇出型封裝陣列。
參照圖1F，對積體扇出型封裝陣列進行切割或單體化以形成多個積體扇出型封裝10。在一些實施例中，切割製程或單體化製程通常涉及使用旋轉刀片或雷射光束來進行切割。換句話說，切割製程或單體化製程為例如雷射削切製程（laser cutting process）、機械削切製程（mechanical cutting process）、或其他適合的製程。
圖2A至圖2K是以區R為著重點繪示根據本發明一些實施例的示例性封裝的製造方法的各製程的示意性放大剖面圖。圖2A至圖2K繪示用於在與圖1C至圖1D中所繪示的結構相似的包封體200a及晶粒100a上形成重佈線結構300、導電柱420及導電凸塊500的詳細製程步驟。參照圖2A，在保護層160a、導電柱體150a及包封體200a上形成介電材料層310。在一些實施例中，介電材料層310的材料包括聚醯亞胺、環氧樹脂、丙烯酸樹脂、酚醛樹脂、苯並環丁烯（benzocyclobutene；BCB）、聚苯并噁唑（PBO）或任何其他適合的聚合物系介電材料。在一些實施例中，介電材料層310的楊氏模數介於0.1 GPa至100 GPa的範圍內且厚度介於1微米（μm）至50μm的範圍內。舉例來說，可通過例如旋轉塗布（spin-on coating）、化學氣相沉積（chemical vapor deposition；CVD）、電漿增強型化學氣相沉積（plasma-enhanced chemical vapor deposition；PECVD）等適合的製作技術來形成介電材料層310。
參照圖2B，在一些實施例中，將介電材料層310圖案化以形成具有多個開口O310a 的第一介電層310a。在一些實施例中，開口O310a 暴露出位於第一介電層310a下的導電柱體150a。可通過微影製程（photolithography process）及蝕刻製程（etching process）來將介電材料層310圖案化。此後，在第一介電層310a上形成第一導電圖案320a。在一些實施例中，第一導電圖案320a延伸到開口O310a 中從而接觸導電柱體150a。第一導電圖案320a可通過例如電鍍（electroplating）、沉積（deposition）、及/或微影及蝕刻等來形成。在一些實施例中，第一導電圖案320a的材料包括鋁、鈦、銅、鎳、鎢、及/或其合金。
參照圖2C，重複進行在與圖2B有關的上下文中闡述的製程步驟以依序形成第二介電層312a、第二導電圖案322a、第三介電層314a及第三導電圖案324a。在一些實施例中，第一介電層310a的材料、第二介電層312a的材料及第三介電層314a的材料可為相同的。在一些實施例中，第一介電層310a的材料、第二介電層312a的材料及第三介電層314a的材料可為不同的，只要其各自的楊氏模數落於0.1 GPa至100 GPa的範圍內即可。類似地，第一導電圖案320a的材料、第二導電圖案322a的材料及第三導電圖案324a的材料可為相同的或不同的。
參照圖2D及圖2E，在第三介電層314a及第三導電圖案324a上形成第四介電層316a。在一些實施例中，可首先在第三介電層314a及第三導電圖案324a上形成介電材料層316。隨後，將介電材料層316圖案化以形成具有多個開口O316a 的第四介電層316a。開口O316a 暴露出位於第四介電層316a下的第三導電圖案324a。在一些實施例中，可通過微影製程及蝕刻製程來將介電材料層316圖案化。在一些實施例中，第四介電層316a的材料不同於第一介電層310a的材料、第二介電層312a的材料及第三介電層314a的材料。舉例來說，第四介電層316a的材料可包括例如環氧樹脂或酚醛樹脂等模塑化合物材料。在一些實施例中，第四介電層316a還可包括填料（filler）。在一些實施例中，第四介電層316a的材料可包括聚醯亞胺、環氧樹脂、丙烯酸樹脂、酚醛樹脂、苯並環丁烯（BCB）、聚苯并噁唑（PBO）或任何其他適合的聚合物系介電材料。在一些實施例中，第四介電層316a的楊氏模數高於第一介電層310a的楊氏模數、第二介電層312a的楊氏模數及第三介電層314a的楊氏模數。舉例來說，第四介電層316a的楊氏模數可介於0.5 GPa至150 GPa的範圍內。
參照圖2F，在一些實施例中，在第四介電層316a上形成覆蓋開口O316a 的晶種層410。如圖2F中所示，以覆蓋開口O316a 的輪廓的共形方式形成晶種層410。也就是說，晶種層410延伸到開口O316a 中從而覆蓋開口O316a 的底表面及側壁。晶種層410可通過例如濺鍍製程（sputtering process）、物理氣相沉積（physical vapor deposition；PVD）製程等來形成。在一些實施例中，晶種層410可包含例如銅、鈦銅合金、或其他適合的材料選擇。
參照圖2G，在晶種層410上形成光阻圖案層PR。在一些實施例中，光阻圖案層PR暴露出位於開口O316a 中的晶種層410且暴露出晶種層410的位於第四介電層316a上及開口O316a 周圍的至少一部分。
參照圖2H，在一些實施例中，在開口O316a 內的晶種層410上形成導電柱420。在一些實施例中，將導電材料（圖中未繪示）沉積到被暴露出的晶種層410上以形成導電柱420。隨後，將焊料材料430沉積到導電柱420上。導電柱420及焊料材料430位於光阻圖案層PR的開口內。換句話說，導電柱420及焊料材料430是使用光阻圖案層PR作為罩幕而形成。在一些實施例中，導電材料及焊料材料430可通過鍍覆製程來形成。所述鍍覆製程為例如電鍍、無電鍍覆（electroless-plating）、浸鍍（immersion plating）等。在一些實施例中，導電材料包括例如銅、銅合金等。
參照圖2I，移除光阻圖案層PR且暴露出晶種層410的未被導電柱420及焊料材料430覆蓋的部分。可通過例如蝕刻製程、灰化製程（ashing process）、或其他適合的移除製程來移除/剝除光阻圖案層PR。
參照圖2J，移除未被導電柱420及焊料材料430覆蓋的晶種層410，以得到夾置在導電柱420與第四介電層316a之間及導電柱420與第三導電圖案324a之間的晶種層410a。可通過蝕刻製程來移除晶種層410的被暴露出的部分。在一些實施例中，導電柱420的材料可不同於晶種層410的材料，因而可通過選擇性蝕刻（selective etching）來移除晶種層410的被暴露出的部分。在一些實施例中，可將導電柱420劃分成第一部分P1及第二部分P2。第一部分P1嵌置在第四介電層316a中，且第二部分P2位於第四介電層316a上。如圖2J中所示，晶種層410a位於第二部分P2與第四介電層316a之間、第一部分P1與第四介電層316a之間及第一部分P1與第三導電圖案324a之間。參照圖2K，對焊料材料430執行回焊製程（reflow process）以使焊料材料430轉變成導電凸塊500。如圖2K中所示，在回焊製程之後導電凸塊500呈現半球體形狀。然而，本發明實施例並非僅限於此。在一些替代性實施例中，在回焊製程之後導電凸塊500可呈其他形狀。
圖3A至圖3J是以區R為著重點繪示根據本發明一些替代性實施例的示例性封裝的製造方法的各製程的示意性放大剖面圖。圖3A至圖3J繪示用於在包封體200a及晶粒100a上形成與圖1C至圖1D中所繪示結構相似的重佈線結構300、導電柱420、及導電凸塊500的詳細製程步驟。參照圖3A，在晶粒100a及包封體200a上依序形成第一介電層310a、第一導電圖案320a、第二介電層312a、第二導電圖案322a、第三介電層314a及第三導電圖案324a。用於形成這些元件的製程步驟與圖2A至圖2C中所示的製程步驟類似，因而本文中不再對其予以贅述。
參照圖3B，在第三介電層314a及第三導電圖案324a上形成第一晶種層410。第一晶種層410可通過例如濺鍍製程、物理氣相沉積（PVD）製程等來形成。在一些實施例中，第一晶種層410可包含例如銅、鈦銅合金、或其他適合的材料選擇。
參照圖3C，在第一晶種層410上形成第一光阻圖案層PR1。在一些實施例中，第一光阻圖案層PR1暴露出第一晶種層410的位於第三導電圖案324a上的至少一部分。
參照圖3D，使用第一光阻圖案層PR1作為罩幕將第一導電材料420a沉積到被暴露出的第一晶種層410上。在一些實施例中，第一導電材料420a可通過鍍覆製程來形成。所述鍍覆製程為例如電鍍、無電鍍覆、浸鍍等。在一些實施例中，第一導電材料420a包括例如銅、銅合金等。
參照圖3D及圖3E，移除第一光阻圖案層PR1且暴露出第一晶種層410的未被第一導電材料420a覆蓋的部分。可通過例如蝕刻製程、灰化製程、或其他適合的移除製程來移除/剝除第一光阻圖案層PR1。隨後，移除未被第一導電材料420a覆蓋的第一晶種層410，以得到夾置在第一導電材料420a與第三導電圖案324a之間的第一晶種層410a。可通過蝕刻製程來移除第一晶種層410的被暴露出的部分。
參照圖3F，在第一晶種層410a及第一導電材料420a周圍形成第四介電層316a。與圖2A至圖2K所示的實施例類似，在一些實施例中，第四介電層316a的材料不同於第一介電層310a的材料、第二介電層312a的材料及第三介電層314a的材料。舉例來說，第四介電層316a的楊氏模數高於第一介電層310a的楊氏模數、第二介電層312a的楊氏模數及第三介電層314a的楊氏模數。在一些實施例中，基於較高的楊氏模數，可將重佈線結構300的第四介電層316a稱作抗應力層。
參照圖3G，可在第四介電層316a及第一導電材料420a上形成第二晶種層412。隨後，在第二晶種層412上形成第二光阻圖案層PR2。在一些實施例中，第二光阻圖案層PR2暴露出第二晶種層412的位於第一導電材料420a上的至少一部分。第二晶種層412可類似於第一晶種層410且第二光阻圖案層PR2可類似於第一光阻圖案層PR1，因而本文中不再對其予以贅述。
參照圖3H，使用第二光阻圖案層PR2作為罩幕將第二導電材料420b及焊料材料430沉積到被暴露出的第二晶種層412上。第二導電材料420b可類似於第一導電材料410b，因而本文中不再對其予以贅述。
參照圖3H及圖3I，移除第二光阻圖案層PR2且暴露出第二晶種層412的未被第二導電材料420b及焊料材料430覆蓋的部分。可通過例如蝕刻製程、灰化製程、或其他適合的移除製程來移除/剝除第二光阻圖案層PR2。隨後，移除未被第二導電材料420b及焊料材料430覆蓋的第二晶種層412，以得到夾置在第二導電材料420b與第一導電材料420a之間及第二導電材料420b與第四介電層316a之間的第二晶種層（附加晶種層）412a。可通過蝕刻製程來移除第二晶種層412的被暴露出的部分。參照圖3I，第一導電材料420a及第二導電材料420b構成導電柱420。在一些實施例中，可將第一導電材料420a稱作導電柱420的嵌置在第四介電層316a中的第一部分P1。另一方面，可將第二導電材料420b稱作導電柱420的位於第四介電層316a上的第二部分P2。第一晶種層410a位於第一部分P1與第三導電圖案324a之間。第二晶種層412a位於第一部分P1與第二部分P2之間及第四介電層316a與第二部分P2之間。參照圖3J，對焊料材料430執行回焊製程以使焊料材料430轉變成導電凸塊500。
圖4A至圖4J是以圖1C中的區R為著重點繪示根據本發明一些替代性實施例的示例性封裝的製造方法的各製程的示意性放大剖面圖。圖4A至圖4J繪示用於在包封體200a及晶粒100a上形成與圖1C至圖1D中所繪示結構類似的重佈線結構300、緩衝層600a、導電柱420、及導電凸塊500的詳細製程步驟。參照圖4A，在晶粒100a及包封體200a上依序形成第一介電層310a、第一導電圖案320a、第二介電層312a、第二導電圖案322a、第三介電層314a及第三導電圖案324a。用於形成這些元件的製程步驟與圖2A至圖2C中所示製程步驟類似，因而本文中不再對其予以贅述。
參照圖4B及圖4C，在第三介電層314a及第三導電圖案324a上形成第四介電層316a。可首先在第三介電層314a及第三導電圖案324a上形成介電材料層316。隨後，將介電材料層316圖案化以形成具有多個開口O316a 的第四介電層316a。開口O316a 暴露出位於第四介電層316a下的第三導電圖案324a的至少一部分。在一些實施例中，可通過微影製程及蝕刻製程來將介電材料層316圖案化。在一些實施例中，第四介電層316a的材料相同於第一介電層310a的材料、第二介電層312a的材料及第三介電層314a的材料。在一些實施例中，第四介電層316a被稱作在與晶粒100a的頂表面垂直的方向上距晶粒100a最遠的介電層。類似地，第三導電圖案324a被稱作在與晶粒100a的頂表面垂直的方向上距晶粒100a最遠的導電圖案。在一些實施例中，第一介電層310a、第二介電層312a、第三介電層314a、第四介電層316a、第一導電圖案320a、第二導電圖案322a及第三導電圖案324a構成重佈線結構300。
參照圖4D，在第四介電層316a及第三導電圖案324a上形成緩衝層600。在一些實施例中，緩衝層600的材料不同於第一介電層310a的材料、第二介電層312a的材料、第三介電層314a的材料及第四介電層316a的材料。舉例來說，緩衝層600的材料可包括例如環氧樹脂或酚醛樹脂等模塑化合物材料。在一些實施例中，緩衝層600還可包括填料。在一些實施例中，緩衝層600的材料可包括聚醯亞胺、環氧樹脂、丙烯酸樹脂、酚醛樹脂、苯並環丁烯（BCB）、聚苯并噁唑（PBO）或任何其他適合的聚合物系介電材料。在一些實施例中，緩衝層600的楊氏模數高於第一介電層310a的楊氏模數、第二介電層312a的楊氏模數、第三介電層314a的楊氏模數及第四介電層316a的楊氏模數。舉例來說，緩衝層600的楊氏模數介於0.5 GPa至150 GPa的範圍內。另一方面，第一介電層310a的楊氏模數、第二介電層312a的楊氏模數、第三介電層314a的楊氏模數及第四介電層316a的楊氏模數介於0.1 GPa至100 GPa的範圍內。在特定實施例中，緩衝層600的楊氏模數對第一介電層310a、第二介電層312a、第三介電層314a或第四介電層316a的楊氏模數的比率介於1.05至100的範圍內。當楊氏模數的比率低於1.05時，緩衝層600不能夠承受住從導電柱420所產生的應力，而使重佈線結構300中的導電圖案變形。另一方面，當楊氏模數的比率超過100時，緩衝層600將呈現與純矽的硬度相似的硬度，由此增大加工難度。在一些實施例中，緩衝層600的厚度大於第一介電層310a的厚度、第二介電層312a的厚度、第三介電層314a的厚度或第四介電層316a的厚度。在一些實施例中，較高的楊氏模數使得緩衝層600能夠減輕或阻擋從導電柱420施加到下伏重佈線結構300的應力，從而保護重佈線結構300中的導電圖案不因在裝配製程及/或熱製程期間產生的應力而損壞。換句話說，具有較高楊氏模數的緩衝層600有助於減輕重佈線結構300中的精細線變形問題。因此，在一些實施例中，可將緩衝層600稱作抗應力層。
參照圖4E，將緩衝層600圖案化以形成具有多個開口O600a 的緩衝層600a。開口O600a 大於開口O316a ，以使得開口O600a 暴露出第四介電層316a的開口O316a 及第四介電層316a的至少一部分。
參照圖4F，在一些實施例中，在緩衝層600a上形成覆蓋開口O316a 及開口O600a 的晶種層410。如圖4F中所示，以覆蓋開口O316a 及開口O600a 的輪廓的共形方式形成晶種層410。也就是說，晶種層410延伸到開口O316a 及開口O600a 中從而覆蓋開口O316a 及開口O600a 的底表面及側壁。晶種層410可通過例如濺鍍製程、物理氣相沉積（PVD）製程等來形成。在一些實施例中，晶種層410可包含例如銅、鈦銅合金、或其他適合的材料選擇。
參照圖4G，在晶種層410上形成光阻圖案層PR。在一些實施例中，光阻圖案層PR暴露出位於開口O316a 及開口O600a 中的晶種層410。光阻圖案層PR還暴露出晶種層410的位於緩衝層600上及開口O600a 周圍的至少一部分。
參照圖4H，在一些實施例中，在開口O316a 及開口O600a 內的晶種層410上形成導電柱420。在一些實施例中，將導電材料（圖中未繪示）沉積到被暴露出的晶種層410上以形成導電柱420。隨後，將焊料材料430沉積到導電柱420上。在一些實施例中，導電材料及焊料材料430可通過鍍覆製程來形成。所述鍍覆製程為例如電鍍、無電鍍覆、浸鍍等。在一些實施例中，導電材料包括例如銅、銅合金等。
參照圖4H及圖4I，移除光阻圖案層PR且暴露出晶種層410的未被導電柱420及焊料材料430覆蓋的部分。可通過例如蝕刻製程、灰化製程、或其他適合的移除製程來移除/剝除光阻圖案層PR。隨後，移除未被導電柱420及焊料材料430覆蓋的晶種層410，以得到夾置在導電柱420與緩衝層600a之間、導電柱420與第四介電層316a之間及導電柱420與第三導電圖案324a之間的晶種層410a。可通過蝕刻製程來移除晶種層410的被暴露出的部分。參照圖4J，對焊料材料430執行回焊製程以使焊料材料430轉變成導電凸塊500。
圖5A是以區R為著重點繪示根據本發明一些替代性實施例的示例性封裝的示意性放大剖面圖。圖5B繪示圖5A中的緩衝層600a及導電柱420的示意性俯視圖。除緩衝層600a的位置或覆蓋率（coverage）以外，圖5A中所示結構類似於圖4J中所示結構。換句話說，可通過與圖4A至圖4J中所示的製程步驟類似的製程步驟來獲得圖5A中所示的結構，因而本文中不再對其予以贅述。在一些實施例中，可執行移除緩衝層600a的位於第四介電層316a上的至少一部分的額外步驟，以獲得環繞導電柱420的環形緩衝層600a。參照圖5A及圖5B，出於說明目的，將導電柱420繪示為圓形導電柱且將環繞每一導電柱420的環形緩衝層600a繪示為圓環形甜甜圈結構以作實例，但並非旨在限制本發明實施例的範圍。在一些實施例中，每一導電柱420均具有為W1的最大直徑。另一方面，環形緩衝層600a的邊緣與導電柱420的側壁之間具有為W2的距離。在一些實施例中，W2對W1（W2/W1）的比率介於0.01至0.6的範圍內。儘管圖5B中導電柱420被繪示為圓柱體且環繞所述柱的緩衝層具有對應形狀，然而可採用各種形狀及不同的相容形狀，且本發明實施例並非僅限於此。在一些替代性實施例中，導電柱420可為橢圓柱體或甚至為正方形柱體或多邊形柱體。此外，儘管圖5A繪示環形緩衝層600a的外側壁為直的，然而本發明實施例並非僅限於此。在一些替代性實施例中，環形緩衝層600a的外側壁可傾斜以進一步增強緩衝層600a的強度。
圖6A至圖6I是以圖1C中的區R為著重點繪示根據本發明一些替代性實施例的示例性封裝的製造方法的各製程的示意性放大剖面圖。圖6A至圖6I繪示用於在包封體200a及晶粒100a上形成與圖1C至圖1D中所繪示結構類似的重佈線結構300、緩衝層600a、導電柱420、及導電凸塊500的詳細製程步驟。參照圖6A至圖6C，所繪示的製程步驟類似於圖4A至圖4C中的製程步驟，因而本文中不再對其予以贅述。
參照圖6D，在第四介電層316a及第三導電圖案324a上形成緩衝層600a。在一些實施例中，緩衝層600a延伸到開口O316a 中從而覆蓋開口O316a 的側壁SW316a 。緩衝層600a暴露出開口O316a 的底表面的至少一部分。換句話說，緩衝層600a暴露出第三導電圖案324a的至少一部分。在一些實施例中，緩衝層600的材料不同於第一介電層310a的材料、第二介電層312a的材料、第三介電層314a的材料及第四介電層316a的材料。舉例來說，緩衝層600a的材料可包括例如環氧樹脂或酚醛樹脂等模塑化合物材料。在一些實施例中，緩衝層600a還可包括填料。在一些實施例中，緩衝層600a的材料可包括聚醯亞胺、環氧樹脂、丙烯酸樹脂、酚醛樹脂、苯並環丁烯（BCB）、聚苯并噁唑（PBO）或任何其他適合的聚合物系介電材料。在一些實施例中，緩衝層600a的楊氏模數高於第一介電層310a的楊氏模數、第二介電層312a的楊氏模數、第三介電層314a的楊氏模數及第四介電層316a的楊氏模數。舉例來說，緩衝層600a的楊氏模數介於0.5 GPa至150 GPa的範圍內。另一方面，第一介電層310a的楊氏模數、第二介電層312a的楊氏模數、第三介電層314a的楊氏模數及第四介電層316a的楊氏模數介於0.1 GPa至100 GPa的範圍內。在特定實施例中，緩衝層600a的楊氏模數對第一介電層310a、第二介電層312a、第三介電層314a或第四介電層316a的楊氏模數的比率介於1.05至100的範圍內。當楊氏模數的比率低於1.05時，緩衝層600a不能夠承受住從導電柱420所產生的應力，而使重佈線結構300中的導電圖案變形。另一方面，當楊氏模數的比率超過100時，緩衝層600a將呈現與純矽相似的硬度，由此增大加工難度。在一些實施例中，緩衝層600a的厚度大於第一介電層310a的厚度、第二介電層312a的厚度、第三介電層314a的厚度或第四介電層316a的厚度。在一些實施例中，較高的楊氏模數使得緩衝層600a能夠減輕或阻擋從導電柱420施加到下伏重佈線結構300的應力，從而保護重佈線結構300中的導電圖案不因在裝配製程及/或熱製程期間產生的應力而損壞。換句話說，具有較高楊氏模數的緩衝層600a有助於減輕重佈線結構300中的精細線變形問題。因此，在一些實施例中，可將緩衝層600a稱作抗應力層。
參照圖6E，在一些實施例中，在緩衝層600a上及被暴露出的第三導電圖案324a上形成晶種層410。如圖6E中所示，以共形方式形成晶種層410。也就是說，晶種層410延伸到開口O316a 中以覆蓋位於開口O316a 中的緩衝層600a及覆蓋被暴露出的第三導電圖案324a。晶種層410可通過例如濺鍍製程、物理氣相沉積（PVD）製程等來形成。在一些實施例中，晶種層410可包含例如銅、鈦銅合金、或其他適合的材料選擇。
參照圖6F，在晶種層410上形成光阻圖案層PR。在一些實施例中，光阻圖案層PR暴露出位於開口O316a 中的晶種層410。光阻圖案層PR還暴露出晶種層410的位於緩衝層600a上的至少一部分。在一些實施例中，光阻圖案層PR可包含感光性樹脂。
參照圖6G，在一些實施例中，在緩衝層600a上的晶種層410上形成導電柱420。在一些實施例中，將導電材料（圖中未繪示）沉積到被暴露出的晶種層410上以形成導電柱420。導電柱420接觸位於第三導電圖案324a上的晶種層410，以實現與重佈線結構300的電性連接。隨後，將焊料材料430沉積到導電柱420上。在一些實施例中，導電材料及焊料材料430可通過鍍覆製程來形成。所述鍍覆製程為例如電鍍、無電鍍覆、浸鍍等。在一些實施例中，導電材料包括例如銅、銅合金等。
參照圖6G及圖6H，移除光阻圖案層PR且暴露出晶種層410的未被導電柱420及焊料材料430覆蓋的部分。可通過例如蝕刻製程、灰化製程、或其他適合的移除製程來移除/剝除光阻圖案層PR。隨後，移除未被導電柱420及焊料材料430覆蓋的晶種層410，以得到夾置在導電柱420與緩衝層600a之間及導電柱420與第三導電圖案324a之間的晶種層410a。可通過蝕刻製程來移除晶種層410的被暴露出的部分。參照圖6I，對焊料材料430執行回焊製程以使焊料材料430轉變成導電凸塊500。
圖7A是以區R為著重點繪示根據本發明一些替代性實施例的示例性封裝的示意性放大剖面圖。圖7B繪示圖7A中的緩衝層600a及導電柱420的示意性俯視圖。除緩衝層600a的位置或覆蓋率以外，圖7A中所示結構類似於圖6I中所示結構。換句話說，可通過與圖6A至圖6I中所示的製程步驟類似的製程步驟來獲得圖7A中所示的結構，因而本文中不再對其予以贅述。在一些實施例中，可執行移除緩衝層600a的位於第四介電層316a上的至少一部分的額外步驟，以獲得環繞導電柱420的環形緩衝層600a。參照圖7A及圖7B，出於說明目的，將導電柱420繪示為圓形導電柱且將環繞每一導電柱420的環形緩衝層600a繪示為圓環形甜甜圈結構以作實例，但並非旨在限制本發明實施例的範圍。在一些實施例中，每一導電柱420均具有為W1的最大直徑。另一方面，環形緩衝層600a的邊緣與導電柱420的側壁之間具有為W2的距離。在一些實施例中，W2對W1（W2/W1）的比率介於0.01至0.6的範圍內。儘管圖7B中導電柱420被繪示為圓柱體且環繞所述柱的緩衝層具有對應形狀，然而可採用各種形狀及不同的相容形狀，且本發明實施例並非僅限於此。在一些替代性實施例中，導電柱420可為橢圓柱體或甚至為正方形柱體或多邊形柱體。此外，儘管圖7A說明環形緩衝層600a的外側壁為直的，然而本發明實施例並非僅限於此。在一些替代性實施例中，環形緩衝層600a的外側壁可傾斜以進一步增強緩衝層600a的強度。
圖8繪示包括圖1F中的積體扇出型封裝10的堆疊封裝結構的示意圖。參照圖8，可在基板20上堆疊積體扇出型封裝10。在一些實施例中，基板20可為上面形成有被動裝置或微機電系統（micro-electro-mechanical system；MEMS）裝置的半導體基板。在一些替代性實施例中，基板20可為中介層（interposer）。積體扇出型封裝10可通過導電柱420及導電凸塊500與基板20電性連接。在一些實施例中，上面形成有積體扇出型封裝10的基板20可進一步設置在印刷電路板30上以形成半導體裝置。積體扇出型封裝10可通過基板20電性連接到印刷電路板30。
根據本發明的一些實施例，一種積體扇出型封裝包括晶粒、包封體、重佈線結構、多個導電柱、晶種層、及多個導電凸塊。所述包封體包封所述晶粒。所述重佈線結構位於所述晶粒及所述包封體上。所述重佈線結構與所述晶粒電性連接且包括依序堆疊的多個介電層以及夾置在所述介電層之間的多個導電圖案。距所述晶粒最遠的所述介電層的楊氏模數高於所述介電層中其餘介電層中的每一者的楊氏模數。所述導電圖案彼此電性連接。所述導電柱設置在所述重佈線結構上且與所述重佈線結構電性連接。所述晶種層位於所述導電柱與所述重佈線結構之間。所述導電凸塊設置在所述導電柱上。
根據本發明的一些實施例，距所述晶粒最遠的所述介電層包含模塑化合物材料。
根據本發明的一些實施例，所述導電柱中的每一者包括第一部分及第二部分，所述第一部分嵌置在距所述晶粒最遠的所述介電層中，所述第二部分位於距所述晶粒最遠的所述介電層上。
根據本發明的一些實施例，所述積體扇出型封裝進一步包括位於所述第一部分與所述第二部分之間以及位於距所述晶粒最遠的所述介電層與所述第二部分之間的附加晶種層。
根據本發明的一些實施例，所述晶種層位於所述第二部分與距所述晶粒最遠的所述介電層之間、所述第一部分與距所述晶粒最遠的所述介電層之間以及所述第一部分與距所述晶粒最遠的所述導電圖案之間。
根據本發明的一些實施例，距所述晶粒最遠的所述介電層的所述楊氏模數對所述介電層中所述其餘介電層的所述楊氏模數的比率介於1.05至100的範圍內。
根據本發明的一些替代性實施例，一種積體扇出型封裝包括晶粒、包封體、重佈線結構、緩衝層、多個導電柱、晶種層、及多個導電凸塊。所述包封體包封所述晶粒。所述重佈線結構位於所述晶粒及所述包封體上。所述重佈線結構與所述晶粒電性連接且包括依序堆疊的多個介電層以及夾置在所述介電層之間的多個導電圖案。所述緩衝層位於所述重佈線結構上。所述緩衝層的楊氏模數高於所述重佈線結構的所述介電層中的每一者的楊氏模數。所述導電柱設置在所述緩衝層上且與所述重佈線結構電性連接。所述晶種層位於所述導電柱與所述緩衝層之間以及所述導電柱與所述重佈線結構之間。所述導電凸塊設置在所述導電柱上。
根據本發明的一些實施例，距所述晶粒最遠的所述介電層具有多個第一開口，所述多個第一開口暴露出距所述晶粒最遠的所述導電圖案的至少一部分，所述緩衝層具有多個第二開口，所述多個第二開口暴露出所述多個第一開口，且所述多個第二開口大於所述多個第一開口。
根據本發明的一些實施例，所述緩衝層是環繞所述多個導電柱的環形結構且暴露出距所述晶粒最遠的所述介電層的至少一部分。
根據本發明的一些實施例，所述環形緩衝層的邊緣與所述多個導電柱的側壁之間的距離對所述多個導電柱的最大直徑的比率介於0.01至0.6的範圍內。
根據本發明的一些實施例，距所述晶粒最遠的所述介電層具有多個第一開口，所述多個第一開口暴露出距所述晶粒最遠的所述導電圖案的至少一部分，且所述緩衝層延伸到所述多個第一開口中以覆蓋所述多個第一開口的側壁。
根據本發明的一些實施例，所述多個導電柱接觸位於距所述晶粒最遠的所述導電圖案上的所述晶種層。
根據本發明的一些實施例，所述緩衝層是環繞所述多個導電柱的環形結構且暴露出距所述晶粒最遠的所述介電層的至少一部分。
根據本發明的一些實施例，所述緩衝層的邊緣與所述多個導電柱的側壁之間的距離對所述多個導電柱的最大直徑的比率介於0.01至0.6的範圍內。
根據本發明的一些實施例，一種積體扇出型封裝的製造方法至少包括以下步驟。提供晶粒。以包封體包封所述晶粒。在所述晶粒及所述包封體上形成多個介電層。形成多個導電圖案。所述導電圖案的至少一部分夾置在所述介電層之間。所述導電圖案彼此電性連接。在所述介電層上形成抗應力層。所述抗應力層的楊氏模數高於所述介電層中的每一者的楊氏模數。在所述抗應力層上形成多個導電柱。在所述導電柱上形成多個導電凸塊。
根據本發明的一些實施例，所述形成所述多個導電柱的步驟至少包括以下步驟。在所述抗應力層中形成多個開口，以暴露出距所述晶粒最遠的所述導電圖案。在所述多個開口中及所述抗應力層上形成晶種層。在所述晶種層上形成光阻圖案層，其中所述光阻圖案層暴露出位於所述多個開口中的所述晶種層以及位於所述抗應力層上的所述晶種層的至少一部分。使用所述光阻圖案層作為罩幕在所述晶種層上形成導電材料。移除所述光阻圖案層。移除被所述導電材料暴露出的所述晶種層。
根據本發明的一些實施例，所述形成所述多個導電柱的步驟以及所述形成所述抗應力層的步驟至少包括以下步驟。在距所述晶粒最遠的所述介電層上以及在距所述晶粒最遠的所述導電圖案上形成第一晶種層。在所述第一晶種層上形成第一光阻圖案層，其中所述第一光阻圖案層暴露出位於距所述晶粒最遠的所述導電圖案上的所述第一晶種層的至少一部分。使用所述第一光阻圖案層作為罩幕在所述第一晶種層上形成第一導電材料。移除所述第一光阻圖案層。移除被所述第一導電材料暴露出的所述第一晶種層。形成圍繞所述第一晶種層及所述第一導電材料的所述抗應力層。在所述第一導電材料及所述抗應力層上形成第二晶種層。在所述第二晶種層上形成第二光阻圖案層，其中所述第二光阻圖案層暴露出位於所述第一導電材料上的所述第二晶種層的至少一部分。使用所述第二光阻圖案層作為罩幕在所述第二晶種層上形成第二導電材料。移除所述第二光阻圖案層。移除被所述第二導電材料暴露出的所述第二晶種層。
根據本發明的一些實施例，所述形成所述多個導電柱的步驟至少包括以下步驟。在距所述晶粒最遠的所述介電層中形成多個第一開口，其中所述多個第一開口暴露出距所述晶粒最遠的所述導電圖案的至少一部分。在所述抗應力層中形成多個第二開口，其中所述多個第二開口暴露出所述多個第一開口及距所述晶粒最遠的所述介電層的至少一部分。在所述多個第一開口及所述多個第二開口中以及所述抗應力層上形成晶種層。在所述晶種層上形成光阻圖案層，其中所述光阻圖案層暴露出位於所述多個第一開口及所述多個第二開口中的所述晶種層且暴露出位於所述抗應力層上的所述晶種層的至少一部分。使用所述光阻圖案層作為罩幕在所述晶種層上形成導電材料。移除所述光阻圖案層。移除被所述導電材料暴露出的所述晶種層。
根據本發明的一些實施例，所述形成所述多個導電柱的步驟以及所述形成所述抗應力層的步驟至少包括以下步驟。在距所述晶粒最遠的所述介電層中形成多個第一開口，其中所述多個第一開口暴露出距所述晶粒最遠的所述導電圖案的至少一部分。在距所述晶粒最遠的所述介電層上以及在所述多個第一開口中形成所述抗應力層，以使得所述抗應力層覆蓋所述多個第一開口的側壁。在所述抗應力層上及距所述晶粒最遠的被暴露出的所述導電圖案上形成晶種層。在所述晶種層上形成光阻圖案層，其中所述光阻圖案層暴露出位於所述多個第一開口中的所述晶種層且暴露出位於所述抗應力層上的所述晶種層的至少一部分。使用所述光阻圖案層作為罩幕在所述晶種層上形成導電材料。移除所述光阻圖案層。移除被所述導電材料暴露出的所述晶種層。
根據本發明的一些實施例，所述積體扇出型封裝的製造方法進一步包括移除所述抗應力層的至少一部分，以使得所述抗應力層是環繞所述多個導電柱的環形結構。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本發明的各個方面。所屬領域中的技術人員應知，其可容易地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不背離本發明的精神及範圍，而且他們可在不背離本發明的精神及範圍的條件下對其作出各種改變、代替、及變更。
10‧‧‧積體扇出型封裝
20‧‧‧基板
30‧‧‧印刷電路板
100、100a‧‧‧晶粒
110‧‧‧半導體基板
120‧‧‧導電接墊
130‧‧‧鈍化層
140‧‧‧後鈍化層
150、150a‧‧‧導電柱體
160、160a‧‧‧保護層
200‧‧‧包封材料
200a‧‧‧包封體
300‧‧‧重佈線結構
310、316‧‧‧介電材料層
310a‧‧‧第一介電層
312a‧‧‧第二介電層
314a‧‧‧第三介電層
316a‧‧‧第四介電層
320a‧‧‧第一導電圖案
322a‧‧‧第二導電圖案
324a‧‧‧第三導電圖案
410、410a‧‧‧晶種層
412、412a‧‧‧第二晶種層
420‧‧‧導電柱
420a‧‧‧第一導電材料
420b‧‧‧第二導電材料
430‧‧‧焊料材料
500‧‧‧導電凸塊
600、600a‧‧‧緩衝層
C‧‧‧載板
DB‧‧‧剝離層
O310a、O316a、O600a‧‧‧開口
P1‧‧‧第一部分
P2‧‧‧第二部分
PR‧‧‧光阻圖案層
PR1‧‧‧第一光阻圖案層
PR2‧‧‧第二光阻圖案層
R‧‧‧區
SW316a‧‧‧側壁
W1‧‧‧最大直徑
W2‧‧‧距離
圖1A至圖1F繪示根據本發明一些實施例的製造積體扇出型封裝的方法的各製程的示意性剖面圖。 圖2A至圖2K是以區R為著重點繪示根據本發明一些實施例的示例性封裝的製造方法的各製程的示意性放大剖面圖。 圖3A至圖3J是以區R為著重點繪示根據本發明一些替代性實施例的示例性封裝的製造方法的各製程的示意性放大剖面圖。 圖4A至圖4J是以區R為著重點繪示根據本發明一些替代性實施例的示例性封裝的製造方法的各製程的示意性放大剖面圖。 圖5A是以區R為著重點繪示根據本發明一些替代性實施例的示例性封裝的示意性放大剖面圖。 圖5B繪示圖5A中所示的緩衝層及導電柱的示意性俯視圖。 圖6A至圖6I是以區R為著重點繪示根據本發明一些替代性實施例的示例性封裝的製造方法的各製程的示意性放大剖面圖。 圖7A是以區R為著重點繪示根據本發明一些替代性實施例的示例性封裝的示意性放大剖面圖。 圖7B繪示圖7A中所示的緩衝層及導電柱的示意性俯視圖。 圖8繪示包括圖1F中的積體扇出型封裝的堆疊封裝結構的示意圖。

Claims (1)

  1. 一種積體扇出型封裝，包括： 晶粒； 包封體，包封所述晶粒； 重佈線結構，位於所述晶粒及所述包封體上，其中所述重佈線結構與所述晶粒電性連接且包括： 依序堆疊的多個介電層，其中距所述晶粒最遠的所述介電層的楊氏模數高於所述介電層中其餘介電層中的每一者的楊氏模數；以及 多個導電圖案，夾置在所述多個介電層之間，其中所述多個導電圖案彼此電性連接； 多個導電柱，設置在所述重佈線結構上且與所述重佈線結構電性連接； 晶種層，位於所述多個導電柱與所述重佈線結構之間；以及 多個導電凸塊，設置在所述多個導電柱上。
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