CN114068459A - 半导体封装元件的凸块结构 - Google Patents

半导体封装元件的凸块结构 Download PDF

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CN114068459A
CN114068459A CN202010972565.1A CN202010972565A CN114068459A CN 114068459 A CN114068459 A CN 114068459A CN 202010972565 A CN202010972565 A CN 202010972565A CN 114068459 A CN114068459 A CN 114068459A
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layer
bump
bump structure
buffer layer
metal
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苏志彦
林俊德
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Powertech Technology Inc
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Powertech Technology Inc
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明公开一种半导体元件的凸块结构，该半导体封装元件的凸块结构形成于一第一介电层上，又该第一介电层形成于一金属层上，并对应该金属层部分形成有一开口，该半导体封装元件的凸块结构包括一凸块下金属层、一缓冲层及一金属凸块；其中该凸块下金属层形成于外露在开口的金属层部分、开口内壁及介电层顶面，供该金属凸块形成于其中；本发明藉由在位于该介电层顶面的凸块下金属层的部分及介电层顶面之间形成该缓冲层，能够有效的吸收因为凸块结构中多层材料的热膨胀系数不同，于接合步骤中所产生的热应力，避免热应力于该凸块结构于接合步骤后产生裂纹。

Description

半导体封装元件的凸块结构
技术领域
本发明涉及一种半导体封装元件，尤其涉及一种半导体封装元件的凸块结构。
背景技术
凸块结构常见于半导体封装元件中，例如形成于覆晶封装元件的芯片上或形成于重布线层上，凸块结构可提供良好的导电率，以覆晶封装元件的芯片来说，多个凸块结构形成于芯片的金属垫上，供芯片直接接合于载板上，相较于打线接合的半导体封装元件尺寸更为减缩。
然而，随着芯片厚度愈来愈薄，如图7所示，芯片40以其上凸块结构50与载板60回焊接合后，可看出芯片40呈现弯曲状，究其原因在于：因为凸块结构50的最外一层为焊锡层51，为顺利焊接于载板60上，该些凸块结构需要加热至220℃至240℃将焊锡层51熔融，在加温至冷却的过程中，常常会因为凸块结构50中多层材料的热膨胀系数不同，如图8A所示，凸块结构50与芯片40的接合处52会出现不同的热应力，导致凸块结构50与芯片40之间产生扭力以及弯曲等热应力问题；再如图8B所示，不同的应力会使得凸块结构50与芯片40不同接合处出现拉伸或压缩现象，最后从凸块结构50与芯片40的接合处52产生裂纹，如图9所示，最严重的裂纹42甚至向内延伸至芯片40的线路层41，破坏芯片40线路。
因此，有必要进一步改良现有技术的凸块结构50。
发明内容
有鉴于上述现有技术的凸块结构的缺陷，本发明的主要发明目的在于提出一种新的半导体封装元件的凸块结构，以解决因为凸块结构的热膨胀系数不同，所产生的热应力造成的裂纹问题。
欲达上述发明的目的所使用的主要技术手段是令该半导体封装元件的凸块结构形成于该半导体封装元件的一第一介电层上，其中该第一介电层形成于一金属层上，并对应该金属层部分形成有一开口，且该介电层具有一第一长度；其中该凸块结构包含：
一凸块下金属层，形成于外露在该开口的金属层部分、该开口内壁及该第一介电层顶面；其中该凸块下金属层形成在该第一介电层顶面的部分具有一第二长度；
一第一缓冲层，形成于该凸块下金属层部分及该第一介电层顶面之间，其中该第一缓冲层具有一第三长度，该第三长度大于该第二长度并小于该第一长度；及
一金属凸块，形成于该凸块下金属层上。
本发明的优点在于，本发明的凸块结构主要在位于该介电层顶面的凸块下金属层的部分及介电层顶面之间进一步形成该缓冲层，藉由该缓冲层有效的吸收因为凸块结构中多层材料的热膨胀系数不同，于接合步骤中所产生的热应力，解决先前技术的凸块结构于接合步骤后产生的裂纹。
以下结合附图和具体实施例对本发明进行详细描述，但不作为对本发明的限定。
附图说明
图1A：为本发明的半导体封装元件的凸块结构的第一实施例的剖视图；
图1B：为本发明的半导体封装元件的凸块结构的第二实施例的剖视图；
图2：为本发明的半导体封装元件的凸块结构的第三实施例的剖视图；
图3：为本发明的半导体封装元件的凸块结构的第四实施例的剖视图；
图4A：为本发明的半导体封装元件的凸块结构的第五实施例的剖视图；
图4B：为本发明的半导体封装元件的凸块结构的第六实施例的剖视图；
图5：为本发明的半导体封装元件的凸块结构的第七实施例的剖视图；
图6：为本发明的半导体封装元件的凸块结构的第八实施例的剖视图；
图7：为现有技术的半导体封装元件的剖视图；
图8A：为现有技术的半导体封装元件的凸块结构与芯片接合处的热应力分布图；
图8B：为现有技术的半导体封装元件的凸块结构的侧面热应力分布图；
图9：为现有技术的局部半导体封装元件的剖视图。
其中，附图标记
10、10a、10b、10c、10d、10e、10f、10g:凸块结构
11、33:金属层
12:绝缘层
13:第一介电层
131:开口
1311:开口的金属层部分
1312:开口内壁
132:第一介电层顶面
14:第一缓冲层
141:第一缓冲层凸出部
15:凸块下金属层
151:凸块下金属层部分
16、16a:金属凸块
161:铜柱层
162:屏障层
163:焊锡层
19:第二缓冲层
20:芯片
30:重布线层
31:钝化层
32:第二介电层
40:芯片
41:线路层
42:裂纹
50:凸块结构
51:焊锡层
52:接合处
60:载板
具体实施方式
本发明针对半导体封装元件的凸块结构进行改良，以下谨以多个实施例配合附图详细说明本发明的详细技术。
首先请参阅图1A所示，为本发明半导体封装元件的凸块结构10的第一实施例；于本实施例中，一凸块结构10形成于芯片20的一对应金属层11上；其中该芯片20及该金属层11的周围部分覆盖有一绝缘层12，再于该绝缘层12及未被该绝缘层12覆盖的金属层11上再形成有一第一介电层13，该第一介电层13对应未被绝缘层12覆盖的金属层11形成有一开口131；较佳地，该绝缘层12的材质为PSV，该第一介电层13材质可为聚酰亚胺(PI，Polyimide)或超低介电材(ELK，Extreme Low-K Dielectric)，并具有一第一长度L1。于本实施例中，该凸块结构10包含有一第一缓冲层14、一凸块下金属层15及一金属凸块16。
上述的第一缓冲层14形成于该第一介电层顶面132，其一端与该第一介电层13的开口内壁1312齐平，该第一缓冲层14具一小于该第一介电层13的第一长度L1的第三长度L3。于本实施例中，该第一缓冲层14的杨氏系数(Young's modulus)较第一介电层13的杨氏系数低。
上述的凸块下金属层15形成于对应开口131的金属层部分1311、开口内壁1312及该第一缓冲层14的顶面，该凸块下金属层15具有一小于该第一缓冲层14的第三长度L3的第二长度L2。因此，上述的第一缓冲层14即形成在该第一介电层顶面132的凸块下金属层15的部分151及该第一介电层顶面132之间。
上述的金属凸块16形成于凸块下金属层15上；于本实施例中，该金属凸块16由下至上依序形成有一铜柱层161、一屏障层162及一焊锡层163(solder paste)；较佳地，屏障层162可为镍。
由上述本发明的第一实施例的说明可知，本实施例的凸块结构10主要在位于第一介电层顶面132的凸块下金属层部分151及第一介电层顶面132之间形成第一缓冲层14，以吸收于接合步骤中所产生的热应力，又更进一步藉由选择杨氏系数较第一介电层13材质的杨氏系数低的材质来形成第一缓冲层14，提高热应力的吸收效果，有效的避免凸块结构10于接合步骤后产生裂纹；该凸块结构10可应用于半导体封装元件的覆晶(flip-chip)结构中。
请参阅图1B所示，为本发明半导体封装元件的凸块结构10a的第二实施例；于本实施例中，该凸块结构10a形成于一芯片20的一重布线层30(RDL，Redistribution Layer)上，该重布线层30在芯片20表面由下至上依序形成有一钝化层31、一第二介电层32、一金属层33及一第一介电层13；其中该第一介电层13对应该金属层33的部分形成有一开口131；又该凸块结构10a形成在对应开口131的金属层33部分上，并包含有一第一缓冲层14、一凸块下金属层15及一金属凸块16a。
本实施例的凸块结构10a的第一介电层13、第一缓冲层14、凸块下金属层15与图1A所示的凸块结构10中的第一介电层13、第一缓冲层14、凸块下金属层15相同，惟上述的金属凸块16a形成于凸块下金属层15上，且该金属凸块16a为一锡球(solder ball)。
由上述本发明的第二实施例的说明可知，本实施例的凸块结构10a主要在位于第一介电层顶面132的凸块下金属层部分151及第一介电层顶面132之间形成第一缓冲层14，以吸收于接合步骤中所产生的热应力，又更进一步藉由选择杨氏系数较第一介电层13材质的杨氏系数低的第一缓冲层14，提高热应力的吸收效果，有效的避免凸块结构10a于接合步骤后产生裂纹。
请参阅图2所示，为本发明半导体封装元件的凸块结构10b的第三实施例；本实施例的凸块结构10b与图1A所示的凸块结构10大致相同，惟该凸块结构10b的第一缓冲层14材质与第一介电层13材质相同；也就是说，本实施例的凸块结构10b在凸块下金属层部分151及第一介电层顶面132之间所形成的第一缓冲层14，是增加该第一介电层132的厚度，通过增厚来吸收于接合步骤中所产生的热应力，可同样避免凸块结构10b于接合步骤后产生裂纹；该凸块结构10b也可应用于半导体封装元件的覆晶结构中。
请参阅图3所示，为本发明半导体封装元件的凸块结构10c的第四实施例；本实施例的凸块结构10c与图1A所示的凸块结构10大致相同，惟该凸块结构10c的第一缓冲层14对应凸块下金属层15的表面朝向凸块下金属层15形成一凸出部141；较佳地，该凸出部141与该金属凸块16对应的侧壁切齐，或如图4A所示，在本发明凸块结构10d的第五实施例中，凸块结构10d的第一缓冲层凸出部141更进一步凸出该金属凸块16对应的侧壁。而在本发明的另一实施例中(图中未示)，凸块结构10c或凸块结构10d的第一缓冲层14材质与第一介电层13材质相同。
由上述本发明的第四及第五实施例的说明可知，本二实施例的凸块结构10c及10d藉由在第一缓冲层14的凸出部141有效增加第一缓冲层14与凸块下金属层15接触面积，使第一缓冲层14与凸块下金属层15的接合度更佳，其中凸块结构10d的第一缓冲层凸出部141更进一步凸出该金属凸块16对应的侧壁，增加该第一缓冲层14厚度；因此，该凸块结构10c及10d通过增加接触面积使第一缓冲层14与凸块下金属层15的接合度更佳及增厚来吸收于接合步骤中所产生的热应力，可同样避免凸块结构10c及10d于接合步骤后产生裂纹；该凸块结构10c及10d也可应用于半导体封装元件的覆晶结构中。
请参阅图4B所示，为本发明半导体封装元件的凸块结构10e的第六实施例；本实施例的凸块结构10e与图1B所示的凸块结构10a大致相同，惟该凸块结构10e的第一缓冲层14具有如本发明第四实施例中的凸出部141或如本发明的第五实施例中的凸出部141(图中未示)。在本发明的另一实施例中(图中未示)，凸块结构10e的第一缓冲层14与第一介电层13材质相同。
由上述本发明的第六实施例的说明可知，本实施例的凸块结构10e藉由在第一缓冲层14的凸出部141有效增加第一缓冲层14与凸块下金属层15接触面积，使第一缓冲层14与凸块下金属层15的接合度更佳，或将该凸出部141更进一步凸出该金属凸块16对应的侧壁，增加该第一缓冲层14厚度；因此，该凸块结构10e通过增加接触面积使第一缓冲层14与凸块下金属层15的接合度更佳及增厚来吸收于接合步骤中所产生的热应力，可同样避免凸块结构10e于接合步骤后产生裂纹；该凸块结构10e也可应用于半导体封装元件的重布线结构当中。
请参阅图5所示，为本发明半导体封装元件的凸块结构10f的第七实施例；本实施例的凸块结构10f与图1A所示的凸块结构10大致相同，惟该凸块结构10f的第一缓冲层14与凸块下金属层15之间进一步形成第二缓冲层19，该第二缓冲层19具有第四长度L4；较佳地，该第二缓冲层19的第四长度L4与第一缓冲层14的第三长度L3相同，或如图6所示，在本发明的第八实施例中，凸块结构10g的第二缓冲层19的第四长度L4小于该第一缓冲层14的第三长度L3并大于该凸块下金属层15的第二长度L2。
由上述本发明的第七及第八实施例的说明可知，本二实施例的凸块结构10f及10g藉由在第一缓冲层14与凸块下金属层15之间进一步形成第二缓冲层19，增加该第一缓冲层14厚度，通过增厚来吸收于接合步骤中所产生的热应力，可同样避免凸块结构10f及10g于接合步骤后产生裂纹；该凸块结构10f及10g也可应用于半导体封装元件的覆晶结构中。
综前诸多实施例说明可知，本发明的凸块结构主要在该介电层顶面的凸块下金属层的部分及第一介电层顶面之间形成第一缓冲层，以增厚该第一介电层来吸收容易集中在凸块结构与介电层之间产生的热应力，减少该凸块结构于接合步骤后因热应力集中而产生的裂纹；此外，本发明可进一步藉由选择杨氏系数较第一介电层材质的杨氏系数低的第一缓冲层，令该第一缓冲层的弹性较第一介电层的弹性高，提升热应力的吸收效果；此外，可再进一步于第一缓冲层上再增加一第二缓冲层，利用厚度或厚度及材质的特性，再提升热应力的吸收效果，更有效地先前技术的凸块结构于接合步骤后产生的裂纹。再者，该第一缓冲层进一步向上形成的凸出部也加强了该第一缓冲层与凸块下金属层之间的接合度。
当然，本发明还可有其它多种实施例，在不背离本发明精神及其实质的情况下，熟悉本领域的技术人员当可根据本发明作出各种相应的改变和变形，但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。

Claims (10)

1.一种半导体封装元件的凸块结构，其中该半导体封装元件包含有一金属层及一第一介电层，该第一介电层形成于一金属层上，并对应该金属层部分形成有一开口，且该介电层具有一第一长度；其特征在于，该半导体封装元件的凸块结构包含：
一凸块下金属层，形成于外露在该开口的金属层部分、该开口内壁及该第一介电层顶面；其中该凸块下金属层形成在该第一介电层顶面的部分具有一第二长度；
一第一缓冲层，形成于该凸块下金属层部分及该第一介电层顶面之间，其中该第一缓冲层具有一第三长度，该第三长度大于该第二长度并小于该第一长度；及
一金属凸块，形成于该凸块下金属层上。
2.根据权利要求1所述的半导体封装元件的凸块结构，其特征在于，该第一缓冲层材质与该第一介电层材质相同。
3.根据权利要求1所述的半导体封装元件的凸块结构，其特征在于，该第一缓冲层材质的杨氏系数较该第一介电层材质的杨氏系数低。
4.根据权利要求1至3中任一项所述的半导体封装元件的凸块结构，其特征在于，该第一缓冲层对应该凸块下金属层的表面朝向该凸块下金属层形成一凸出部。
5.根据权利要求1至3中任一项所述的半导体封装元件的凸块结构，其特征在于，该第一缓冲层与该凸块下金属层之间进一步形成一第二缓冲层。
6.根据权利要求5所述的半导体封装元件的凸块结构，其特征在于，该第二缓冲层的长度小于该第一缓冲层的第三长度并大于该凸块下金属层的第二长度。
7.根据权利要求5所述的半导体封装元件的凸块结构，其特征在于，该第二缓冲层材质与该第一缓冲层材质不同。
8.根据权利要求1至3中任一项所述的半导体封装元件的凸块结构，其特征在于，该第一介电层材质为聚酰亚胺或超低介电材。
9.根据权利要求1至3中任一项所述的半导体封装元件的凸块结构，其特征在于，该金属凸块为一锡球或一金属柱。
10.根据权利要求9所述的半导体封装元件的凸块结构，其特征在于，该金属柱为一铜柱焊锡凸块，其中该铜柱焊锡凸块依序堆叠有一铜柱层、一屏障层与一焊锡层。
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