CN102142413A - 半导体元件及其制法 - Google Patents

半导体元件及其制法 Download PDF

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Publication number
CN102142413A
CN102142413A CN201010239344XA CN201010239344A CN102142413A CN 102142413 A CN102142413 A CN 102142413A CN 201010239344X A CN201010239344X A CN 201010239344XA CN 201010239344 A CN201010239344 A CN 201010239344A CN 102142413 A CN102142413 A CN 102142413A
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layer
stress
bond pad
stepped
protective layer
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CN102142413B (zh
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王姿予
邱志威
郑心圃
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种半导体元件及其制法，该半导体元件包括：一半导体基材；一接合焊盘位于该半导体基材之上；一应力缓冲结构部分地覆盖该接合焊盘并暴露一部分的接合焊盘，其中该应力缓冲结构包括一阶梯状侧壁，该阶梯状侧壁从该暴露的接合焊盘逐渐地向上延伸；以及一凸块底层金属层位于该暴露的接合焊盘上与该阶梯状侧壁之上，其中该凸块底层金属的形状与该阶梯状侧壁的形状一致。本发明的接合结构包括一阶梯状应力缓冲层位于具有同样阶梯状的凸块底层金属层之下。本发明的凸块底层金属结构与应力缓冲结构的阶梯状构造会造成较均匀的应力分布，且降低芯片底下介电材料与凸块底层金属结构自身的最大/平均应力值。

Description

半导体元件及其制法
技术领域
本发明涉及半导体元件及其制法，且特别涉及一种应力缓冲结构(stressbuffer structure)应用于半导体元件的接合结构(mounting structure)及其制法。
背景技术
近年来，随着集成电路(integrated circuits，ICs)朝向微小化的趋势，因此，需要发展高输入/输出(high I/O)密度的元件，亦即，需要发展小尺寸的接合焊盘(bonding pads)。这些接合焊盘通常形成于芯片的有源表面上，且这些接合焊盘会定义出芯片的电路电性连接到外部元件所需要的区域。由于各种潜在的(potential)问题(例如短路、结合强度不一致或不适当)，使得接合线(bondingwires)的使用逐渐地不普及。因此，开始引进倒装芯片技术(flip chiptechnique)。根据此技术，焊料凸块(solder bumps)会形成于芯片的接合焊盘上，且通过回焊(reflow)此焊料凸块，使芯片直接粘着到基材上。最后的产物通常称为球栅阵列(ball grid array，BGA)或倒装芯片球栅阵列(flip chip ball gridarray，FCBGA)芯片或封装。
为了增进焊料凸块与接合焊盘之间的粘着性，设置一凸块底层金属(under bump metallurgy，UBM)结构介于焊料凸块与接合焊盘之间。凸块底层金属(UBM)结构也可具有其他功能，例如，作为阻挡层(barrier layer)，以避免焊料材料扩散至接合焊盘或甚至是进入芯片的半导体材料中。一般凸块底层金属(UBM)结构包括各自具有不同功能的多层金属层。
由于凸块底层金属(UBM)结构与焊料凸块的多层材料层集中在每一个接合焊盘附近，因此，应力也会集中于这些材料所在的区域。如果没有预防性的测量，这些应力会逐渐增大，而对直接位于接合焊盘底下或附近的芯片的层间介电层(inter-level dielectric layers，ILD)造成伤害。对于脆性较高(brittle)，或者于某些应用中多孔性的(porous)low-k介电(低介电常数介电材料)层，应力的影响更大。这些低介电常数介电层容易产生裂缝(cracks)及/或于应力的作用下造成脱层(delaminate)。
发明内容
为克服现有技术中的缺陷，本发明提供一种半导体元件，包括：一半导体基材；一接合焊盘(bonding pad)位于该半导体基材之上；一应力缓冲结构(stress buffer structure)部分地覆盖该接合焊盘并暴露一部分的接合焊盘，其中该应力缓冲结构包括一阶梯状侧壁(stepwise wall)，该阶梯状侧壁从该暴露的接合焊盘逐渐地向上延伸；以及一凸块底层金属(under-bump metallurgy，UBM)层位于该暴露的接合焊盘上与该阶梯状侧壁之上，其中该凸块底层金属的形状与该阶梯状侧壁的形状一致。
本发明也提供一种半导体元件，包括：一接合焊盘；一第一保护层覆盖该接合焊盘的周围部分(peripheral portion)，而暴露该接合焊盘的中间部分；一阶梯状应力缓冲层，从该第一保护层的上表面向下延伸，沿着该第一保护层的侧壁延伸至该接合焊盘的中间部分；一凸块底层金属(under-bumpmetallurgy，UBM)层位于该接合焊盘中间的暴露部分、位于阶梯状应力缓冲层之上，其中该凸块底层金属(under-bump metallurgy，UBM)层的形状与该阶梯状应力缓冲层的形状一致；以及一焊料凸块位于该凸块底层金属(under-bump metallurgy，UBM)层之上。
本发明另提供一种半导体元件的制法，其中该制法包括：形成一接合焊盘于该半导体元件的有源表面上；形成具有阶梯状侧壁的应力缓冲层于该接合焊盘的周围部分，而暴露该接合焊盘的中间部分；形成凸块底层金属(under-bump metallurgy，UBM)层位于该接合焊盘中间的暴露部分，与位于该应力缓冲层的阶梯状侧壁上，使得凸块底层金属(under-bump metallurgy，UBM)层的形状与该阶梯状侧壁的形状一致；以及形成一焊料凸块于该凸块底层金属(under-bump metallurgy，UBM)层之上。
本发明又提供一种半导体元件的制法，包括以下步骤：形成一接合焊盘于该半导体元件的有源表面上；形成至少一保护层于该有源表面或接合焊盘上，以围绕该接合焊盘；形成一应力缓冲层于该至少一保护层与接合焊盘之上，而暴露该接合焊盘的中间部分；图案化至少(i)该应力缓冲层或(ii)该至少一保护层，使其具有阶梯状形状以定义该应力缓冲层的阶梯状侧壁；形成一凸块底层金属(under-bump metallurgy，UBM)层于该接合焊盘的暴露的中间部分，与位于该阶梯状应力缓冲层之上，使得该凸块底层金属(under-bumpmetallurgy，UBM)层的形状与该阶梯状侧壁的形状一致；以及一焊料凸块形成于凸块底层金属(under-bump metallurgy，UBM)层之上。
本发明的凸块底层金属(UBM)结构与应力缓冲结构的阶梯状构造会造成较均匀的应力分布，且降低芯片底下介电材料与凸块底层金属(UBM)结构自身的最大/平均应力值。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出优选实施例，并配合附图，进行详细说明。
附图说明
图1为一剖面图，用以说明公知的半导体元件的焊料凸块结构。
图2A～图2C为一系列剖面图，用以说明本发明一优选实施例的流程。
图3A～图3B为一系列图式，用以说明图2A-图2C的接合结构的应力分布与应力值。
图4A～图4H为一系列剖面图，用以说明本发明另一优选实施例的流程。
图5A～图5D为一系列剖面图，用以说明本发明又一优选实施例的流程。
图6A～图6B为一系列剖面图，用以说明本发明一优选实施例的流程。
图7A～图7C为一系列剖面图，用以说明本发明另一优选实施例的流程。
图8A～图8C为一系列剖面图，用以说明本发明又一优选实施例的流程。
其中，附图标记说明如下：
100～焊料凸块结构
101～有源表面
102～晶片或芯片
104～最上层金属层
106～第一保护层
108～接合焊盘
110～第二保护层
112～聚酰亚胺层(PI)
114～凸块底层金属(UBM)结构
116～焊料凸块
120～凸块底层金属(UBM)结构114的下方边缘
122～凸块底层金属(UBM)结构114的上方边缘
201～有源表面
204～最上层金属层
208～接合焊盘
212～应力缓冲结构
214～凸块底层金属(UBM)结构
216、240、250～焊料凸块
400、500、600、700、800～半导体元件
401～有源表面
402、502、702、802～半导体基材
404、504、704、804～最上层金属层
406、506、706、806～第一保护层
408、508、708、808～接合焊盘
410、510、710、810～第二保护层
411、511、711、811～掩模
412、512、612、712、812～应力缓冲结构
413、613～掩模
414、514、614、714、814～凸块底层金属(UBM)结构
416～焊料凸块
1125～侧壁
1149、2149～侧壁
b～下层阶梯的高度
a～上层阶梯的高度
2125、4125、5125、6125、7125、8125～侧壁
4083～接合焊盘的凸起部分
4101、4102、5101～保护材料层
4107～阶梯状的侧壁
4121、7121、8121～应力缓冲材料层
8122～第二应力缓冲材料层
4159、5159、7159、8159～第二保护层开口
4160～放大后的第二保护层开口
2121、5061、5081、5128、6128、7128、8128～下层阶梯
2122、5062、5082、5127、6127、7127、8127～上层阶梯
6129～中间阶梯
D1、D2、D3、D4～开口
具体实施方式
应注意的是，下文所述的一层位于另一层或基材之上，其可以是直接接触该层或该基材，或者是中间仍存在着别层。
图1显示公知的焊料凸块结构100的剖面图。焊料凸块结构100形成于半导体元件的晶片或芯片102的有源表面101之上，且包括第一保护层106、接合焊盘108、第二保护层110、聚酰亚胺层(polyimide，PI)112、凸块底层金属(UBM)结构114与焊料凸块116，并依此顺序由下而上形成于晶片或芯片102之上。芯片102包括位于接合焊盘108之下，电性连接至接合焊盘108的最上层金属层(top-level metal)104。最上层金属层(top-level metal)104是芯片102中内连线结构的一部分。芯片102的内连线结构还包括，位于最上层金属层104之下及/或附近的一个或多个介电层(图中未显示)，同上所述，这些介电层通常由低介电常数或极低介电常数材料所组成，这些低介电常数材料是脆性高的(brittle)且容易产生裂缝(cracks)或脱层(delamination)。
由于焊料凸块结构100通常会在凸块底层金属(UBM)结构114的下方边缘与上方边缘120，122产生高度应力集中。应力大小取决于凸块底层金属(UBM)结构114的侧壁1149的倾斜角度。特别当侧壁1149处于(例如，相对于有源表面101为40°)锐角(acute)角度时，应力大部分会集中于下方边缘120。当侧壁1149的倾斜角度增加至90°时，应力会集中偏移至上方边缘122。然而，不论处于任何斜角，高应力仍会传送至位于边缘120，122底下的内连线结构的介电层中，因此，提高介电层产生裂缝(cracks)或脱层(delamination)的可能性。
图2A显示图1焊料凸块结构100的简化图或部分图。图2B-图2C类似于图2A，显示本发明的各种焊料凸块结构240，250的实施例。
图2B中的焊料凸块结构形成于半导体元件的半导体晶片或芯片(图中未显示)的有源表面201上。焊料凸块结构240包括接合焊盘208、应力缓冲结构212、凸块底层金属(UBM)结构214与焊料凸块216(部分显示)，并依此顺序由下而上依序形成。于接合焊盘208之下，芯片包括由多层导电与介电层依序迭加形成的内连线结构。为了简化说明，只有内连线结构的最上层导电层显示于图中，例如最上层金属层204。内连线结构还包括，位于最上层金属层204之下及/或附近的一个或多个介电层(图中未显示)，于一些实施例中，该些介电层通常由低介电常数(low-k)或极低介电常数(extreme low-k)材料所组成。当芯片被反转(flipped over)与设置于载板(例如基材或导线架(leadframe)(图中未显示))之上，与焊料凸块216被回焊(reflow)时，焊料凸块结构240用以定义出芯片的粘着结构(mounting structure)。于一些实施例中，因为提供多个焊料凸块结构240，所以芯片包括多个接合焊盘208。
应力缓冲结构(stress buffer structure)212与图1与图2A中的焊料凸块结构100的聚酰亚胺(PI)层112不同。特别的是，亚酰亚胺(PI)层112具有一侧壁1125，此侧壁1125角度一致地(monotonously)从接合焊盘108开始延伸向上，亦即，从接合焊盘108开始以一固定的斜率向上延伸。如此一来，形成于聚酰亚胺(PI)层112上的凸块底层金属(UBM)结构114与聚酰亚胺(PI)层112的形状一致，且也具有角度一致地(monotonously)延伸的侧壁1149。此种焊料凸块结构100，同上所述，容易造成底下各层(例如，芯片的低介电常数(low-k)介电层或超低介电常数(extremely low-k)介电层)的应力集中。
相反地，于图2B中的应力缓冲结构(stress buffer structure)212并不具有角度一致地(monotonously)延伸的侧壁1149。取而代之的是应力缓冲结构212从接合焊盘208开始以阶梯状(stepwise manner)向上延伸。高于接合焊盘208之上的侧壁2125至少包括两个阶梯，分别命名为下层阶梯2121与上层阶梯2122，其各自具有高度b与a，如图2B中所示。既然应力缓冲结构212的侧壁2125是阶梯状，则形成于应力缓冲结构212之上且顺应其形状的凸块底层金属(UBM)结构214也具有阶梯状侧壁2149。下文会加以详述，凸块底层金属(UBM)结构214与应力缓冲结构212的阶梯状构造，会造成底下各层(例如低介电常数(low-k)介电层或超低介电常数(extremely low-k)介电层)的应力分布较为均匀。比起焊料凸块结构100，此阶梯状构造还可降低应力的最大及/或平均值。
于图2C中的焊料凸块结构250类似于焊料凸块结构240，差别只在介于阶梯之间(例如下层阶梯2121与上层阶梯2122)的高度不同。图2B中的高度比例为约1∶1，亦即，下层阶梯2121的高度与上层阶梯2122的高度大约相同。于图2C中的高度比例为约2∶1，亦即上层阶梯2122的高度为下层阶梯2121的高度的两倍。
假设焊料凸块结构100，240与250的所有特性皆相同(亦即，材料或厚度等)，差别只在聚酰亚胺(PI)层112/应力缓冲结构212与对应的凸块底层金属(UBM)结构的特定形状与特定高度不同(请参见图2B-图2C)，应力产生的计算机模拟(computer simulation)结果显示于图3A-图3B中。
图3A中显示底下各层的低介电常数(low-k)材料或超低介电常数(extremely low-k，ELK)材料的应力分布图，例如位于焊料凸块结构100，240与250中最上层金属层104，204底下的各层。在图2A中的焊料凸块结构100的应力分布最不平均(uneven)，其位于下方边缘120(图1中)的位置具有非常高的信号峰值(最大应力值)。图2B中的焊料凸块结构240的应力分布比图2A的焊料凸块结构100均匀，其具有较低的信号峰值。图2C中的焊料凸块结构250的应力分布比图2B的焊料凸块结构240更为均匀，其具有最低的信号峰值。如此一来，最大的应力值依序从焊料凸块结构100、焊料凸块结构240下降至焊料凸块结构250。因此，比起焊料凸块结构100，应力集中的问题在焊料凸块结构240、焊料凸块结构250中较不严重。
此外，平均应力值也可改善。图3B中显示底下各层的低介电常数(low-k)材料或超低介电常数(extremely low-k，ELK)材料的平均应力分布图，例如于最上层金属层104、204底下的各层，与位于凸块底层金属(UBM)结构(例如凸块底层金属结构114、214)之上的各层。由图3B中可得知，横越凸块底层金属(UBM)结构的宽度，且位于底下的介电层与凸块底层金属(UBM)结构两者的平均应力值依序从焊料凸块结构100、焊料凸块结构240下降至焊料凸块结构250。因此，位于底下的介电层材料，其平均应力值下降超过25％(从63.4下降至47.1)；凸块底层金属(UBM)结构中的平均应力值下降超过20％(从183.3下降至147.1)。
因此，凸块底层金属(UBM)结构与应力缓冲结构的阶梯状构造会造成较均匀的应力分布，且降低芯片底下介电材料与凸块底层金属(UBM)结构自身的最大/平均应力值。于各种未显示的实施例中，通过改变阶梯的数目(例如，形成大于两个以上的阶梯)及/或高度及/或于各个阶梯构造的高度比，于凸块底层金属(UBM)结构中的应力值与分布可以像芯片底下介电材料一样，皆被最佳化成所需的数值。进行应力最佳化的调整时，可以单一条件各自调整或多个条件一起调整，例如调整应力缓冲结构的厚度(于某些实施例中也称为聚酰亚胺(PI)层厚度)、及/或于应力缓冲结构中开口的尺寸(于某些实施例中也称为“PI层开口”)、及/或开口的侧壁的斜角。
应力缓冲结构212包括一层或多层材料层。简而言之，于图2B-图2C中仅显示一层应力缓冲层。这些应力缓冲层是由应力缓冲材料所组成，且由应力缓冲结构212定义出阶梯状侧壁2125，因此，也对应地定义出凸块底层金属(UBM)结构214的阶梯状侧壁2149。于某些实施例中，应力缓冲材料为高分子，其中高分子包括聚酰亚胺(polyimide)、聚苯恶唑(polybenzoxazole，PBO)、以环氧树脂为主的高分子、酚(phenol)为主的高分子或苯并环丁烯(benzocyclobutene，BCB)。
于一些实施例中，提供类似于焊料凸块结构100的第二保护层110的保护层(并未显示于图中)，此保护层位于应力缓冲结构212之下，用以调整应力缓冲结构212的高度，因此不需要大量的应力缓冲层材料。于其他实施例中，由一种或多种应力缓冲材料形成的多层结构由下而上依序形成，用以组成应力缓冲结构212，这些材料可组成应力缓冲结构212或与保护层一起组成应力缓冲结构212。
依据本发明的实施例，图4A-图4H显示半导体元件400(图4H)制作接合结构的各个工艺阶段的剖面图。
于图4A中，提供一半导体基材402。于一些实施例中，半导体基材402为晶片。于其他实施例中，半导体基材402为具有内部电路与有源表面401的芯片。半导体基材402包括最上层导电层，例如最上层金属层404。半导体基材402还包括位于最上层金属层104之下及/或附近的一个或多个介电层(图中未显示)，于某些实施例中，该些介电层由脆性高的(brittle)且容易产生裂缝(cracks)或脱层(delamination)的低介电常数或极低介电常数材料所组成。
第一保护层406形成于有源表面401上，以部分覆盖最上层金属层404。未被第一保护层406覆盖的一部分最上层金属层404是暴露的，在此也称为第一保护层开口。于一些实施例中，保护层406包括氧化层或氮化层，例如氧化硅或氮化硅。于其他实施例中，第一保护层包括聚酰亚胺(polyimide)。第一保护层406的形成方法包括沉积(例如通过化学气相沉积法(chemicalvapor deposition，CVD))保护材料于有源表面401上，接着蚀刻一部分的保护材料以形成第一保护层开口。
导电材料接着沉积到第一保护层开口中，与位于第一保护层406上表面之上并围绕第一保护层开口，以形成接合焊盘408。于一些实施例中，接合焊盘408局限于(confined within)第一保护层开口中，不设置于第一保护层406上表面之上。接合焊盘408的导电材料包括铝或铜，且其沉积后用以电性连接半导体基材或芯片402的内部电路。
如图4A所示，保护材料层4101沉积于接合焊盘408与第一保护层406之上。于此特别实施例中，保护材料层4101的上表面的形状与底下接合焊盘408的形状相同。于其他实施例中，于后续工艺步骤之前，对保护材料层4101的上表面进行平坦化。保护材料层4101的材料与第一保护层406的材料相同或类似。
请参见图4B，具有一开口D1的掩模411用于部分地移除保护材料层4101的暴露部分。举例而言，掩模411包括沉积一光致抗蚀剂，接着，对位于保护材料层4101上表面之上的光致抗蚀剂进行光光刻图案化(photo-lithographically patterned)工艺。之后，移除暴露的保护材料层4101(例如，通过第一蚀刻工艺)。
图4C显示进行第一蚀刻工艺之后且掩模411被移除之后的剖面图。特别的是，第二保护层开口4159形成于保护材料层4101之中。曾经被图案化的保护材料层4101在此处将被称为保护材料层4102。于一些实施例中，请参见图4C，对保护材料层4101的蚀刻停止于接合焊盘408暴露之前。如此一来，可得到如下所述的至少三阶的阶梯状结构。于其他实施例中，对保护材料层4101的蚀刻停止于直到接合焊盘408暴露为止。如此一来，可得到如下所述的至少两阶的阶梯状结构。
请参见图4D，另一掩模413具有大于开口D1的开口D2，此开口D2用于(例如，通过第二蚀刻工艺)移除保护材料层4102的暴露部分。举例而言，掩模413的形成类似于掩模411。
图4E显示进行第二蚀刻工艺之后且掩模413被移除之后的剖面图。特别的是，第二保护层开口4159被放大且标示为4160。经过两次图案化的保护材料层4101已经变成第二保护层410。如图4E所示，第二保护层410具有阶梯状的侧壁4107。对保护材料层4102的蚀刻停止于直到接合焊盘408暴露为止。
请参见图4F，通过例如旋转涂布法沉积应力缓冲材料层4121于第二保护层410之上，与沉积于第二保护层开口4160之中与接合焊盘408的暴露部分上。应力缓冲材料层4121的侧壁4125具有两层上层阶梯，其中上层阶梯的形状同于第二保护层410的阶梯状侧壁4107。应力缓冲材料层4121的侧壁4125还包括一较下层阶梯，其中下层阶梯的形状同于接合焊盘408的凸起部分4083。
请参见图4G，移除位于第二保护层开口4160底部的部分应力缓冲材料层4121以暴露一部分的接合焊盘408，利用例如已知的图案化方法，包括光刻工艺与蚀刻工艺。因此，图案化后的应力缓冲材料层4121现在变成具有三层阶梯状结构的应力缓冲结构412。
请参见图4H，凸块底层金属(UBM)结构414沉积于应力缓冲结构412之上，其顺应应力缓冲结构412的形状而形成且电性接触接合焊盘408暴露的部分。凸块底层金属(UBM)结构414包括一层或多层金属，其中金属包括铬(Cr)、钛(Ti)、镍(Ni)、钨(W)、铂(Pt)、铜(Cu)、钯(Pd)、金(Au)、银(Ag)或上述的合金。凸块底层金属(UBM)结构414的形成依序通过(例如化学气相沉积法(CVD)、电镀或溅镀)沉积成分层(亦即金属层)于接合焊盘408之上，接着进行蚀刻工艺(例如干式蚀刻或湿式蚀刻)移除不想要的部分。焊料凸块416形成于凸块底层金属(UBM)结构414之上，以完成半导体元件400。
依据本发明的实施例，图5A-图5D显示半导体元件500(图5D)制作接合结构的各个工艺阶段的剖面图。
于图5A中，提供类似于半导体基材402的半导体基材502。半导体基材502包括最上层导电层，例如类似于最上层金属层404的最上层金属层504。第一保护层506、接合焊盘508与保护材料层5101类似于第一保护层406、接合焊盘408与保护材料层4101，各自地形成于半导体基材502之上，且形成的方法类似于图4A所述的方法。
图5A与图4A的差别在于，第一保护层506被图案化大于一次(例如两次)，而于图4A中，第一保护层406只被图案化一次。结果造成于第一保护层506中的第一保护层开口具有如图5A所示的阶梯状侧壁。形成阶梯状第一保护层开口的工艺步骤类似于图4A-图4E所示的方法(例如通过具有不同尺寸掩模进行两次蚀刻工艺)。然而，也可以使用其他方法。
图5A与图4A另一点差别在于，形成于第一保护层506之上的接合焊盘508的形状与第一保护层506的形状相同，同样具有阶梯状形状。特别的是，接合焊盘508具有下层阶梯5081与上层阶梯5082各自对应到第一保护层506的下层阶梯5061与上层阶梯5062。于一些实施例中(图中未显示)，接合焊盘508被局限于(confined within)第一保护层506的上层阶梯5062所定义的边界(boundary)中，因此其具有类似于图4A的形状。
请参见图5B，类似于掩模411的掩模511具有开口D3用于移除保护材料层5101的暴露部分，移除的方法类似于图4B所述的方法。
图5C显示进行图5B的蚀刻工艺之后且掩模511被移除之后的剖面图。特别的是，第二保护层开口5159形成于曾经被图案化的保护材料层5101中(在此处将被称为保护材料层510)。对保护材料层5101的蚀刻停止于接合焊盘508暴露之前或之后。接合焊盘508的上层阶梯5082的上表面被埋入第二保护层510中，且因此形成如下所述至少有两层阶梯的形状。
请参见图5D，沉积应力缓冲材料层并图案化之，以定义应力缓冲结构512，形成的方法类似于图4F-图4G所述的方法。应力缓冲结构512的侧壁5125具有对应到第二保护层510上表面的上层阶梯5127与具有对应到接合焊盘508下层阶梯5081的下层阶梯5128。
凸块底层金属(UBM)结构514沉积于应力缓冲结构512之上，其顺应应力缓冲结构512的形状而形成且电性接触接合焊盘508暴露的中间部分，此形成方法类似于图4H所述的方法。焊料凸块(未显示于图5D中)形成于凸块底层金属(UBM)结构514之上，以完成半导体元件500。
依据本发明的实施例，图6A-图6B显示半导体元件600(图6B)制作接合结构的各个工艺阶段的剖面图。
图6A延续图5C的步骤，其中掩模613具有大于开口D3的开口D4，此开口D4用于蚀刻第二保护层510，以获得应力缓冲结构612(图6B)。因此，于图5C中的第二保护层开口5159变宽，因此造成接合焊盘508的上层阶梯5082的上表面暴露，且定义出如图6B所示的最终阶梯形状。
特别的是，于图6B中，应力缓冲材料层612的侧壁6125具有对应于第二保护层610上表面的上层阶梯6127、对应于接合焊盘508下层阶梯5081的下层阶梯6128与对应于接合焊盘508上层阶梯5082上表面的中间阶梯6129。
凸块底层金属(UBM)结构614沉积于应力缓冲结构612之上，其顺应应力缓冲结构612的形状而形成且电性接触接合焊盘508暴露的中间部分，此形成方法类似于本发明上述公开的方法。焊料凸块(未显示于图6B中)形成于凸块底层金属(UBM)结构614之上，以完成半导体元件600。
于一些实施例中，掩模613可以被取代掩模511(而非结合两者)，以蚀刻如图5B所示的保护材料层5101，以获得类似于半导体元件600的半导体元件。
依据本发明的实施例，图7A-图7C显示半导体元件700(图7C)制作接合结构的各个工艺阶段的剖面图。
图7A显示半导体元件经过图4A-图4C与图4F-图4H工艺步骤之后的状态。特别的是，于图7A中的半导体基材702类似于半导体基材402。半导体基材702包括最上层导电层，例如类似于最上层金属层402的最上层金属层704。第一保护层706、接合焊盘708与保护材料层(图中未显示)类似于第一保护层406、接合焊盘408与保护材料层4101，各自地形成于半导体基材702之上，且形成的方法类似于图4A所述的方法。
利用类似于图4B所述的掩模(mask)图案化保护材料层。
保护材料层的图案化步骤会进行到直到接合焊盘708的中间部分暴露为止，并不像图4C的工艺。因此，会得到第二保护层710。
如图4F所述，应力缓冲材料层(图中未显示)沉积于图案化第二保护层710之上。且如图4G所述，对应力缓冲材料层进行图案化，以获得如图7A所示的图案化应力缓冲材料层7121。
类似于掩模411的掩模711具有一开口(并未标示)宽于形成于第二保护层710中的第二保护层开口7159，掩模711的作用在于，移除围绕于第二保护层开口7159的图案化应力缓冲材料层7121的暴露部分，以获得如图7B所示的应力缓冲结构712。
图7B显示进行图7A的蚀刻工艺之后且掩模711被移除之后的剖面图。特别的是，移除部分的图案化应力缓冲材料层7121会得到具有阶梯状侧壁7125的应力缓冲结构712。值得一提的是，应力缓冲材料层712的侧壁7125具有对应到图案化应力缓冲材料层7121上表面的上层阶梯7127(于第二次蚀刻工艺之前)，与对应到围绕第二保护层开口7159的应力缓冲材料层7121上表面的下层阶梯7128(于第二次蚀刻工艺之后)。因此，可获得两层阶梯的形状。
请参见图7C，凸块底层金属(UBM)结构714沉积于应力缓冲结构712之上，其顺应应力缓冲结构712的形状而形成且电性接触接合焊盘708暴露的中间部分，此形成方法类似于图4H所述的方法。焊料凸块(未显示于图7C中)形成于凸块底层金属(UBM)结构714之上，以完成半导体元件700。
依据本发明的实施例，图8A-图8C显示半导体元件800(图8C)制作接合结构的各个工艺阶段的剖面图
图8A类似于图7A，差别在于不需要使用掩模711。因此，于图8A中的半导体基材802类似于半导体基材702。半导体基材802包括最上层导电层，例如类似于最上层金属层704的最上层金属层804。第一保护层806、接合焊盘808与第二保护材料层810与图案化应力缓冲材料层8121类似于第一保护层706、接合焊盘708与第二保护层710与图案化应力缓冲材料层7121，各自地形成于半导体基材802之上，且形成的方法同前所述。此外，亦形成类似于第二保护层开口7159的第二保护层开口8159。
不同于图7A中立即使用掩模对图8A的结构进行蚀刻，取而代之的是于图8B，填充第二应力缓冲材料层8122到第二保护层开口8159中，且沉积一所需厚度到图案化应力缓冲材料层8121之上。于一些实施例中，使用旋转涂布工艺(spin-coating process)形成第二应力缓冲材料层8122。使用具有所需开口(图中未显示)的掩模811，此掩模811用于蚀刻形成于第二保护层开口8159中的第二应力缓冲材料层8122的暴露部分，以及蚀刻位于图案化应力缓冲材料层8121之上的部分。提高对应力缓冲材料层8121与第二应力缓冲材料层8122的蚀刻选择性(etch selectivity)，使得第二应力缓冲材料层8122的暴露部分被移除，且不会严重影响到形成于掩模811开口中的图案化应力缓冲材料层8121的厚度。
图8C显示进行图8B的蚀刻工艺之后且掩模811被移除之后的剖面图。之后，会得到具有阶梯状侧壁8125且结合第二应力缓冲材料层8122与图案化应力缓冲材料层8121的应力缓冲结构812。应力缓冲材料层812的侧壁8125具有对应到第二应力缓冲材料层8122上表面之上层阶梯8127，与对应到图案化应力缓冲材料层8121上表面的下层阶梯8128(于第二次蚀刻工艺之后)。因此，可获得两层阶梯的形状。可通过调整第二应力缓冲材料层8122于第二保护层开口8159中的深度(图8A)决定阶梯形状中各层阶梯的高度比(height ratio)。
凸块底层金属(UBM)结构814沉积于应力缓冲结构812之上，其顺应应力缓冲结构812的形状而形成且电性接触接合焊盘808暴露的中间部分，此形成方法类似于图4H所述的方法。焊料凸块(未显示于图8C中)形成于凸块底层金属(UBM)结构814之上，以完成半导体元件800。
虽然本发明已以数个优选实施例公开如上，然其并非用以限定本发明，任何所属技术领域中的普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视随附的权利要求所界定的保护范围为准。

Claims (10)

1.一种半导体元件，包括：
一半导体基材；
一接合焊盘位于该半导体基材之上；
一应力缓冲结构部分地覆盖该接合焊盘并暴露一部分的接合焊盘，其中该应力缓冲结构包括一阶梯状侧壁，该阶梯状侧壁从该暴露的接合焊盘逐渐地向上延伸；以及
一凸块底层金属层位于该暴露的接合焊盘上与该阶梯状侧壁之上，其中该凸块底层金属的形状与该阶梯状侧壁的形状一致。
2.如权利要求1所述的半导体元件，其中该应力缓冲结构包括：
一保护层；以及
一应力缓冲高分子层位于该保护层之上，且定义出整个该阶梯状侧壁，其中该应力缓冲高分子层包括聚酰亚胺、聚苯恶唑、以环氧树脂为主的高分子、酚为主的高分子或苯并环丁烯。
3.如权利要求1所述的半导体元件，其中该应力缓冲结构包括：
一保护层，其中该保护层包括一第一阶梯状侧壁；以及
一应力缓冲高分子层位于该保护层之上，且包括与该阶梯状侧壁的形状一致的一第二阶梯状侧壁。
4.如权利要求3所述的半导体元件，其中该接合焊盘包括一第三阶梯状侧壁，且该第一与第二阶梯状侧壁的形状与该第三阶梯状侧壁的形状一致。
5.如权利要求1所述的半导体元件，其中该阶梯状侧壁包括至少两层高度大体上相同的阶梯。
6.如权利要求1所述的半导体元件，其中该阶梯状侧壁包括至少两层不同高度的阶梯。
7.一种半导体元件的制法，其中该制法包括：
形成一接合焊盘于该半导体元件的有源表面上；
形成具有阶梯状侧壁的应力缓冲层于该接合焊盘的周围部分，而暴露该接合焊盘的中间部分；
形成凸块底层金属层位于该接合焊盘中间的暴露部分，与位于该应力缓冲层的阶梯状侧壁上，使得凸块底层金属层的形状与该阶梯状侧壁的形状一致；以及
形成一焊料凸块于该凸块底层金属层之上。
8.如权利要求7所述的半导体元件的制法，于形成该应力缓冲层之前，还包括：
形成一上层保护层于该有源表面上与该接合焊盘上；以及
当应力缓冲层形成于该上层保护层之上时，图案化该上层保护层，使该上层保护层具有一阶梯状形状，其中该阶梯状形状至少部分地定义出该应力缓冲层的阶梯状侧壁。
9.如权利要求7所述的半导体元件的制法，还包括：
当应力缓冲层形成于该接合焊盘之上时，图案化该接合焊盘，使得该接合焊盘具有一阶梯状形状，其中该阶梯状形状至少部分地定义出该应力缓冲层的阶梯状侧壁。
10.如权利要求7所述的半导体元件的制法，于形成该接合焊盘之前，还包括：
形成一下层保护层于该有源表面上；以及
当接合焊盘形成于该下层保护层之上时，图案化该下层保护层，使该下层保护层具有一阶梯状形状，其中该阶梯状形状定义出对应于该接合焊盘的一阶梯形状；
当应力缓冲层形成于该接合焊盘之上时，其中接合焊盘的阶梯状形状至少部分地定义出该应力缓冲层的阶梯状侧壁。
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CN106898625A (zh) * 2015-12-18 2017-06-27 中芯国际集成电路制造(上海)有限公司 图像传感器芯片的封装结构及封装方法
CN106898625B (zh) * 2015-12-18 2020-06-02 中芯国际集成电路制造(上海)有限公司 图像传感器芯片的封装结构及封装方法
CN105977177A (zh) * 2016-05-11 2016-09-28 上海华虹宏力半导体制造有限公司 解决半导体测试失败的半导体结构以及半导体测试方法
CN109841594A (zh) * 2017-11-27 2019-06-04 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN109841594B (zh) * 2017-11-27 2021-04-02 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN110890338A (zh) * 2018-09-07 2020-03-17 矽品精密工业股份有限公司 电子封装结构及其制法
TWI695459B (zh) * 2018-09-07 2020-06-01 矽品精密工業股份有限公司 電子封裝結構及其製法
CN111613596A (zh) * 2019-02-25 2020-09-01 中芯国际集成电路制造(上海)有限公司 封装结构及其形成方法
CN111613596B (zh) * 2019-02-25 2022-01-14 中芯国际集成电路制造(上海)有限公司 封装结构及其形成方法
CN115084048A (zh) * 2022-08-22 2022-09-20 成都复锦功率半导体技术发展有限公司 一种低应力Low-K半导体器件封装结构及其制造方法

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US20150102487A1 (en) 2015-04-16
US8906798B2 (en) 2014-12-09
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US20110186987A1 (en) 2011-08-04
US20130109169A1 (en) 2013-05-02
TW201128751A (en) 2011-08-16
TWI429042B (zh) 2014-03-01
US9337118B2 (en) 2016-05-10

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