KR100691398B1 - 미소소자 패키지 및 그 제조방법 - Google Patents
미소소자 패키지 및 그 제조방법 Download PDFInfo
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- KR100691398B1 KR100691398B1 KR1020060023407A KR20060023407A KR100691398B1 KR 100691398 B1 KR100691398 B1 KR 100691398B1 KR 1020060023407 A KR1020060023407 A KR 1020060023407A KR 20060023407 A KR20060023407 A KR 20060023407A KR 100691398 B1 KR100691398 B1 KR 100691398B1
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- 238000004519 manufacturing process Methods 0.000 title claims description 32
- 239000000758 substrate Substances 0.000 claims abstract description 122
- 238000000034 method Methods 0.000 claims abstract description 59
- 230000002093 peripheral effect Effects 0.000 claims abstract description 39
- 229910000679 solder Inorganic materials 0.000 claims description 43
- 238000007789 sealing Methods 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 238000004377 microelectronic Methods 0.000 claims description 9
- 230000005693 optoelectronics Effects 0.000 claims description 9
- 238000002161 passivation Methods 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 125000006850 spacer group Chemical group 0.000 claims description 5
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 238000000926 separation method Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 18
- 239000011247 coating layer Substances 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000011109 contamination Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- WSMQKESQZFQMFW-UHFFFAOYSA-N 5-methyl-pyrazole-3-carboxylic acid Chemical compound CC1=CC(C(O)=O)=NN1 WSMQKESQZFQMFW-UHFFFAOYSA-N 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- GQYHUHYESMUTHG-UHFFFAOYSA-N lithium niobate Chemical compound [Li+].[O-][Nb](=O)=O GQYHUHYESMUTHG-UHFFFAOYSA-N 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000012780 transparent material Substances 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- SXHLTVKPNQVZGL-UHFFFAOYSA-N 1,2-dichloro-3-(3-chlorophenyl)benzene Chemical compound ClC1=CC=CC(C=2C(=C(Cl)C=CC=2)Cl)=C1 SXHLTVKPNQVZGL-UHFFFAOYSA-N 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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Abstract
Description
Claims (35)
- 상면에 미소소자가 형성되며 상기 미소소자의 주변으로 상대적으로 얇은 두께로 형성된 주변부를 갖는 기판; 및상기 주변부를 매개로 상기 미소소자와 전기적으로 연결되는 회로기판;을 포함하는 미소소자 패키지.
- 제1항에 있어서,상기 주변부의 상면에는 상기 미소소자와 전기적으로 연결되는 전극패드가 형성된 것을 특징으로 하는 미소소자 패키지.
- 제2항에 있어서,상기 주변부에는 상기 전극패드의 저면이 노출되도록 비아홀이 형성된 것을 특징으로 하는 미소소자 패키지.
- 제3항에 있어서,상기 전극패드의 저면에는 솔더범프가 형성된 것을 특징으로 하는 미소소자 패키지.
- 제1항에 있어서,상기 미소소자의 상측에 에어 캐비티가 형성되도록 상기 기판의 상측에 접합되는 투광성 커버를 더 포함하는 것을 특징으로 하는 미소소자 패키지.
- 제1항에 있어서,상기 미소소자는 마이크로기계공학적 소자, 마이크로전자공학적 소자, 광전자공학적 소자 중 어느 하나인 것을 특징으로 하는 미소소자 패키지.
- 미소소자가 상면에 형성되며, 상기 미소소자의 주변으로 저면에 리세스(recess)가 형성된 기판;상기 기판의 상측에 접합되는 투광성 커버; 및상기 리세스에 적어도 일부가 수용되며 상기 미소소자에 전기적으로 접속되는 회로기판;을 포함하는 미소소자 패키지.
- 제7항에 있어서,상기 리세스에 해당되는 상기 기판의 상면에는 상기 미소소자와 전기적으로 연결되는 전극패드가 형성된 것을 특징으로 하는 미소소자 패키지.
- 제8항에 있어서,상기 기판에는 상기 전극패드가 상기 리세스로 노출되도록 비아홀이 형성된 것을 특징으로 하는 미소소자 패키지.
- 제9항에 있어서,상기 전극패드의 저면에는 솔더범프가 형성된 것을 특징으로 하는 미소소자 패키지.
- 제10항에 있어서,상기 전극패드와 상기 솔더범프의 사이에 개재되는 씨드메탈을 더 포함하는 것을 특징으로 하는 미소소자 패키지.
- 제7항에 있어서,상기 미소소자의 상측에 에어 캐비티가 형성되도록 상기 투광성 커버는 상기 기판으로부터 이격되게 접합된 것을 특징으로 하는 미소소자 패키지.
- 제12항에 있어서,상기 기판과 상기 투광성 커버의 사이에는 스페이서가 개재된 것을 특징으로 하는 미소소자 패키지.
- 제7항에 있어서,상기 미소소자는 마이크로기계공학적 소자, 마이크로전자공학적 소자, 광전자공학적 소자 중 어느 하나인 것을 특징으로 하는 미소소자 패키지.
- 제7항에 있어서,상기 기판은 실리콘으로 이루어진 웨이퍼로부터 제공된 것을 특징으로 하는 미소소자 패키지.
- 미소소자 및 상기 미소소자의 주변에서 상기 미소소자와 전기적으로 연결되는 전극패드가 상면에 형성되고, 상기 미소소자의 주변으로 저면에 리세스가 형성되며, 상기 전극패드가 상기 리세스로 노출되도록 비아홀이 형성된 기판;상기 미소소자의 상측에 에어 캐비티가 형성되도록 상기 미소소자로부터 이격되게 접합되는 투광성 커버;상기 전극패드와 전기적으로 연결되게 상기 전극패드의 저면에 형성되는 솔더범프; 및상기 리세스에 적어도 일부가 수용되며 상기 전극패드에 전기적으로 접속되는 회로기판;을 포함하는 미소소자 패키지.
- 상면에 미소소자가 형성되며 상기 미소소자 주변으로 상대적으로 얇은 두께로 형성된 주변부를 갖는 기판을 제공하는 단계; 및상기 주변부를 매개로 상기 미소소자와 전기적으로 접속되도록 회로기판을 연결하는 단계;를 포함하는 미소소자 패키지의 제조방법.
- 제17항에 있어서,상기 주변부의 상면에 상기 미소소자와 전기적으로 연결되는 전극패드를 형성하는 단계를 포함하는 것을 특징으로 하는 미소소자 패키지의 제조방법.
- 제18항에 있어서,상기 회로기판을 연결하기 전에 상기 주변부에 상기 전극패드의 저면이 노출되도록 비아홀을 형성하는 단계를 포함하는 것을 특징으로 하는 미소소자 패키지의 제조방법.
- 제19항에 있어서,상기 전극패드의 저면에 솔더범프를 형성하는 단계를 포함하는 것을 특징으로 하는 미소소자 패키지의 제조방법.
- 제17항에 있어서,상기 미소소자의 상측에 에어 캐비티가 제공되도록 상기 기판의 상측에 투광성 커버를 접합하는 단계를 더 포함하는 것을 특징으로 하는 미소소자 패키지의 제조방법.
- 제17항에 있어서,상기 미소소자는 마이크로기계공학적 소자, 마이크로전자공학적 소자, 광전 자공학적 소자 중 어느 하나인 것을 특징으로 하는 미소소자 패키지의 제조방법.
- 소정 이격 거리를 갖도록 복수개의 미소소자가 상면에 형성된 기판을 제공하는 단계;상기 각 미소소자의 주변을 따라 상기 기판의 저면에 그루브를 형성하는 단계;상기 그루브를 따라 상기 기판을 다이싱(dicing)하는 단계;상기 그루브에 의해서 제공되는 리세스에 적어도 일부가 수용되며 상기 미소소자에 전기적으로 접속되도록 회로기판을 연결하는 단계;를 포함하는 미소소자 패키지의 제조방법.
- 제23항에 있어서,상기 리세스에 해당되는 상기 기판의 상면에 상기 미소소자와 전기적으로 연결되는 전극패드를 형성하는 단계를 포함하는 것을 특징으로 하는 미소소자 패키지의 제조방법.
- 제24항에 있어서,상기 기판을 다이싱하기 전에 상기 전극패드가 상기 그루브로 노출되도록 비아홀을 형성하는 단계를 포함하는 것을 특징으로 하는 미소소자 패키지의 제조방법.
- 제25항에 있어서,상기 전극패드의 저면에 솔더범프를 형성하는 단계를 포함하는 것을 특징으로 하는 미소소자 패키지의 제조방법.
- 제26항에 있어서,상기 솔더범프를 형성하기 전에 상기 기판의 저면 및 상기 비아홀의 벽면에는 절연층을 형성하는 단계를 포함하는 것을 특징으로 하는 미소소자 패키지의 제조방법.
- 제26항에 있어서,상기 전극패드와 상기 솔더범프의 사이에 개재되도록 씨드메탈을 형성하는 단계를 더 포함하는 것을 특징으로 하는 미소소자 패키지의 제조방법.
- 제28항에 있어서,상기 솔더범프를 형성하기 전에 상기 씨드메탈의 노출면에 패시베이션 막을 형성하는 단계를 더 포함하는 것을 특징으로 하는 미소소자 패키지의 제조방법.
- 제23항에 있어서,상기 그루브를 형성하기 전에 상기 기판의 저면을 씨닝하는 단계를 더 포함 하는 것을 특징으로 하는 미소소자 패키지의 제조방법.
- 제23항에 있어서,상기 미소소자의 상측에 에어 캐비티가 제공되도록 상기 기판의 상측에 투광성 커버를 접합하는 단계를 더 포함하는 것을 특징으로 하는 미소소자 패키지의 제조방법.
- 제31항에 있어서,상기 투광성 커버를 접합하는 단계는,상기 투광성 커버와 상기 기판의 상호 대향면 중 적어도 어느 일측에 실링패턴을 형성하는 단계; 및상기 실링패턴을 피접착면에 접착하는 단계;를 포함하는 것을 특징으로 하는 미소소자 패키지의 제조방법.
- 제32항에 있어서,상기 실링패턴은 상기 전극패드를 덮도록 형성되는 것을 특징으로 하는 미소소자 패키지의 제조방법.
- 제32항에 있어서,상기 실링패턴은 에폭시 수지로 형성된 것을 특징으로 하는 미소소자 패키 지.
- 제23항에 있어서,상기 미소소자는 마이크로기계공학적 소자, 마이크로전자공학적 소자, 광전자공학적 소자 중 어느 하나인 것을 특징으로 하는 미소소자 패키지의 제조방법.
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