WO2019160517A2 - A method for improving the flip-chip bonding process - Google Patents

A method for improving the flip-chip bonding process Download PDF

Info

Publication number
WO2019160517A2
WO2019160517A2 PCT/TR2019/050015 TR2019050015W WO2019160517A2 WO 2019160517 A2 WO2019160517 A2 WO 2019160517A2 TR 2019050015 W TR2019050015 W TR 2019050015W WO 2019160517 A2 WO2019160517 A2 WO 2019160517A2
Authority
WO
WIPO (PCT)
Prior art keywords
reading circuit
layer
ubm
flip
chip bonding
Prior art date
Application number
PCT/TR2019/050015
Other languages
French (fr)
Other versions
WO2019160517A3 (en
Inventor
Tolga YELBOĞA
Original Assignee
Aselsan Elektroni̇k Sanayi̇ Ve Ti̇caret Anoni̇m Şi̇rketi̇
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aselsan Elektroni̇k Sanayi̇ Ve Ti̇caret Anoni̇m Şi̇rketi̇ filed Critical Aselsan Elektroni̇k Sanayi̇ Ve Ti̇caret Anoni̇m Şi̇rketi̇
Publication of WO2019160517A2 publication Critical patent/WO2019160517A2/en
Publication of WO2019160517A3 publication Critical patent/WO2019160517A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14634—Assemblies, i.e. Hybrid structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/1469—Assemblies, i.e. hybrid integration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
    • H01L2224/03472—Profile of the lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
    • H01L2224/03474—Multilayer masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
    • H01L2224/0348—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16112—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16147—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/81139—Guiding structures on the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector

Definitions

  • the invention relates to a method for improving the Flip-Chip Bonding (FCB) process using a focal plane array (FPA) and read-out integrated circuit (ROIC).
  • FCB Flip-Chip Bonding
  • FPA focal plane array
  • ROIC read-out integrated circuit
  • the invention is particularly concerned with the method that solves the problem caused by a high-thickness passivation layer on the read-out integrated circuit to improve detector production involving FCB processes, ensures that indium solder balls in flip-chip bonding operations are in full contact with the reading circuit and reduces the dead pixel value in the detector.
  • FCB processing is used in combination with ROIC and FPA in the production of infrared detectors.
  • the problem encountered in the FCB process can be explained as follows: in the production of infrared detectors, the ROIC and FPA merging process requires the preparation of solder balls on the samples. These solder balls can be gold, silver or lead, as well as indium metal.
  • a special metal coating is required to be applied to the region before the solder balls so that these solder balls are well adhered to both the ROIC and FPA surfaces and are prevented from entering the sample surface over time. This metal coating step is called UBM (Under Bump Metallization) layer.
  • UBM is selected according to the material of the solder balls to be used.
  • the passivation coating thickness found in some ROIC top layer can be high (> 2 urn).
  • the UBM metal coated on the ROIC for flip chip bonding process shows discontinuity due to the thick passivation coating on the top layer.
  • a rupture occurs in the lower part of the thick passivation layer of the UBM metal.
  • the thickness of the passivation layer which causes the UBM discontinuity is not standard. This means that all passivation thickness will not be the same, and it can vary depending on the ROIC design and the process flow of the ROIC manufacturing house. Different methods can be applied to ensure UBM continuity.
  • UBM metal can change the contact resistances coming from the detector, causing the detector to underperform.
  • very thick UBM metal coatings will challenge the lift-off process to be carried out in the next step.
  • PVD physical vaporization techniques
  • the discontinuity (rupture) in the UBM metal causes the following types of problems in the further stages of the detector production: During the alignment-bonding process, the indium solder balls adhere to the UBM metal. During the bonding of FPA with ROIC, solder balls that do not come into contact due to the gap seen in Figure 4 are formed. These solder balls that do not come into contact are called dead pixels in infrared detectors and affect the performance of the detector.
  • the invention is inspired by the existing circumstances and aims to solve the above- mentioned drawbacks.
  • the purpose of the invention is to remove the dead pixels which will be formed due to the passivation thickness of the reading circuit in the detectors to be used in the infrared detection.
  • the purpose of photolithography is to mask the wafer surface. By masking, different zones can be obtained in the abrasion and coating processes.
  • the photolithography process is the process of shaping a polymer (photo-resist), which is laid on a wafer, with a semiconductor mask designed according to the contents of the process. In the forming process, ultraviolet wavelength light is used in which the polymer is sensitive and its structure is deteriorated. The process is then completed with a chemical (developer). With the degradation of the light-curing polymers and the steadiness of the non-light-curing polymers, the shapes on the semiconductor mask are transferred to the wafer surface with the polymer used. At the present time, by using semiconductor technology, it is possible to produce complex structured chips and in order to produce these complex chips, sometimes up to 30 photolithography processes can be performed on the same chip.
  • Photoresist material in which wavelength it is sensitive and the thickness of the material is important.
  • Photoresist Spinner Performs homogeneous photoresist spreading by whirling the sample.
  • Developer Material Selected according to the photoresist used.
  • Semiconductor Mask can be made from Chrome or Soda-Lime material.
  • Mask Alignment and Exposure Device can make exposure with the Mercury Lamp.
  • Figure 1 is a view of the reading circuit and passivation layer in the prior art.
  • Figure 2 is a view of the UBM layer and the rupture in the UBM layer in the prior art.
  • Figure 3 is a view of the reading circuit with the focal plane array.
  • Figure 4 is a view of the gap formed by merging the focus plane array and the reading circuit.
  • Figure 5 is a view of the photoresist layer constructed in the method of the invention.
  • Figure 6 is a view of the passivation layer that is eroded in the method of the invention.
  • Figure 7 is a view of the UBM coating in the method of the invention.
  • Figure 8 is a view of the photoresist removed UBM coating in the method of the invention.
  • Figure 9 is a view of the reading circuit with the focal plane array in the method of the invention.
  • Figure 10 is a view showing the merged reading circuit with the focal plane array in the method of the invention.
  • the photolithography (forming the photoresist layer (2)) of the UBM layer (4) is performed on the reading circuit (1 ) (ROIC).

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

The invention relates to a method to reduce the number of dead pixels in flip-chip bonding process using a focal plane array (5) and a reading circuit (1), wherein; it comprises the 5 process steps of forming the photoresist layer (2) on the reading circuit (1), etching by using the thickness of the passivation layer (3) in the top layer of the reading circuit (1), coating over the reading circuit (1) with the UBM layer (4), and removing the photoresist layer (2) by applying a lift-off process to the reading circuit (1).

Description

A METHOD FOR IMPROVING THE FLIP-CHIP BONDING PROCESS
Technical Field
The invention relates to a method for improving the Flip-Chip Bonding (FCB) process using a focal plane array (FPA) and read-out integrated circuit (ROIC).
The invention is particularly concerned with the method that solves the problem caused by a high-thickness passivation layer on the read-out integrated circuit to improve detector production involving FCB processes, ensures that indium solder balls in flip-chip bonding operations are in full contact with the reading circuit and reduces the dead pixel value in the detector.
Prior Art
Today, FCB processing is used in combination with ROIC and FPA in the production of infrared detectors. The problem encountered in the FCB process can be explained as follows: in the production of infrared detectors, the ROIC and FPA merging process requires the preparation of solder balls on the samples. These solder balls can be gold, silver or lead, as well as indium metal. A special metal coating is required to be applied to the region before the solder balls so that these solder balls are well adhered to both the ROIC and FPA surfaces and are prevented from entering the sample surface over time. This metal coating step is called UBM (Under Bump Metallization) layer.
UBM is selected according to the material of the solder balls to be used. As it can be seen in Figure 2, the passivation coating thickness found in some ROIC top layer can be high (> 2 urn). The UBM metal coated on the ROIC for flip chip bonding process shows discontinuity due to the thick passivation coating on the top layer. In other words, as can be seen in Figure 2, a rupture occurs in the lower part of the thick passivation layer of the UBM metal. On the ROIC, the thickness of the passivation layer which causes the UBM discontinuity is not standard. This means that all passivation thickness will not be the same, and it can vary depending on the ROIC design and the process flow of the ROIC manufacturing house. Different methods can be applied to ensure UBM continuity. One of them is to increase the thickness of UBM metal. However, the disadvantages of this method can be as follows: Different layer UBM metals can change the contact resistances coming from the detector, causing the detector to underperform. In addition, very thick UBM metal coatings will challenge the lift-off process to be carried out in the next step. Different physical vaporization techniques (PVD) can be used for UBM metal. Even if different coating techniques are used, the problem encountered in the UBM metal described above cannot be overcome.
The discontinuity (rupture) in the UBM metal causes the following types of problems in the further stages of the detector production: During the alignment-bonding process, the indium solder balls adhere to the UBM metal. During the bonding of FPA with ROIC, solder balls that do not come into contact due to the gap seen in Figure 4 are formed. These solder balls that do not come into contact are called dead pixels in infrared detectors and affect the performance of the detector.
In the prior art, a patent application entitled as "Methods of Manufacturing Stress Buffer Structures in a Mounting Structure of a Semiconductor Device" with a patent no. US 20130109169 A1 refers to a semiconductor that is formed to comprise of a gradual strain buffer layer under the gradual UBM structure. However, in the structure of that application, it is not possible to ensure that the indium solder balls are in full contact with the reading circuit during flip-chip bonding operations and also that the dead pixel value in the detector is reduced.
As a result, due to the above-mentioned drawbacks and the inadequacy of the existing solutions, an improvement in the technical field has been required.
The Purpose of Invention
The invention is inspired by the existing circumstances and aims to solve the above- mentioned drawbacks.
The purpose of the invention is to remove the dead pixels which will be formed due to the passivation thickness of the reading circuit in the detectors to be used in the infrared detection.
Another purpose of the invention is to perform a photolithography without any misalignment on the ROIC. The purpose of photolithography is to mask the wafer surface. By masking, different zones can be obtained in the abrasion and coating processes. The photolithography process is the process of shaping a polymer (photo-resist), which is laid on a wafer, with a semiconductor mask designed according to the contents of the process. In the forming process, ultraviolet wavelength light is used in which the polymer is sensitive and its structure is deteriorated. The process is then completed with a chemical (developer). With the degradation of the light-curing polymers and the steadiness of the non-light-curing polymers, the shapes on the semiconductor mask are transferred to the wafer surface with the polymer used. At the present time, by using semiconductor technology, it is possible to produce complex structured chips and in order to produce these complex chips, sometimes up to 30 photolithography processes can be performed on the same chip.
Devices and materials used in the process of photolithography:
• Photoresist material: in which wavelength it is sensitive and the thickness of the material is important.
• Photoresist Spinner: Performs homogeneous photoresist spreading by whirling the sample.
• Developer Material: Selected according to the photoresist used.
• Semiconductor Mask: can be made from Chrome or Soda-Lime material.
• Mask Alignment and Exposure Device: can make exposure with the Mercury Lamp.
(320 nm-365 nm-415 nm)
The structural and characteristic features and all advantages of the invention outlined in the drawings below and in the detailed description made by referring these figures will be understood clearly, therefore the evaluation should be made by taking these figures and detailed explanation into consideration.
Brief Description of the Figures
Figure 1 is a view of the reading circuit and passivation layer in the prior art.
Figure 2 is a view of the UBM layer and the rupture in the UBM layer in the prior art.
Figure 3 is a view of the reading circuit with the focal plane array.
Figure 4 is a view of the gap formed by merging the focus plane array and the reading circuit.
Figure 5 is a view of the photoresist layer constructed in the method of the invention. Figure 6 is a view of the passivation layer that is eroded in the method of the invention.
Figure 7 is a view of the UBM coating in the method of the invention.
Figure 8 is a view of the photoresist removed UBM coating in the method of the invention.
Figure 9 is a view of the reading circuit with the focal plane array in the method of the invention.
Figure 10 is a view showing the merged reading circuit with the focal plane array in the method of the invention.
Reference Numbers
1 . Reading circuit
2. Photoresist layer
3. Passivation layer
4. UBM layer
5. Focal plane array
6. Gap
7. Disconnection zone
8. Connection pad
9. Solder ball
Detailed Description of the Invention
In this detailed description, the preferred structures of the method for improving the alignment and merging process of the invention are described only for a better understanding of the subject.
The process steps involved in the method for improving the alignment and merge process of the invention are as follows:
• As shown in Figure 5, the photolithography (forming the photoresist layer (2)) of the UBM layer (4) is performed on the reading circuit (1 ) (ROIC).
• As shown in Figure 6, dry etching is made using the RIE/Reactive Ion Etching system taking into account the thickness of the passivation layer (3) at the top layer of the reading circuit (1 ). The studies have shown that the ruptures in the UBM layer (4) are observed when the thickness of the passivation layer (3) is greater than 2 microns (> 2 microns). The studies also show that when the thickness of the passivation layer (3) is less than 1 micron after the etching, it does not lead to dead pixels. In this way, the thick passivation layer (3) on top layer of the reading circuit (1 ) is etched. The etched passivation layer (3) is shown in Figure 6.
· The UBM layer (4) is covered before the photoresist layer (2) on the reading circuit
(1 ) is cleaned (Figure 7).
• The photoresist layer (2) is removed by applying the lift-off process to the reading circuit (1 ) (Figure-8). In this way, a continuous coating of the UBM layer (4) is obtained on the reading circuit (1 ). By means of the invention, the gap (6) problem encountered in the prior art is not seen when the reading circuit (1 ) and the focus plane array (5) are hybridized (Figure 4). Therefore, the dead pixels encountered in the prior art are eliminated with the help of the method of the invention.

Claims

1. A method to reduce the number of dead pixels in flip-chip bonding process using a focal plane array (5) and a reading circuit (1 ), wherein; it comprises the process steps of,
• forming the photoresist layer (2) on the reading circuit (1 ),
• etching by using the thickness of the passivation layer (3) in the top layer of the reading circuit (1 ),
• coating over the reading circuit (1 ) with the UBM layer (4),
• removing the photoresist layer (2) by applying a lift-off process to the reading circuit (1 ).
2. A method according to Claim 1 , wherein; it comprises of dry etching in the passivation layer (3) by means of reactive ion etching in the process.
PCT/TR2019/050015 2018-02-15 2019-01-08 A method for improving the flip-chip bonding process WO2019160517A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TR2018/02169 2018-02-15
TR201802169 2018-02-15

Publications (2)

Publication Number Publication Date
WO2019160517A2 true WO2019160517A2 (en) 2019-08-22
WO2019160517A3 WO2019160517A3 (en) 2019-09-12

Family

ID=66397403

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/TR2019/050015 WO2019160517A2 (en) 2018-02-15 2019-01-08 A method for improving the flip-chip bonding process

Country Status (1)

Country Link
WO (1) WO2019160517A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113471061A (en) * 2021-06-30 2021-10-01 颀中科技（苏州）有限公司 Preparation method of wafer surface dielectric layer, wafer structure and forming method of bump

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130109169A1 (en) 2010-02-01 2013-05-02 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of manufacturing stress buffer structures in a mounting structure of a semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4827326A (en) * 1987-11-02 1989-05-02 Motorola, Inc. Integrated circuit having polyimide/metal passivation layer and method of manufacture using metal lift-off
JPH0485961A (en) * 1990-07-30 1992-03-18 Mitsubishi Electric Corp Optical sensor
US20120168210A1 (en) * 2011-01-05 2012-07-05 International Business Machines Corporation Methods and Structures Involving Terminal Connections

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130109169A1 (en) 2010-02-01 2013-05-02 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of manufacturing stress buffer structures in a mounting structure of a semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113471061A (en) * 2021-06-30 2021-10-01 颀中科技（苏州）有限公司 Preparation method of wafer surface dielectric layer, wafer structure and forming method of bump

Also Published As

Publication number Publication date
WO2019160517A3 (en) 2019-09-12

Similar Documents

Publication Publication Date Title
KR101033078B1 (en) Semiconductor package including through-hole electrode and light-transmitting substrate
US6387793B1 (en) Method for manufacturing precision electroplated solder bumps
US8492892B2 (en) Solder bump connections
KR100319813B1 (en) method of forming solder bumps with reduced UBM undercut
US6479900B1 (en) Semiconductor device and method of manufacturing the same
US6756294B1 (en) Method for improving bump reliability for flip chip devices
US20080050905A1 (en) Method of manufacturing semiconductor device
US20040157450A1 (en) Waferlevel method for direct bumping on copper pads in integrated circuits
KR100593162B1 (en) Image sensor and method for fabricating the same
US7541275B2 (en) Method for manufacturing an interconnect
CN111739806A (en) Indium ball array manufacturing method of focal plane detector with small center distance
US20100167432A1 (en) Method of manufacturing semiconductor device
US20060264021A1 (en) Offset solder bump method and apparatus
WO2019160517A2 (en) A method for improving the flip-chip bonding process
US6716669B2 (en) High-density interconnection of temperature sensitive electronic devices
US6528417B1 (en) Metal patterned structure for SiN surface adhesion enhancement
CN104037091B (en) Electrical connector and forming method thereof
JP5587899B2 (en) Method of making a detector suitable for oxide coupling with a readout integrated chip
US20230116270A1 (en) Integrated Circuit Features with Obtuse Angles and Method of Forming Same
KR101416596B1 (en) Semiconductor packages and methods for fabricating the same
US11495558B2 (en) Integrated circuit features with obtuse angles and method of forming same
US8664090B1 (en) Electronic component package fabrication method
JP2006332694A (en) Method for forming metal bumps on semiconductor surface
KR101418440B1 (en) Semiconductor packages and methods for fabricating the same
KR100915752B1 (en) Method for Manufacturing A Image Sensor

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19721872

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19721872

Country of ref document: EP

Kind code of ref document: A2