KR101416596B1 - Semiconductor packages and methods for fabricating the same - Google Patents

Abstract

The present invention relates to a semiconductor package and a manufacturing method thereof.
A semiconductor package of the present invention includes: a semiconductor substrate having a plurality of bonding pads spaced apart from each other; An insulating layer formed on the semiconductor substrate so as to have an opening exposing the bonding pad; A metal base layer formed on the bonding pad and the insulating layer; A solder bump formed on the metal base layer to be electrically connected to the bonding pad; And an etch stop layer formed on the base layer to surround the solder bumps.
According to the present invention, occurrence of undercut can be minimized in the metal base layer etching.

Description

Technical Field [0001] The present invention relates to a semiconductor package,

The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package capable of minimizing occurrence of undercuts when a metal base layer is etched to form a solder bump on a semiconductor chip, and a manufacturing method thereof.

BACKGROUND ART [0002] Semiconductor packages have been used in various products. In recent years, in order to reduce the size of a semiconductor package in accordance with the tendency of thinning and shortening of products, a flip chip package or a bonding pad (TSV) through electrodes (Through Silicone Via) and solder bumps are formed on the through electrodes.

One of the most important processes in this flip chip package technology is the process of forming solder bumps. In general, solder bumps are formed by deposition or electroplating. The deposition method is relatively simple in process, but is limited in application when the pad pitch is reduced. Therefore, in recent years, bumps are formed by electrolytic plating.

On the other hand, a so-called under-bump metallization (UBM) is formed between the solder bump and the bonding pad, and the metal base layer is generally formed by an electrolytic plating method having good bonding force. That is, after a seed layer is formed and a current is applied to form a metal base layer, the seed layer is etched together with the metal base layer in the final structure and patterned in the same manner as the metal base layer.

In the etching process, however, an undercut region is inevitably formed at the bottom of the seed layer.

FIG. 1 is a process sectional view for explaining a solder bump forming method according to the prior art, showing a situation where an undercut has occurred in a metal base layer.

1A, a bonding pad 12 is formed on a semiconductor chip 10, and a protective layer 14 and a buffer layer 16 are formed on the surface of the semiconductor chip 10 except for the bonding pad 12 . The metal base layer 18 is formed over the entire surface of the semiconductor chip 10, the protective film 14 and the buffer layer 16 and forms a multilayer structure 18a and 18b. A solder bump 20 is formed on the metal base layer 18 above the bonding pad 12.

1B shows a state where undercuts are generated in the metal base layers 18a and 18b after the underlying metal base layer 18 is etched using the solder bumps 20 as a mask. The undercut is a phenomenon in which the metal base layer 18 is excessively etched below the solder bump 20. When the undercut occurs, the underbase is formed between the metal base layer 18 and the solder bumps 20, between the metal base layer 18 and the buffer layer 16 The contact area of the contact surface is reduced.

If the contact area between the metal base layer 18 and the solder bump 20 is reduced, the height of the solder bumps formed through the reflow process subsequent to the subsequent process will vary greatly depending on the degree of undercut occurring in each bump. In addition, a reduction in the contact area between the metal base layer 18 and the buffer layer 16 results in a reduction in the shear strength of the bumps, all of which reduce the physical and electrical reliability of the solder bumps, Thereby deteriorating the reliability of the semiconductor package.

A conventional technique for solving such a problem is disclosed in European Patent No. 0603296. According to the prior art, there is disclosed a technique of melting a solder bump before etching a metal base layer to form an intermetallic compound layer at an interface between the solder bump and the metal base layer, and etching the metal base layer using the intermetallic compound layer. However, according to this conventional technique, since a solder dam must be formed on the metal base layer between the bumps in order to prevent the molten solder bumps from flowing into the metal base layer, it is not suitable for the bump structure of fine pitches and the solder dam forming and removing process There is a problem that the process becomes complicated.

On the other hand, US Pat. No. 5,902,686 discloses a technique of melting a solder bump before etching a metal base layer without forming a solder dam and etching the metal base layer using the resulting intermetallic compound layer as a mask. According to the prior art, an oxide film is formed on the bump surface instead of the solder dam in order to prevent the molten solder from flowing down. However, since the annealing film is formed not only on the surface of the solder bump but also on the upper part of the metal base layer, in order to etch the metal base layer after forming the intermetallic compound layer, a step of removing the oxide film first is required, .

European Patent 0603296 U.S. Patent No. 5,902,686

SUMMARY OF THE INVENTION Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and it is an object of the present invention to provide a semiconductor package capable of minimizing an undercut occurring in removing a metal base layer for forming a solder bump, will be.

To this end, a semiconductor package according to an embodiment of the present invention includes: a semiconductor substrate having a plurality of bonding pads spaced apart from each other; An insulating layer formed on the semiconductor substrate so as to have an opening exposing the bonding pad; A metal base layer formed on the bonding pad and the insulating layer; A solder bump formed on the metal base layer to be electrically connected to the bonding pad; And an etch stop layer formed on the metal base layer to surround the solder bumps.

In the semiconductor package of the embodiment of the present invention, the etch stop layer may be formed of a metal equivalent to the metal forming the metal base layer or a polyimide-based material having a lower water absorption property to the etching solution for forming the metal base layer pattern than the metal base layer have.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor package, comprising: (a) forming an insulating layer on a semiconductor substrate having a plurality of bonding pads such that an upper surface of the bonding pad is exposed; (b) forming a metal base layer on the bonding pad and the insulating layer; (c) forming a first mask pattern on the metal base layer to expose the metal base layer in a predetermined solder bump forming area; (d) forming a solder bump on the exposed metal base layer; (e) forming a second mask pattern on the first mask pattern and the solder bump such that the first mask pattern of the predetermined etch stop layer formation region of the solder bump edge is exposed; (f) etching the first mask pattern by an etching process using the second mask pattern as a mask to expose the metal base layer in a predetermined etching prevention layer formation region; (g) forming an etch stop layer over the exposed underlying metal layer; (h) removing the first mask pattern and the second mask pattern; (i) removing the metal base layer by an etching process using the solder bump and the etch stopper layer as a mask.

In the method of manufacturing a semiconductor package according to an embodiment of the present invention, the first mask pattern and the second mask pattern may be made of photoresist.

In the method for manufacturing a semiconductor package according to an embodiment of the present invention, the step (f) may be performed by a dry etching process.

In the method for fabricating a semiconductor package according to an embodiment of the present invention, the step (g) may include a step of forming a metal layer having a lower absorption coefficient than the metal base layer in the electroplating process or the etching solution used for removing the metal base layer in the step (i) . ≪ / RTI >

According to the semiconductor package and the method of manufacturing the same according to the present invention, it is possible to improve the physical and electrical reliability of the solder bump by minimizing the occurrence of undercuts in the metal base layer etching by forming the etch stop layer in the metal base layer extended portion to surround the solder bump edges.

1 is a cross-sectional view illustrating a conventional solder bump forming method.
2 is a cross-sectional view illustrating a structure of a semiconductor package according to an embodiment of the present invention.
3A to 3J are cross-sectional views illustrating a semiconductor package manufacturing process according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In addition, the terms described below are defined in consideration of the functions of the present invention, and these may vary depending on the intention or precedent of the user. Therefore, the definition should be based on the contents throughout this specification.

2 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

2, the semiconductor package 100 according to the present embodiment includes a semiconductor substrate 110, a bonding pad 120 formed on one side of the semiconductor substrate 110, And a metal base layer 140 formed on the bonding pad 120 and the insulating layer 130. The metal base layer 140 is formed on the upper surface of the semiconductor base 110, And an etch stop layer 160 formed to surround the solder bump 150 at the edge of the metal base layer 140. The solder bump 150 is formed on the solder bump 150,

Although not shown in the figure, the semiconductor substrate 110 includes a plurality of semiconductor elements in its inside (active region).

A plurality of bonding pads 120 are provided on the semiconductor substrate 110 for inputting / outputting electrical signals to and from the semiconductor substrate 110 and may be formed of a metal having a low specific resistance such as aluminum (Al) or copper (Cu) Lt; / RTI >

The insulating layer 130 is formed on the upper portion of the semiconductor substrate 110 except the region where the bonding pad 120 is formed so that the semiconductor substrate 110 is insulated in a region other than the bonding pad 120. The insulating layer 130 protects the upper surface of the semiconductor substrate 110 from external impurities, physical impact, and the like. The insulating layer 130 may be formed of a plurality of layers and the material thereof may be an oxide film, a nitride film, a polyimide (PI), a benzoxycyclobutene (BCB), a polybenzoxazole ), BT (bismaleimide triazine), phenolic resin, epoxy or the equivalent thereof.

The metal base layer 140 is formed over the entire surface of the exposed bonding pad 120 and the insulating layer 130 and may be formed by a thin film deposition process such as sputtering or evaporation. The metal base layer 140 has a multilayer structure of, for example, a titanium tungsten (TiW) layer 142 and a copper (Cu) layer 144 and may include other metals such as Ni, Ti ), Tungsten (W), tin (Sn), silver (Ag) or the like may be used as the metal base layer 140.

The titanium tungsten (TiW) layer 142 serves as an adhesive layer and a diffusion barrier layer, and the copper (Cu) layer 144 functions as a solder spread layer during solder reflow. In addition, the copper layer 144 functions as a seed for forming the solder bumps 150. That is, when the solder bump 150 is formed by an electro-plating method, the copper layer provides a path through which a current can flow so that the solder bump 150 can be formed on the copper layer.

The solder bump 150 is formed on the metal base layer 140 to electrically connect an external circuit such as a PCB substrate (not shown) to the semiconductor substrate 110. The solder bump 150 includes a stud 152, (154). The stud 152 may be formed on the metal base layer 140 and may be for adjusting the height of the solder bump 150. That is, the stud 152 can secure the height of the solder bump 150 necessary for connecting the semiconductor substrate 110 and the PCB substrate (not shown). For this purpose, the stud 152 may be set to a height of 30 [mu] m to 50 [mu] m. In addition, the solder ball 154 may be formed in a hemispherical shape on the stud 152.

The etch stop layer 160 is formed to surround the solder bump 150 at the edge of the solder bump 150 to extend the metal base layer 140 so that the etch stop layer 160 has a function of preventing the undercut when the metal base layer 140 is etched. do. The etch stop layer 160 may have a lower absorptivity than that of the metal base layer 140 in the etching process for forming a metal or metal base layer pattern equivalent to a metal of the metal base layer 140.

As described above, the semiconductor package according to the present embodiment can minimize the occurrence of undercuts when the underlying metal base layer is etched by forming the metal base layer extension portion, that is, the etch stop layer to surround the solder bumps on the side walls of the solder bumps.

In addition, the semiconductor package according to the present embodiment can prevent the solder bumps from being lifted off by forming an etch stop layer having a fine pattern on the side walls of the solder bumps.

3A to 3J are cross-sectional views illustrating a semiconductor package manufacturing process according to an embodiment of the present invention.

First, as shown in FIG. 3A, a plurality of bonding pads 120 are formed on a semiconductor substrate 110, and then an insulating layer 130 is formed on the semiconductor substrate 110 excluding the bonding pads 120. Here, the bonding pad 120 is formed of a metal having a low non-static characteristic such as aluminum (Al) or copper (Cu), and the insulating layer 130 is formed of an oxide film, a nitride film, a polyimide (PI), a benzoxycyclobutene , BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), phenolic resin, epoxy, or an equivalent thereof. In addition, although the insulating layer 130 is formed as one layer in this embodiment, it is needless to say that the insulating layer 130 may be formed of a plurality of layers.

Next, as shown in FIG. 3B, a metal base layer 140 is formed over the entire surface of the bonding pad 120 and the insulating layer 130. The metal base layer 140 is formed of a multilayer of a first metal layer 142 serving as an adhesive layer and a diffusion preventing layer and a second metal layer 144 serving as a solder spreading layer and is formed by sputtering or evaporation May be formed by a thin film deposition process. In this embodiment, the first metal layer 142 may be an alloy of titanium and tungsten (TiW), the second metal layer 144 may be formed of copper (Cu), and other metals such as nickel (Ni) And may be formed of a metal such as titanium (Ti), tungsten (W), tin (Sn), silver (Ag), or the like. In addition, the second metal layer 144, that is, the copper layer, functions as a seed for forming the solder bumps 150. That is, when the solder bump is formed by an electro-plating method, the copper layer provides a path through which a current can flow so that a solder bump can be formed on the solder bump.

3C, a first photoresist pattern 171 is formed on the second metal layer 144 to expose the upper surface of the second metal layer 144 in the predetermined solder bump forming area 150a. The first photoresist pattern 171 is formed by applying a first photoresist on the entire surface of the second metal layer 144 to a thickness of about 40 to 50 μm by a general photolithography process, And removing the first photoresist of the first photoresist layer.

Next, a solder bump 150 is formed on the upper surface of the exposed second metal layer 144 as shown in FIG. 3D. Here, the solder bump 150 includes the stud 152 and the solder ball 154 and is made of an alloy such as copper (Cu), nickel (Ni), tin (Sn), lead (Pb), silver (Ag) As shown in FIG.

Next, as shown in FIG. 3E, a second photoresist pattern 172 is formed on the first photoresist pattern 171 and the solder bump 150 to form a first photoresist pattern 172 in a predetermined etching prevention layer 160 formation region, Thereby exposing the upper surface of the recess 171. Here, the second photoresist pattern 172 is formed on the entire surface of the solder bumps 150 and the first photoresist pattern 171 by a general photolithography process with a thickness of about 10 to 30 μm And then removing the second photoresist in the region where the predetermined etching preventing layer 160 is to be formed.

Next, as shown in FIG. 3F, the first photoresist pattern 171 is removed by a dry etching process using the second photoresist pattern 172 as an etching mask to form a metal base layer (Not shown). Here, the first photoresist and the second photoresist may be photoresists of polymethyl methacrylate (PMMA) or polyetheretherketone (PEEK). In addition to the etch stop layer formation region 160a predetermined by O ₂ plasma The second photoresist is removed by dry etching. In addition, the dry etching process may be performed after the second photoresist pattern 171 is partially removed by chemical mechanical polishing (CMP) before the dry etching process to reduce the thickness.

Etching Rate and Etching Depth according to Etching Time of PMMA and PEEK are as shown in FIG. Referring to FIG. 4, the etch rate is constant even with the elapse of the etching time, and the etch depth increases linearly with the elapse of the etch time, so that the proper etch time can be set in consideration of the thickness and the etch rate of the photoresist to be etched. Thus, the fine pattern region having a high aspect ratio can be removed by dry etching without an etch stop.

Next, an etch stop layer 160 is formed on the exposed metal base layer 140 as shown in FIG. 3G. The etch stop layer 160 is formed on the metal base extension 140a so as to surround the edge of the solder bump 150 and functions to prevent undercut when the metal base layer 140 is etched. The etch stop layer 160 may be formed of a material having a low etch rate with respect to the etch solution, for example, a metal or a polymer, when the wet etch process for removing the metal base layer 140 is performed. And when the etching preventing layer 160 is a metal, it can be formed by an electrolytic plating method.

Next, as shown in FIG. 3H, the first photoresist pattern 171 and the second photoresist pattern 172 used as masks for exposing the predetermined etching prevention layer formation region are removed.

Next, as shown in FIG. 3I, the metal base layer 140 under the etching prevention layer 160 is removed. Here, it can be confirmed that the undercut does not occur in the underlying metal base layer 140 by the etch stop layer 160 formed in the metal base extension 140a.

Next, a general solder reflow process may be performed to form the solder bump final structure as shown in FIG. 3J.

As described above, the method of manufacturing a semiconductor package according to the present embodiment minimizes the occurrence of undercuts when a metal base layer is etched by forming a metal base layer extension portion, that is, an etching prevention layer to surround the solder bumps on the side walls of the solder bumps.

In addition, the semiconductor package manufacturing method according to the present embodiment uses a photoresist pattern of a multilayer structure as a mask to form a fine pattern etch stopping layer on the side wall of the solder bump, thereby preventing the solder bump from being lifted off .

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and similarities. Accordingly, the scope of the present invention should be construed as being limited to the embodiments described, and it is intended that the scope of the present invention encompasses not only the following claims, but also equivalents thereto.

100: semiconductor package 110: semiconductor substrate
120: bonding pad 130: insulating layer
140: metal base layer 150: solder bump
160: etching prevention layer 171, 172: photoresist pattern

Claims (8)

delete delete delete (a) forming an insulating layer such that an upper surface of the bonding pad is exposed on a semiconductor substrate having a plurality of bonding pads;
(b) forming a metal base layer on the bonding pad and the insulating layer;
(c) forming a first mask pattern made of photoresist on the metal base layer to expose the metal base layer in a predetermined solder bump forming area;
(d) forming a solder bump on the exposed metal base layer;
(e) forming a second mask pattern made of photoresist on the first mask pattern and the solder bump to expose the first mask pattern in a predetermined etch stop layer formation region of the solder bump edge;
(f) etching the first mask pattern by a dry etching process using the second mask pattern as a mask to expose the metal base layer in a predetermined etch stop layer formation region;
(g) forming an etch stop layer over the exposed underlying metal layer;
(h) removing the first mask pattern and the second mask pattern;
(i) removing the metal base layer by an etching process using the solder bump and the etch stop layer as a mask.
delete delete 5. The method of claim 4, wherein step (g)
Wherein the plating is performed by an electrolytic plating process.
5. The method of claim 4, wherein step (g)
Wherein the absorptivity of the etching solution used for removing the metal base layer in the step (i) is lower than that of the metal base layer.

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