CN210640232U

CN210640232U - Semiconductor structure

Info

Publication number: CN210640232U
Application number: CN201922107979.3U
Authority: CN
Inventors: 庄凌艺
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2019-11-29
Filing date: 2019-11-29
Publication date: 2020-05-29
Anticipated expiration: 2029-11-29

Abstract

The utility model provides a semiconductor structure, which comprises a semiconductor substrate, a conductive layer, a lug and an intermetallic compound; the conducting layer is arranged on the semiconductor substrate; the bump is arranged on the conductive layer; the intermetallic compound is arranged on the bump, and the intermetallic compound is concave-convex. The utility model discloses a design intermetallic compound for unsmooth form, make it can block the fracture to extending all around, can minimize or prevent the extension and the electric connection trouble of the fracture between lug and the solder layer, effectively improve the yield.

Description

Semiconductor structure

Technical Field

The utility model discloses relate to the semiconductor technology field generally, particularly, relate to a semiconductor structure.

Background

After the chip is subjected to flip-chip packaging, when the chip is subjected to subsequent temperature cycle reliability test, cracks are often generated at the joint of a solder layer and a bump in a packaging structure, so that an electrical connection fault is caused, and the yield of the chip is reduced.

The above information disclosed in this background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not constitute prior art that is already known to a person of ordinary skill in the art.

SUMMERY OF THE UTILITY MODEL

A primary object of the present invention is to overcome at least one of the above-mentioned drawbacks of the prior art and to provide a semiconductor structure, which can minimize or prevent the extension and electrical connection failures of the cracks between the bumps and the solder layer, thereby effectively improving the yield.

In order to realize the purpose of the utility model, the utility model adopts the following technical scheme:

according to an aspect of the present invention, a semiconductor structure is provided, including a semiconductor substrate, a conductive layer, a bump, and an intermetallic compound; the conducting layer is arranged on the semiconductor substrate; the bump is arranged on the conductive layer; the intermetallic compound is arranged on the bump, and the intermetallic compound is concave-convex.

According to an embodiment of the present invention, one side of the bump away from the semiconductor substrate has a concave-convex surface.

According to an embodiment of the present invention, the concave-convex surface is a rough surface having a concave-convex shape.

According to an embodiment of the present invention, the roughness of the rough surface is greater than 0.2.

According to an embodiment of the present invention, the solder layer is disposed on the intermetallic compound.

According to an embodiment of the present invention, the solder layer has a concave-convex surface fitted with the intermetallic compound.

According to an embodiment of the present invention, the profile of the intermetallic compound is a comb-like structure.

According to the utility model discloses an embodiment still includes the under bump metal level, locates the lug with between the conducting layer.

According to an embodiment of the present invention, the under bump metal layer covers the side wall of the bump.

According to an embodiment of the present invention, the solder layer is disposed on the intermetallic compound; the solder layer is connected with the under bump metal layer and defines a closed cavity, and the bump is closed in the closed cavity.

According to the above technical scheme, the utility model discloses a semiconductor structure's advantage lies in with positive effect:

on the one hand, compare among the prior art semiconductor construction be planar structure's intermetallic compound, the utility model discloses a semiconductor construction's intermetallic compound is unsmooth form, and this intermetallic compound is the 3D structure promptly, when taking place a small crack in this intermetallic compound's somewhere, because the existence of 3D structure, can block the crack and extend all around, can minimize or prevent the extension and the electric connection trouble of the crack in the semiconductor construction, effectively improve the yield.

On the other hand, the concave-convex surface of the bump is a rough surface, so that the concave-convex surface is rougher, the contact area between the solder layer and the bump is further increased, intermetallic compounds formed between the bump and the solder layer form a wrinkled surface, and the wrinkled surface can more effectively prevent cracks from extending to the periphery.

In another aspect, the present invention provides a solder bump structure, wherein the solder bump is formed by a plurality of bumps and a plurality of recesses, and the solder bump is bonded to the solder layer by a bonding process.

Drawings

The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 is a schematic cross-sectional view of a semiconductor structure of the present invention according to an exemplary embodiment.

Fig. 2 is a schematic view of a concave-convex surface of a bump of the present invention, shown according to an exemplary embodiment.

Fig. 3 is a partially enlarged view of the uneven surface of the bump in fig. 1.

Fig. 4 is a flow chart illustrating a method of fabricating a semiconductor structure according to the present invention, according to an exemplary embodiment.

Fig. 5-10 are schematic cross-sectional views illustrating the fabrication process of the semiconductor structure of the present invention according to an exemplary embodiment.

Wherein the reference numerals are as follows:

210. semiconductor substrate

220. Conductive layer

230. Protective layer

240. First mask layer

241. First opening

250. Under bump metallurgy

260. Bump

261. Concave part

262. Convex part

270. Second mask layer

271. Second opening

280. The photoresist layer

290. Solder layer

291. Intermetallic compound

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.

Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". The terms "a," "an," "the," and "said" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first," "second," "third," and "fourth," etc. are used merely as labels, and are not limiting as to the number of their objects.

The utility model discloses a utility model people discovers in studying, adopts the flip-chip mode to encapsulate the chip after, in putting down or reliability Test processes such as Temperature Cycle Test (TCT), joint interface department between lug and the solder layer often produces the crack, and then causes the electric connection trouble, has reduced the yield of chip.

The utility model discloses a utility model people further discover in studying, and the interface department between lug and the solder layer often produces the reason of crack because interface department between lug and the solder layer can form InterMetallic Compound (IMC), because InterMetallic Compound is fragile, produces the crack more easily. The utility model discloses a utility model people still discovers, and the intermetallic compound that joint interface department formed between lug and the solder layer among the prior art all is planar structure, so, when certain department in planar structure produces small crack, because planar structure's existence, the crack is easier to extending all around, and then produces great longer crack, causes the electric connection trouble.

Based on this, the utility model provides a semiconductor structure, including semiconductor substrate, conducting layer, lug and intermetallic compound, the conducting layer is located on the semiconductor substrate, and on the conducting layer was located to the lug, intermetallic compound located on the lug, and intermetallic compound is unsmooth.

Compare semiconductor structure's among the prior art intermetallic compound that is planar structure, the utility model discloses a semiconductor structure's intermetallic compound is unsmooth form, and this intermetallic compound is the 3D structure promptly, when taking place a small crack in this intermetallic compound's somewhere, because the existence of 3D structure, can block the crack and extend all around, can minimize or prevent the extension and the electric connection trouble of the crack in the semiconductor structure, effectively improve the yield.

The structure, connection mode and functional relationship of the main components of the semiconductor structure according to the present invention will be described in detail with reference to the following embodiments.

As shown in fig. 1, in an example embodiment, the semiconductor structure includes a semiconductor substrate 210, a conductive layer 220, a passivation layer 230, a bump 260, and a solder layer 290, wherein the semiconductor structure may be a die, a wafer, or a portion of a semiconductor package.

In an embodiment of the present invention, the semiconductor substrate 210 has a predetermined functional circuit. In an embodiment of the present invention, the semiconductor substrate 210 includes a plurality of conductive lines and a plurality of electronic components, such as transistors and diodes (not shown), connected by the plurality of conductive lines. In an embodiment of the present invention, the semiconductor substrate 210 is a wafer. In embodiments of the present invention, the semiconductor substrate 210 comprises a semiconductor material, such as silicon, germanium, gallium, arsenic and combinations thereof, and other semiconductor materials including group III, group IV and group V elements may also be used. In an embodiment of the present invention, the semiconductor substrate 210 is a silicon substrate. In embodiments of the present invention, the semiconductor substrate 210 is a quadrilateral, a rectangle, a square, a polygon, or any other suitable shape.

In an embodiment of the present invention, the semiconductor substrate 210 may further include an interlayer dielectric layer and a metallization structure overlying the integrated circuit. The interlevel dielectric layer in the metallization structure may comprise a low-k dielectric material, Undoped Silicate Glass (USG), silicon nitride, silicon oxynitride, or other commonly used materials. The low-k dielectric material may have a dielectric constant (k value) of less than about 3.9, or less than about 2.8. The metal lines in the metallization structure may be formed of copper, aluminum, or copper alloys. Those skilled in the art will recognize the detailed structure of the metallization layers and will not be described in detail herein.

In an example embodiment, the conductive layer 220 is disposed on the semiconductor substrate 210. In an exemplary embodiment, the conductive layer 220 is disposed on a front surface (or active surface) of the semiconductor substrate 210, wherein a circuit or an electronic component, etc., is disposed on the front surface (or active surface). In an example embodiment, the conductive layer 220 is electrically connected to a circuit or an electronic element in the semiconductor substrate 210. In an example embodiment, the conductive layer 220 is electrically connected to a circuit outside the semiconductor substrate 210, and thus the circuit in the semiconductor substrate 210 may be electrically connected to the circuit outside the semiconductor substrate 210 through the conductive layer 220. In an example embodiment, the conductive layer 220 is configured to receive a conductive structure. In an example embodiment, the conductive layer 220 may include, but is not limited to, gold, silver, copper, nickel, tungsten, aluminum, palladium, and/or alloys thereof.

In an example embodiment, if the conductive layer 220 is made of copper, a copper diffusion barrier layer (not shown) is provided to surround the conductive layer 220 to prevent copper from diffusing into the area of the semiconductor substrate 210. In an example embodiment, the copper diffusion barrier layer may include, but is not limited to, titanium nitride, tantalum nitride, and/or combinations thereof.

In an example embodiment, the conductive layer 220 may be formed by electrochemical plating, electroless plating, sputtering, Chemical Vapor Deposition (CVD), or the like. If a conductive layer 220 of copper is deposited using an electroplating process, a copper seed layer (not shown) may be used to increase the copper plating rate and quality. In some embodiments, the copper seed layer is formed by a sputter deposition or CVD process.

In an exemplary embodiment, the bump 260 is disposed on the conductive layer 220 and electrically connected to the conductive layer 220. In an exemplary embodiment, the bump 260 may be made of copper, and it is worth mentioning that the term "copper" refers to pure copper simple substance or a copper alloy containing a small amount of other elements, such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum or zirconium. In an example embodiment, the bump 260 may be formed by sputtering, printing, electroplating, electroless plating, or Chemical Vapor Deposition (CVD). In an exemplary embodiment, the cross-section of the bump 260 may be circular, rectangular, quadrangular, or polygonal.

In an exemplary embodiment, a side of the bump 260 away from the semiconductor substrate 210 (i.e., a surface where the bump 260 is bonded to the solder layer 290) has a concave-convex surface. In an exemplary embodiment, the cross-section of the concave-convex surface may be a sawtooth structure, a wave structure, a comb-like structure, or other 3D structures, or a combination thereof.

As shown in fig. 2, the bump of the present invention is schematically illustrated according to an exemplary embodiment. In an example embodiment, the concave-convex surface of the bump 260 includes a plurality of convex portions 262 and a plurality of concave portions 261 arranged at intervals, the plurality of concave portions 261 in one row or one column form an opening, and the plurality of convex portions 262 in one row or one column form a barrier layer structure. However, the uneven surface of the bump of the present invention is not limited to the structure shown in fig. 2, and in other embodiments, the uneven surface of the bump may be a shape with one side lower and one side higher, or a shape with two sides higher and one middle lower. During the reflow process after the chip bonding, some bumps 260 are compressed due to thermal deformation of the package substrate, so that the solder of the solder layer 290 overflows, and bridges are formed between adjacent bumps 260, thereby causing functional failure. The utility model discloses a surface design of lug 260 with the joint of solder layer 290 is concave-convex surface, designs for the isolation layer structure through a plurality of concave parts 261 with concave-convex surface and a plurality of convex part 262 to guide the overflow direction of solder layer 290 solder, make its overflow toward the adjacent lug that the distance is the farthest, with can minimize or prevent the solder bridge problem that arouses because the base plate warp.

In an example embodiment, solder layer 290 is disposed on intermetallic 291. The intermetallic compound 291 is a 3D structure, which increases the contact area between the solder layer 290 and the bump 260; on the other hand, when a micro crack occurs at a certain position of the intermetallic compound, the existence of the 3D structure can block the crack from extending to the periphery, thereby minimizing or preventing the extension of the crack in the semiconductor structure and the electrical connection failure, and effectively improving the yield.

In an exemplary embodiment, the solder layer 290 is disposed on the bump 260. Solder layer 290 may include nickel, tin-lead (SnPb), gold (Au), silver, palladium (Pd), indium (In), nickel-palladium-gold (NiPdAu), nickel-gold (NiAu), or other similar materials, or alloys. In one embodiment, the solder layer 290 includes tin.

As shown in fig. 3, fig. 3 is a partially enlarged view of the uneven surface of the bump in fig. 1. In an exemplary embodiment, the concave-convex surface of the bump 260 is a rough surface, so that the concave-convex surface is rougher, the contact area between the solder layer 290 and the bump 260 is further increased, and the intermetallic compound between the bump 260 and the solder layer 290 forms a wrinkled surface, which more strongly blocks the crack from extending to the periphery. In an example embodiment, the surface roughness of the concave-convex surface of the bump 260 is greater than 0.2, so that the anti-crack property of the intermetallic compound is stronger.

As shown in fig. 1, in an exemplary embodiment, the semiconductor device further includes a protection layer 230, the protection layer 230 is disposed on the semiconductor substrate 210 and exposes an exposed region of the conductive layer 220, and the bump 260 is disposed on the exposed region to be electrically connected to the conductive layer 220. In an example embodiment, the protective layer 230 includes a passivation layer and a polymer layer.

In an exemplary embodiment, the passivation layer may be made of a dielectric material, such as silicon nitride, silicon carbide, silicon oxynitride or other suitable materials, and may be formed by a Plasma Enhanced Chemical Vapor Deposition (PECVD) or other conventional CVD methods.

In an example embodiment, the polymer layer is formed of a polymer, such as epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole, and the like. In some embodiments, the polymer layer is a polyimide layer. In some other embodiments, the polymer layer is a polybenzoxazole layer.

In an example embodiment, an Under Bump Metallurgy (UBM) 250 is further disposed between the Bump 260 and the conductive layer 220, and the Under Bump metallurgy 250 may be made of titanium, tantalum, chromium, titanium tungsten, or other similar materials. In an exemplary embodiment, the under bump metallurgy 250 has a U-shaped cross section to completely cover the sidewalls of the bump 260. Through such design, can effectively reduce the not infiltration problem that arouses because the tin volume that creeps the tin is not enough to cause to and because the solder bridge problem that arouses of the too much tin volume. In an exemplary embodiment, the solder layer 290 is connected to the ubm layer 250 to form a closed cavity, and the bump 260 is enclosed in the closed cavity.

The utility model also provides a semiconductor structure manufacturing method. In an example embodiment, a semiconductor structure may be formed by the method of fig. 4, wherein the method includes some operations, descriptions and illustrations that should not be construed as limiting the order of the operations.

In step 310, a semiconductor substrate 210 is provided, the semiconductor substrate 210 having predetermined functional circuitry. In an embodiment of the present invention, the semiconductor substrate 210 includes a plurality of conductive lines and a plurality of electronic components, such as transistors and diodes (not shown), connected by the plurality of conductive lines. In an embodiment of the present invention, the semiconductor substrate 210 is a wafer, and the semiconductor substrate 210 comprises semiconductor materials, such as silicon, germanium, gallium, arsenic, and combinations thereof, and other semiconductor materials including group III, group IV, and group V elements may be used. In embodiments of the present invention, the semiconductor substrate 210 is a quadrilateral, a rectangle, a square, a polygon, or any other suitable shape. In an embodiment of the present invention, the semiconductor substrate 210 has a similar structure and function as any of the above descriptions.

In an example embodiment, the semiconductor substrate 210 may further include an interlayer dielectric layer and a metallization structure overlying the integrated circuit. The interlevel dielectric layer in the metallization structure may comprise a low-k dielectric material, Undoped Silicate Glass (USG), silicon nitride, silicon oxynitride, or other commonly used materials. The low-k dielectric material may have a dielectric constant (k value) of less than about 3.9, or less than about 2.8. The metal lines in the metallization structure may be formed of copper or a copper alloy. Those skilled in the art will recognize the detailed structure of the metallization layers and will not be described in detail herein.

In step 320, a conductive layer 220 is disposed on the semiconductor substrate 210. In an exemplary embodiment, the conductive layer 220 is disposed on a front surface (or active surface) of the semiconductor substrate 210, wherein a circuit or an electronic component, etc., is disposed on the front surface (or active surface). In an example embodiment, the conductive layer 220 is electrically connected to a circuit or an electronic element in the semiconductor substrate 210. In an example embodiment, the conductive layer 220 is electrically connected to a circuit outside the semiconductor substrate 210, and thus the circuit in the semiconductor substrate 210 may be electrically connected to the circuit outside the semiconductor substrate 210 through the conductive layer 220. In an example embodiment, the conductive layer 220 is configured to receive a conductive structure. In an example embodiment, the conductive layer 220 may include, but is not limited to, gold, silver, copper, nickel, tungsten, aluminum, palladium, and/or alloys thereof.

In an example embodiment, the conductive layer 220 may be formed by electrochemical plating, electroless plating, sputtering, Chemical Vapor Deposition (CVD), or the like. If a conductive layer 220 of copper is deposited using an electroplating process, a copper seed layer (not shown) may be used to increase the copper plating rate and quality. In some embodiments, the copper seed layer is formed by a sputter deposition or CVD process. In an embodiment of the present invention, the conductive layer 220 has a similar structure or function as any of the above descriptions.

In an exemplary embodiment, the protection layer 230 is disposed on the semiconductor substrate 210 and exposes an exposed region of the conductive layer 220. In an exemplary embodiment, the protection layer 230 is formed with a dielectric material, such as silicon oxide, silicon oxynitride, silicon nitride, or the like. In the embodiment of the present disclosure, the protection layer 230 is configured by Chemical Vapor Deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), spin coating, or any other suitable process. In embodiments of the present disclosure, the protective layer 230 has a similar structure or function as any of the above descriptions.

In an example embodiment, a first mask layer 240 is disposed on the protection layer 230, the first mask layer 240 has a first opening 241, and the first opening 241 corresponds to a portion of the conductive layer 220, so that the portion of the conductive layer 220 is exposed to the first mask layer 240 through the first opening 241.

In step 330, a bump 260 is disposed on the conductive layer 220.

In an example embodiment, an under bump metallurgy 250 is disposed on the first mask layer 240. In one embodiment, as shown in fig. 5, since the first mask layer 240 has the first opening 241, the under bump metallurgy 250 forms a recessed area at the first opening 241 of the first mask layer 240.

In an exemplary embodiment, the under bump metallurgy 250 has a U-shaped cross section to completely cover the sidewalls of the bump 260. Through such design, can effectively reduce the not infiltration problem that arouses because the tin volume that creeps the tin is not enough to cause to and because the solder bridge problem that arouses of the too much tin volume. In an exemplary embodiment, the solder layer 290 is connected to the ubm layer 250 to form a closed cavity, and the bump 260 is enclosed in the closed cavity.

In step 340, an intermetallic compound 291 is formed on the bump 260, wherein the intermetallic compound 291 is uneven.

In an exemplary embodiment, an intermetallic compound 291 is formed on the bump 260, including: a solder layer 290 is disposed on the bump 260, and the intermetallic compound 291 is formed at the junction of the solder layer 290 and the bump 260.

In an example embodiment, a side of the bump 260 away from the semiconductor substrate 210 is processed into a concave-convex surface. In some embodiments, the profile of the concave-convex surface may be a sawtooth structure, a wave structure, a comb-like structure, or other 3D structures, or a combination thereof.

In an example embodiment, the concave-convex surface of the bump 260 includes a plurality of convex portions 262 and a plurality of concave portions 261 arranged at intervals, the plurality of concave portions 261 in one row or one column form an opening, and the plurality of convex portions 262 in one row or one column form a barrier layer structure. However, the uneven surface of the bump of the present invention is not limited to the structure shown in fig. 2, and in other embodiments, the uneven surface of the bump may be a shape with one side lower and one side higher, or a shape with two sides higher and one middle lower.

During the reflow process after the chip bonding, some bumps 260 are compressed due to thermal deformation of the package substrate, so that the solder of the solder layer 290 overflows, and bridges are formed between adjacent bumps 260, thereby causing functional failure. The utility model discloses a surface design of lug 260 with the joint of solder layer 290 is concave-convex surface, designs for the isolation layer structure through a plurality of concave parts 261 with concave-convex surface and a plurality of convex part 262 to guide the overflow direction of solder layer 290 solder, make its overflow toward the adjacent lug that the distance is the farthest, with can minimize or prevent the solder bridge problem that arouses because the base plate warp.

In an exemplary embodiment, before the solder layer 290 is disposed on the bump 260, the uneven surface of the bump 260 is roughened to make the uneven surface rougher, so as to further increase the contact area between the solder layer 290 and the bump 260, and further to make the intermetallic compound between the bump 260 and the solder layer 290 form a wrinkled surface, which more strongly blocks the crack from extending to the periphery. In some embodiments, the surface roughening treatment may be performed using chemical deposition or other suitable processes. In some embodiments, the surface roughness is greater than 0.2, resulting in greater crack resistance of the intermetallic compound.

In an example embodiment, the bump 260 may be formed by sputtering, printing, electroplating, electroless plating, or Chemical Vapor Deposition (CVD). In an exemplary embodiment, the cross-section of the bump 260 may be circular, rectangular, quadrangular, or polygonal.

In an exemplary embodiment, as shown in fig. 6, a second mask layer 270 is disposed on the bump 260, the second mask layer 270 having a plurality of second openings 271, the plurality of second openings 271 corresponding to the bump 260.

In an example embodiment, as shown in fig. 7, portions of the bump 260 corresponding to the plurality of first openings 241 are removed, forming a concave-convex surface of the bump 260. In some embodiments, a portion of bump 260 is removed, for example, using a wet etch technique.

In an example embodiment, as shown in fig. 8, the second mask layer 270 is removed. In some embodiments, for example, by an etching process.

In an exemplary embodiment, as shown in fig. 9, a photoresist layer 280 is disposed on the exposed portion of the ubm layer 250, and a solder layer 290 is disposed on the upper surface of the bump 260. In some embodiments, the photoresist layer 280 is disposed by deposition or other suitable process, and the solder layer 290 is disposed by electroplating or other suitable process.

In an exemplary embodiment, as shown in fig. 10, the photoresist layer 280, the exposed portion of the under bump metal layer 250, and the first mask layer 240 are removed. In some embodiments, the photoresist layer 280 may be removed by photolithography, etching, or other suitable processes.

In an exemplary embodiment, after removing the first mask layer 240, a reflow process is performed to form an intermetallic compound 291, since the surface of the bump 260 bonded to the solder layer 290 is a concave-convex surface.

To sum up, the utility model provides a semiconductor structure and manufacturing method's advantage and beneficial effect lie in:

It is noted herein that the semiconductor structure and the method of fabricating the same shown in the drawings and described in the present specification is only one example of the application of the principles of the present invention. It should be clearly understood by those skilled in the art that the principles of the present invention are not limited to any of the details or any of the components of the apparatus shown in the drawings or described in the specification.

It is to be understood that the invention is not limited in its application to the details of construction and the arrangement of components set forth in the description. The present invention is capable of other embodiments and of being practiced and carried out in a variety of ways. The foregoing variations and modifications fall within the scope of the present invention. It will be understood that the invention disclosed and defined in this specification extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute various alternative aspects of the present invention. The embodiments set forth herein explain the best modes known for practicing the invention and will enable others skilled in the art to utilize the invention.

Claims

1. A semiconductor structure, comprising:

a semiconductor substrate;

a conductive layer disposed on the semiconductor substrate;

the bump is arranged on the conductive layer; and

and the intermetallic compound is arranged on the bump and is concave-convex.

2. The semiconductor structure of claim 1, wherein a side of the bump remote from the semiconductor substrate has a concave-convex surface.

3. The semiconductor structure of claim 2, wherein the bumpy surface is a bumpy rough surface.

4. The semiconductor structure of claim 3, wherein the rugged rough surface has a surface roughness greater than 0.2.

5. The semiconductor structure of claim 1, further comprising a solder layer disposed on the intermetallic compound.

6. The semiconductor structure of claim 5, wherein the solder layer has a concave-convex surface that mates with the intermetallic compound.

7. The semiconductor structure of claim 1, wherein the intermetallic compound has a comb-like structure in cross section.

8. The semiconductor structure of claim 1, further comprising an under bump metallurgy layer disposed between the bump and the conductive layer.

9. The semiconductor structure of claim 8, wherein the under bump metallurgy layer encapsulates sidewalls of the bump.

10. The semiconductor structure of claim 9, further comprising a solder layer disposed on the intermetallic compound; the solder layer is connected with the under bump metal layer and defines a closed cavity, and the bump is closed in the closed cavity.