CN112530819A - Metal bump and manufacturing method thereof - Google Patents
Metal bump and manufacturing method thereof Download PDFInfo
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- CN112530819A CN112530819A CN202110186640.6A CN202110186640A CN112530819A CN 112530819 A CN112530819 A CN 112530819A CN 202110186640 A CN202110186640 A CN 202110186640A CN 112530819 A CN112530819 A CN 112530819A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/116—Manufacturing methods by patterning a pre-deposited material
- H01L2224/1162—Manufacturing methods by patterning a pre-deposited material using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/116—Manufacturing methods by patterning a pre-deposited material
- H01L2224/1162—Manufacturing methods by patterning a pre-deposited material using masks
- H01L2224/11622—Photolithography
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a metal bump and a manufacturing method thereof, wherein the inner wall of a metal plating window is modified into a ladder shape from the prior linear shape, so that the bottom opening of the metal plating window is larger than the top opening of a contact window of a passivation layer and smaller than the top opening of the metal plating window, after a first solder layer, a metal barrier layer and a second solder layer are sequentially plated in the metal plating window, the outer edge of the top of the first solder layer is shorter than the outer edge of the top of the metal barrier layer in the circumferential direction by utilizing the limiting action of the ladder-shaped inner wall, namely, the first solder layer forms an undercut structure relative to the metal barrier layer, thereby ensuring that the second solder layer can not contact the first solder layer in the subsequent process, and avoiding the problem that the metal in the first solder layer and the second solder layer in the metal bump generates unnecessary eutectic reaction, the performance of the metal bump is improved, and the risk of failure of the device due to poor performance of the metal bump is reduced.
Description
Technical Field
The invention relates to the technical field of integrated circuit packaging, in particular to a metal bump and a manufacturing method thereof.
Background
With the development of the integrated circuit packaging technology, the packaging technology based on metal bumps (Bump) is more beneficial to the development of multiple functions, miniaturization, low power consumption and the like of the device than the traditional packaging technologies based on the mounting and inserting of pins, wire bonding and the like. Especially, Micro Electro Mechanical Systems (MEMS) devices such as sensing devices and radio frequency devices have better process adaptability and thermoelectric performance when packaged by using a metal bump Packaging process, and further, each functional unit in the MEMS device can be further stacked and evolved from two-dimensional layout to three-dimensional stacking by using Wafer Level Packaging (WLP) technologies such as Wafer bonding, metal bumps, thinning, and the like, so that the functional diversity of the device can be further enhanced while the size of the device is reduced. Therefore, the metal bump process is one of the key processes affecting the final performance of the device.
Referring to fig. 1, a specific process for fabricating a metal bump in the prior art includes: providing a package substrate 100 having conductive members (also referred to as electrical contacts) 101 such as Redistribution Layer (RDL) structures, metal interconnection structures, or contact pads, wherein the Redistribution structures are used for leading out original electrical contacts such as contact pads of the package or metal interconnection structures, so that new electrical contacts can be manufactured at a larger pitch; then, a series of processes including deposition of a passivation layer 102, photolithography and etching are performed on the package substrate 100, so that a plurality of openings 102a (i.e., regions for forming metal bumps) capable of exposing a portion of the surface of the conductive member 101 are formed in the passivation layer 102; next, an Under Bump Metallurgy 103 (UBM), such as Ti, Cu, or a Ti-Cu-TiCu alloy, is formed on the passivation layer 102 and the surface of the opening 102a by a sputtering deposition process, and a photoresist layer (not shown) having a metal plating window (not shown) is further formed on the Under Bump Metallurgy 103 by operations of photoresist coating, exposure, and development; then, continuously electroplating a Cu layer 104a, a nickel Ni layer 104b, and a solder layer 104c (for example, tin-silver-AgSn alloy or tin Sn) in the metal plating window, and further removing the photoresist layer to form a metal bump 104; then, the excess under bump metallurgy 103 is removed by wet etching.
In the above process of fabricating the metal bump 104, when the excess under-bump metal layer 103 is removed by the wet method, Ni has a faster etching rate than Cu in the etching solution, so that there is a loss at the edge of the Ni layer 104 b. During the operation of the device, a current and a voltage are applied to the metal bump 104, so that joule heat is generated on the metal bump 104, which may cause the solder layer 104c to melt, and the solder layer 104c and the Cu layer 104a may not be well separated by the nickel Ni layer 104b due to the damage of the nickel Ni layer 104b at the edge 105 of the metal bump 104, and the solder layer 104c may contact the Cu layer 104a after melting and cause a CuSn eutectic problem, thereby causing the metal bump 104 to fail, and finally causing the device to fail.
In addition, the eutectic failure problem is not only in the metal bump 104 formed by the electroplating process, but also in other metal bumps formed by the chemical plating, evaporation, and other processes, as long as the top solder layer and the bottom solder layer at the edge of the metal bumps are not well separated by the intermediate metal barrier layer, and the metal of the top solder layer and the metal of the bottom solder layer are easily eutectic, the eutectic failure problem is easily generated in the metal bumps during the operation of the device.
Disclosure of Invention
The invention aims to provide a metal bump and a manufacturing method thereof, which can prevent unnecessary eutectic problem in the metal bump so as to improve the performance of the metal bump and reduce the eutectic failure probability of the metal bump.
In order to solve the above technical problem, the present invention provides a method for manufacturing a metal bump, comprising:
providing a substrate with a conductive member, and forming a passivation layer on the surface of the substrate, wherein the passivation layer is provided with a contact window exposing at least part of the surface of the conductive member;
covering an under bump metal layer at least on the surface of the contact window;
forming a patterned mask layer on the under bump metal layer, wherein the patterned mask layer is provided with a metal plating window which is aligned with and communicated with the contact window, and the bottom opening of the metal plating window is larger than the top opening of the contact window and smaller than the top opening of the metal plating window, so that the metal plating window and the inner wall of the contact window form a step-shaped inner wall;
sequentially plating a first solder layer, a metal barrier layer and a second solder layer in the metal plating window and the contact window, wherein the outer edge of the top of the first solder layer is shorter than the outer edge of the top of the metal barrier layer in the circumferential direction due to the stepped inner wall, and the second solder layer contains metal capable of performing eutectic reaction with the metal in the first solder layer;
and removing the patterned mask layer to form a metal bump.
The invention also provides a metal bump which is formed by adopting the manufacturing method of the metal bump, the metal bump is electrically connected with the corresponding conductive piece through the metal layer under the bump, and the metal bump comprises a first solder layer, a metal barrier layer and a second solder layer which are sequentially stacked; the second solder layer contains metal which can perform eutectic reaction with the metal in the first solder layer; the top outer edges of the first solder layers are each circumferentially shorter than the top outer edges of the metallic barrier layers.
Compared with the prior art, the technical scheme provided by the invention has at least one of the following beneficial effects:
1. the inner wall of the metal plating window in the mask layer is modified into a ladder shape from the existing linear shape, so that the bottom opening of the metal plating window is larger than the top opening of the contact window of the passivation layer and smaller than the top opening of the metal plating window, after the first solder layer, the metal barrier layer and the second solder layer are sequentially plated in the metal plating window, the top outer edge of the first solder layer is enabled to be shorter than the top outer edge of the metal barrier layer in the circumferential direction by utilizing the limiting action of the ladder-shaped inner wall, namely, the first solder layer forms an undercut (undercut) structure relative to the metal barrier layer, therefore, the second solder layer can be ensured not to contact with the first solder layer in the subsequent process, the problem that the metal in the first solder layer and the second solder layer in the metal bump generates unnecessary eutectic reaction is avoided, and the performance of the metal bump is improved, the risk of failure of the device due to eutectic problems of the metal bumps is reduced.
2. The metal plating window with the step-shaped inner wall is formed by two times of photoresist photoetching, and the process is simple.
Drawings
Fig. 1 is a schematic cross-sectional view of a conventional metal bump.
Fig. 2 is a flowchart of a method for manufacturing a metal bump according to an embodiment of the invention.
Fig. 3 to 7 are schematic cross-sectional views of device structures in a method for manufacturing a metal bump according to an embodiment of the invention.
Fig. 8 to 10 are schematic cross-sectional views of device structures in a process of applying the method for manufacturing a metal bump to a MEMS device according to an embodiment of the present invention.
Detailed Description
The technical solution proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 2, the present invention provides a method for manufacturing a metal bump, including the following steps:
s1, providing a substrate with a conductive piece, and forming a passivation layer on the surface of the substrate, wherein the passivation layer is provided with a contact window exposing at least part of the surface of the conductive piece;
s2, at least covering the surface of the contact window with an under bump metal layer;
s3, forming a patterned mask layer on the under bump metal layer, wherein the patterned mask layer is provided with a metal plating window aligned with and communicated with the contact window, and the bottom opening of the metal plating window is larger than the top opening of the contact window and smaller than the top opening of the metal plating window, so that the inner walls of the metal plating window and the contact window form a step-shaped inner wall;
s4, sequentially plating a first solder layer, a metal barrier layer and a second solder layer in the metal plating window and the contact window, wherein the outer edge of the top of the first solder layer is shorter than the outer edge of the top of the metal barrier layer in the circumferential direction due to the stepped inner wall, and the second solder layer contains metal capable of performing eutectic reaction with the metal in the first solder layer;
and S5, removing the patterned mask layer to form a metal bump.
In step S1, referring to fig. 3, a substrate having a conductive member 201 is provided, wherein the substrate may be a semiconductor substrate or wafer processed by front end of line (FEOL) and partial back end of line processes such as growth of all gate oxide layers, polysilicon deposition, photolithography, polysilicon etching, ion implantation and thermal treatment in integrated circuit manufacturing. Active elements (not shown) such as diodes and MOS transistors may be formed, passive devices (not shown) such as capacitors, resistors and inductors may be formed, and device isolation structures such as Shallow Trench Isolation (STI) structures and local oxidation of silicon (LOCOS) isolation structures may be formed. The front-end process comprises the processes of growth of a grid oxide layer, polycrystalline silicon deposition, photoetching technology, polycrystalline silicon etching, various ion injection, heat treatment and the like, and the back-end process comprises the processes of interlayer dielectric layer deposition, contact hole etching, metal interconnection and the like.
The substrate of the present embodiment includes a connection layer 200 and a conductive member 201 formed on the connection layer 200, wherein the connection layer 200 may be any suitable semiconductor substrate known to those skilled in the art, such as silicon, silicon-on-insulator, etc., or may be an interlayer dielectric layer, etc., and the interlayer dielectric layer includes at least one suitable material such as silicon nitride, silicon oxynitride, low-k dielectric material, oxide such as silicon oxide, Undoped Silicate Glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc., wherein the dielectric constant k of the low-k dielectric material may be less than 2.5.
The conductive member 201 may include at least one of the following conductive structures: metal interconnection lines formed by a back-end-of-line metal interconnection process (e.g., a damascene process); a rewiring layer formed by a Rewiring (RDL) process; a metal pad formed by a pad process; a conductive plug formed by a through-silicon-via process; and a conductive plug formed by a contact plug process other than a through-silicon-via process. The material includes at least one of copper, copper alloy, tungsten, silver, gold, aluminum and other metals.
The conductive member 201 may have a single-layer structure or a stacked structure of multiple layers. As an example, the conductive member 201 includes a metal adhesion layer 201a at a bottom layer and a metal conductive layer 201b at a top layer. As an example, the material of the metal adhesion layer 201a includes at least one of titanium Ti, nickel Ni, chromium Cr, tantalum Ta, titanium nitride TiN, tantalum nitride TaN, and the like; the material of the metal conductive layer 201b includes at least one of copper Cu, aluminum Al, tungsten W, and the like.
With continued reference to fig. 3, in step S1, a passivation layer 202 is covered on the connection layer 200 and the conductive member 201 by any suitable process such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), or spin coating, and the passivation layer 202 is subjected to photolithography and etching to remove the excess passivation layer and form a contact window 202a exposing at least a portion of the upper surface of the conductive member 201. Among others, the material of the passivation layer 202 may include at least one of a photo-patternable dielectric material of Polybenzoxazole (PBO), Polyimide (PI), benzocyclobutene (BCB), etc., or may further include at least one of a non-photo-patternable dielectric material such as silicon nitride, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.
With continued reference to fig. 3, in step S2, the passivation layer 202 and the surface of the contact window 202a may be covered with the under bump metal layer 203 by using CVD, PVD, ALD, electroplating, electroless plating, and the like. The under bump metallurgy 203 may be a single-layer structure or a stacked structure of multiple layers. The material may include at least one of titanium (Ti), titanium nitride (TiN), titanium oxide (TiOx), tantalum (Ta), tantalum nitride (TaN), tungsten, copper, and gold. The under bump metallurgy 203 can make the conductive device 201 adhere to the metal bump 7 formed subsequently better, and prevent the metal in the metal bump from diffusing downward to the periphery, thereby preventing the problem that the connection interface between the metal bump formed subsequently and the conductive device 201 is weak, which may lead to the fracture or peeling of the metal bump.
In this embodiment, the overall film thickness of the under bump metallurgy 203 is such that it can form a recess along with the recess of the contact window 202 a.
Referring to fig. 4 and 5, in step S3, a patterned mask layer is formed on the under bump metallurgy layer 203, where the patterned mask layer has a metal plating window aligned with and connected to the contact window 202a, and a bottom opening of the metal plating window is larger than a top opening of the contact window 202a and smaller than a top opening of the metal plating window, so that inner walls of the metal plating window and the contact window 202a form a stepped inner wall.
As an example, referring to fig. 4 and 5, in step S3, first, a first mask layer 204 is formed on the under bump metallurgy 203 by photoresist coating, and the first mask layer 204 is subjected to photolithography by exposure, development, and other photolithography processes to form a first window 204a aligned with and communicated with the contact window 202a in the first mask layer 204, a stacking thickness of the first mask layer 204 on the under bump metallurgy 203 at the periphery of the contact window 202a is H1, that is, a depth of the first window 204a is H1, a sidewall of the first window 204a may be a vertical sidewall perpendicular to an upper surface of the substrate, or an inclined sidewall having an included angle different from 90 degrees with the upper surface of the substrate, and a width D2 of a bottom opening of the first window 204a is greater than a width D1 of a top opening of the contact window 202 a; secondly, forming a second mask layer 205 on the first mask layer 204 and the first window 204a by photoresist coating, and photoetching the second mask layer 205 by photolithography processes such as exposure, development and the like, forming a second window 205a aligned and communicated with the first window 204a in the second mask layer 205, wherein the stacking thickness of the second mask layer 205 on the first mask layer 204 is H2, that is, the depth of the second window 205a is H2, wherein H2 may be greater than H1, or less than or equal to H1, the side wall of the second window 205a may be a vertical side wall perpendicular to the upper surface of the substrate, or an inclined side wall having an included angle with the upper surface of the substrate not being 90 degrees, the width D3 of the bottom opening of the second window 205a is greater than the width D2 of the top opening of the first window 204a, and the second window 205a and the first window 204a are combined to form a desired metal-plated window (unmarked window) having a step-type inner wall, wherein, the inner walls of the first window 204a and the contact window 202a constitute a first step of the stepped inner wall, and the inner walls of the first window 204a and the second window 205a constitute a second step of the stepped inner wall. That is, in this example, the patterned mask layer is a photoresist.
In the example, the required metal plating window is formed through photoetching processes such as photoresist coating, exposure, development and the like twice, the photoresist is relatively well removed, the process is simple, the cost can be reduced, the influence of the forming and removing processes of the photoresist on other structures is small, and the reliability of the device is favorably ensured.
It should be noted that the process of forming the desired metal-plated window in the present invention is not limited to the above example, and a person skilled in the art may form a patterned mask layer of the metal-plated window with a stepped inner wall on the under bump metal layer 203 by using any suitable process.
For example, in other embodiments of the present invention, a mask layer with a thickness equal to the sum of the thicknesses of the first mask layer 204 and the second mask layer 205 is coated, and then the surface layer of the mask layer is exposed by controlling the exposure parameters to define an exposure region and an exposure depth corresponding to the second window 205 a; and then adjusting the exposure parameters again, carrying out second exposure on the mask layer to define an exposure area and an exposure depth corresponding to the first window 204a, and then carrying out development to remove the exposed photoresist and form a required metal plating window.
For another example, in other embodiments of the present invention, a vapor deposition process is first performed to cover a first mask layer 204, which may be a single-layer structure or a structure formed by stacking multiple layers of films, on the surface of the under bump metal layer 203, where the material of the first mask layer includes at least one of silicon oxide, silicon nitride, and silicon oxynitride, and then a series of photolithography processes such as photoresist coating, exposure, and development are performed on the first mask layer to form a patterned first photoresist layer (not shown); then, the patterned first photoresist layer is used as a mask, and the first mask layer 204 is etched to form a first window 204a in the first mask layer 204; then, removing the first photoresist layer, covering the first mask layer 204 with the second mask layer 205 by using a vapor deposition process again, and performing a series of photoresist processes such as photoresist coating, exposure, development and the like to form a patterned second photoresist layer (not shown); then, the patterned second photoresist layer is used as a mask to etch the second mask layer 205, so as to form a second window 205a in the second mask layer 205; and removing the patterned second photoresist layer to form the required metal plating window. This example is relatively costly, but may utilize the mechanical properties of silicon oxide, silicon nitride, silicon oxynitride, etc. to form deeper metallization windows than those achieved using photoresist alone (e.g., to form metallization windows, which may meet some device fabrication requirements for metal bumps with higher height requirements.referring to FIGS. 5 and 6, in step S4, a first solder layer 206a, a metal barrier layer 206b, and a second solder layer 206c may be sequentially deposited in the metallization windows by any suitable method, such as evaporation, electroplating, electroless plating, sputtering, etc. to form metal bumps 206. in step S4, the second solder layer 206c may contain a metal that can react with the metal in the first solder layer 206a in a eutectic manner The electrical connection between the first solder layer 206a and the second solder layer 206c can also prevent the first solder layer 206a and the second solder layer 206c from diffusing with each other in the subsequent process to generate eutectic reaction, thereby greatly improving the reliability of the metal bump 206.
As an example, the material of the first solder layer 206a is copper or copper alloy; the material of the metal barrier layer 206b includes at least one of platinum, palladium and nickel; the material of the second solder layer 206c is tin or tin alloy.
As an example, the depth of the recess formed after the under bump metallurgy 203 covers the contact window 202a is H0, the depth of the first window 204a is H1, and the depth of the second window 205a is H2. The first solder layer 206a has a film thickness H0 in the contact window 202a and a film thickness H1 in the first window 204 a. The thickness of the metal barrier layer 206b in the first window 204a is greater than H1, but the thickness of the film on the first mask layer 204 in the second window 205a is less than H2. The film thickness of the second solder layer 206c is less than H2.
As an example, referring to fig. 5 and 6, in step S4, the step of sequentially plating the first solder layer 206a, the metal barrier layer 206b, and the second solder layer 206c in the metal plating window and the contact window 202a includes: after forming the second window 205a, first, plating a first solder layer 206a in the first window 204a and the contact window 202a by electroplating or chemical plating, and the like, and the plated first solder layer 206a may fill the contact window 202a but not fill the first window 204a, or even may not fill the contact window 202a but extend upward from the inner side wall of the contact window 202a to at least cover a part of the inner side wall of the first window 204a, i.e. the first solder layer 206a does not exceed the top surface of the first mask layer 204 in the first window 204 a; then, sequentially plating a metal barrier layer 206b and a second solder layer 206c in the first window 204a and the second window 205a by electroplating or electroless plating, and the metal barrier layer 206b may fill the contact window 202a and the first window 204a but not fill the second window 205a, or even may not fill the contact window 202a and the first window 204a but extend upward from the inner sidewall of the contact window 202a to at least partially cover the inner sidewall of the second window 205a, so as to cover the top corner of the first mask layer 204 exposed by the second mask layer 205 in the second window 205 a; the second solder layer 206c may or may not fill the second window 205 a.
The contact window 202a, the first window 204a and the second window 205a have stepped inner walls formed by increasing the size of the opening, so that after the electroplating is completed, the bottom edge of the second solder layer 206c is aligned with the top edge of the metal barrier layer 206b, and the bottom edge of the first solder layer 206a is shorter than the bottom edge of the metal barrier layer 206b along the circumferential direction, thereby forming an undercut structure of the metal bump 206.
In the technical solution of the present invention, the steps of sequentially plating the first solder layer, the metal barrier layer, and the second solder layer in the metallization window and the contact window are not limited to the above examples, and a person skilled in the art may use any other suitable process to sequentially plate the first solder layer, the metal barrier layer, and the second solder layer. For example, in another embodiment of the present invention, please refer to fig. 4 to 6, after the first window 204a is formed and before the second mask layer 205 is formed, the first solder layer 206a is plated in the first window 204a and the contact window 202a, and the plated first solder layer 206a does not exceed the top surface of the first mask layer 204 in the first window 204 a; after the second window 205a is formed, a metal barrier layer 206b and a second solder layer 206c are sequentially plated, and the metal barrier layer 206b covers the top of the first mask layer 204 exposed by the second mask layer 205 in the second window 205 a. That is, the embodiment performs the above-described step S3 and step S4 in combination with each other, and performs a part of the process in step S3 and a part of the process in step S4 in this order, and performs the remaining process in step S3 and the remaining process in step S4 in this order.
Referring to fig. 7, in step S5, the first mask layer 204 and the second mask layer 205 may be removed by a suitable photoresist stripping process such as dry photoresist stripping, wet photoresist stripping, etc. to expose the under bump metallurgy layer 203 at the periphery of the metal bump 206.
After step S5, the method of the present embodiment further includes step S6: with the metal bump 206 as a mask, the under bump metallurgy layer 203 exposed on the periphery of the metal bump 206 can be removed by a wet etching process. At this time, the metal bump 206 has a flat-top pillar structure as a whole.
When the metal bump 206 is required to be in a ball shape, the metal bump 206 may be reflowed after the first mask layer 204 and the second mask layer 205 are removed and before or after the under bump metal layer 203 exposed on the periphery of the metal bump 206 is removed by a wet process, that is, after the step S5 and before or after the step S6, and the second solder layer 206c becomes a ball 206 c' under the action of the reflow.
As can be seen from fig. 7, the protrusion height of the metal bump 206 is mainly determined by the thicknesses of the first solder layer 206a and the second solder layer 206c, i.e. by the thicknesses of the first mask layer 204 and the second mask layer 205, and those skilled in the art can make reasonable settings according to the height requirement of the device for the metal bump.
It should be noted that, in the above embodiment, before the patterned mask layer is formed on the under bump metal layer 203, the under bump metal layer 203 covers not only the inner surface of the contact window 202a, but also the surface of the passivation layer 202 at the periphery thereof and the surface of the connection layer 200 exposed by the passivation layer 202, which is advantageous for forming the metal bump 206 by an electroplating process. However, the technical solution of the present invention is not limited thereto, and in other embodiments of the present invention, when the film layers of the metal bump 206 are formed by processes such as chemical plating, evaporation, or sputtering deposition, in step S2, the under bump metallurgy layer 203 may further cover the inner surface of the contact window 202a, and the under bump metallurgy layer 203 may expose at least a portion of the surface of the passivation layer 202 at the periphery of the contact window 202 a.
Referring to fig. 7, an embodiment of the invention further provides a metal bump 206 formed by the above-mentioned method for manufacturing a metal bump, wherein the metal bump 206 is electrically connected to the corresponding conductive member 201 through the under bump metal layer 203, and the metal bump 206 includes a first solder layer 206a, a metal barrier layer 206b and a second solder layer 206c stacked in sequence; the second solder layer 206c contains a metal capable of eutectic reaction with the metal in the first solder layer 206 a; the top outer edges of the first solder layers 206a are each circumferentially shorter than the top outer edges of the metallic barrier layers 206 b.
The material and structure of each film layer of the metal bump 206 of this embodiment can be referred to the above description, and are not repeated herein.
In summary, according to the metal bump and the manufacturing method thereof of the present invention, the inner wall of the metallization window in the mask layer is modified from the existing linear type to the step type, so that the bottom opening of the metallization window is larger than the top opening of the contact window of the passivation layer and smaller than the top opening of the metallization window, and thus after the first solder layer, the metal barrier layer and the second solder layer are sequentially plated in the metallization window, the outer edge of the top of the first solder layer is circumferentially shorter than the outer edge of the top of the metal barrier layer by using the limiting effect of the step type inner wall, that is, the first solder layer forms an undercut (undercut) structure with respect to the metal barrier layer, thereby ensuring that the second solder layer cannot contact the first solder layer in the subsequent process, and avoiding the problem of unnecessary eutectic reaction between the metals in the first solder layer and the second solder layer in the metal bump, the performance of the metal bump is improved, and the risk of failure of the device due to poor performance of the metal bump is reduced. Furthermore, the metal plating window with the step-shaped inner wall can be formed by two times of photoresist photoetching respectively, and the process is simple.
The metal bump and the manufacturing method thereof can be applied to manufacturing MEMS devices such as bulk filters. The following describes in detail the manufacturing process of the MEMS device by applying the method for manufacturing metal bumps according to the present invention with reference to fig. 2 to 10.
Referring to fig. 8 to 10, the bulk acoustic filter generally includes a substrate (not shown), on which a plurality of bulk acoustic resonators (not shown) and pads (not shown) are disposed, each of the bulk acoustic resonators includes an electrode layer 207 and an electrode connection layer (i.e., a conductive member 201) disposed on the substrate, the electrode layer includes a bottom electrode, a piezoelectric layer, and a top electrode sequentially formed on the substrate, and the electrode connection layer (i.e., the conductive member 201) is formed by a rewiring process for electrically connecting the bulk acoustic resonators and the pads.
Therefore, in step S1, referring to fig. 8, a substrate MEMS device substrate is provided, in which the connection layer 200 is a silicon cover plate, a Through Silicon Via (TSV) is performed on the connection layer 200 to form a through silicon via 200a exposing the underlying electrode layer 207, and a redistribution layer (RDL) process is further performed to form an electrode connection layer electrically connected to the electrode layer 207 on the surface of the through silicon via 200a and on a portion of the upper surface of the connection layer 200, i.e., a conductive member 201 is formed, and the conductive member 201 covers the inner surface of the through silicon via 200a and extends from the inner surface of the through silicon via 200a to the surface of the connection layer 200 at the periphery of the through silicon via 200 a.
When the passivation layer 202 having the contact window 202a is formed, the passivation layer 202 is also opened at the through silicon via 200a to expose a portion of the conductive member 201 covering the sidewall and bottom surface of the through silicon via 200 a. That is, the contact window 202a is formed at the periphery of the through-silicon via 200a, and the passivation layer 202 is opened not only at the contact window 202a but also at the through-silicon via 200 a. The purpose of exposing the through silicon via 200a through the passivation layer 202 is to release internal pressure generated in the bulk acoustic wave filter by using the through silicon via 200a, so as to avoid problems such as bubbling of an electrode layer caused by a subsequent process. After the first mask layer 204 and the second mask layer 205 are removed in step S5, the through silicon via 200a is exposed again, and the under bump metallurgy 203 on the inner surface of the through silicon via 200a is also removed in step S6.
It should be noted that when the method for manufacturing metal bumps according to the present invention is applied to the manufacture of MEMS devices other than bulk filters, the connection layer 200 may be replaced by an inorganic or organic dielectric material layer.
The metal bump required by the MEMS device is formed by applying the manufacturing method of the metal bump, so that the performance of the packaged MEMS device can be improved.
It should be noted that, in the technical solution of the present invention, the difference between the widths of the first solder layer 206a and the metal barrier layer 206b at the edge of the metal bump 206 needs to be set according to the design requirements and the working environment of a specific device, and it is within the protection scope of the technical solution of the present invention as long as the metal bump has sufficient mechanical properties and eutectic problem is not easy to occur during working.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art according to the above disclosure are within the scope of the present invention.
Claims (10)
1. A method for manufacturing a metal bump is characterized by comprising the following steps:
providing a substrate with a conductive member, and forming a passivation layer on the surface of the substrate, wherein the passivation layer is provided with a contact window exposing at least part of the surface of the conductive member;
covering an under bump metal layer at least on the surface of the contact window;
forming a patterned mask layer on the under bump metal layer, wherein the patterned mask layer is provided with a metal plating window which is aligned with and communicated with the contact window, and the bottom opening of the metal plating window is larger than the top opening of the contact window and smaller than the top opening of the metal plating window, so that the metal plating window and the inner wall of the contact window form a step-shaped inner wall;
sequentially plating a first solder layer, a metal barrier layer and a second solder layer in the metal plating window and the contact window, wherein the outer edge of the top of the first solder layer is shorter than the outer edge of the top of the metal barrier layer in the circumferential direction due to the stepped inner wall, and the second solder layer contains metal capable of performing eutectic reaction with the metal in the first solder layer;
and removing the patterned mask layer to form a metal bump.
2. The method for manufacturing a metal bump according to claim 1, wherein the conductive member comprises at least one of the following conductive structures: a metal interconnection line formed by a metal interconnection process of a back-end process; a rewiring layer formed by a rewiring process; a metal pad formed by a pad process; a conductive plug formed by a through-silicon-via process; and a conductive plug formed by a contact plug process other than a through-silicon-via process.
3. The method of fabricating a metal bump according to claim 1, wherein the step of forming the patterned mask layer having the metallization window on the under bump metal layer comprises:
forming a first mask layer on the under bump metal layer, and photoetching and/or etching the first mask layer to form a first window which is aligned with and communicated with the contact window in the first mask layer, wherein the bottom opening of the first window is larger than the top opening of the contact window;
and forming a second mask layer on the first mask layer and the first window, photoetching and/or etching the second mask layer, forming a second window which is aligned with and communicated with the first window in the second mask layer, wherein the bottom opening of the second window is larger than the top opening of the first window, and the second window and the first window are combined to form the metal-plated window.
4. The method for manufacturing a metal bump according to claim 3, wherein the step of plating a first solder layer, a metal barrier layer, and a second solder layer in this order in the metal plating window and the contact window comprises: after the second window is formed, plating a first solder layer, wherein the plated first solder layer does not exceed the top surface of the first mask layer in the first window; then, sequentially plating a metal barrier layer and a second solder layer, wherein the metal barrier layer covers the top of the first mask layer exposed by the second mask layer in the second window;
or the step of sequentially plating a first solder layer, a metal barrier layer and a second solder layer in the metal plating window and the contact window comprises: after the first window is formed and before the second mask layer is formed, plating the first solder layer in the first window and the contact window, wherein the plated first solder layer does not exceed the top surface of the first mask layer in the first window; and after the second window is formed, sequentially plating a metal barrier layer and a second solder layer, wherein the metal barrier layer covers the top of the first mask layer exposed by the second mask layer in the second window.
5. The method of fabricating a metal bump according to claim 1, wherein the stepped inner wall aligns a bottom edge of the second solder layer with a top edge of the metal barrier layer.
6. The method for manufacturing a metal bump according to claim 1, wherein the under bump metallurgy is a single layer structure or a multi-layer stacked structure, and the material thereof includes: at least one of titanium, titanium nitride, tantalum nitride, tungsten, copper and gold; the patterned mask layer is made of at least one of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and tetraethoxysilane; the first solder layer is made of copper or copper alloy; the material of the metal barrier layer comprises at least one of platinum, palladium and nickel; the material of the second solder layer is tin or tin alloy.
7. The method of fabricating a metal bump according to any one of claims 1 to 6, wherein the under bump metallurgy further covers a surface of the passivation layer at a periphery of the contact window before forming the patterned mask layer; and after the metal bump is formed, removing the under bump metal layer exposed by the metal bump by using the metal bump as a mask through a wet method.
8. The method for manufacturing a metal bump according to claim 7, wherein after the metal bump is formed and before or after the under bump metal layer at the periphery of the metal bump is removed by a wet process, the metal bump is reflowed so that the second solder layer is transformed into a ball shape.
9. The method for manufacturing a metal bump according to claim 7, wherein the substrate is a MEMS device substrate, the substrate further has an electrode layer, a connection layer covering the electrode layer, and a through hole penetrating through the connection layer, the through hole exposes a part of the surface of the electrode layer, and the conductive member covers the inner surface of the through hole and extends from the inner surface of the through hole to the surface of the connection layer at the periphery of the through hole; the contact window is formed at the periphery of the through hole, and the passivation layer is opened not only at the contact window but also at the through hole.
10. A metal bump formed by the method of any one of claims 1 to 9, the metal bump being electrically connected to a corresponding conductive member through an under bump metallurgy (ubm), the metal bump comprising a first solder layer, a metal barrier layer and a second solder layer stacked in this order; the second solder layer contains metal which can perform eutectic reaction with the metal in the first solder layer; the top outer edges of the first solder layers are each circumferentially shorter than the top outer edges of the metallic barrier layers.
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| CN202110186640.6A CN112530819A (en) | 2021-02-18 | 2021-02-18 | Metal bump and manufacturing method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113691233A (en) * | 2021-08-27 | 2021-11-23 | 中国电子科技集团公司第二十六研究所 | High-reliability wafer-level packaged acoustic surface filter structure and preparation method thereof |
| TWI834048B (en) * | 2021-04-29 | 2024-03-01 | 台灣積體電路製造股份有限公司 | Semiconductor structure and method of manufacturing the same |
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| CN100527358C (en) * | 2005-09-06 | 2009-08-12 | 日月光半导体制造股份有限公司 | Projection producing process and its structure |
| CN103681562A (en) * | 2012-09-18 | 2014-03-26 | 台湾积体电路制造股份有限公司 | Ladder bump structures and methods of making same |
| US20200258855A1 (en) * | 2019-02-11 | 2020-08-13 | Infineon Technologies Ag | Semiconductor Device Having a Copper Pillar Interconnect Structure |
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- 2021-02-18 CN CN202110186640.6A patent/CN112530819A/en not_active Withdrawn
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| CN100527358C (en) * | 2005-09-06 | 2009-08-12 | 日月光半导体制造股份有限公司 | Projection producing process and its structure |
| CN103681562A (en) * | 2012-09-18 | 2014-03-26 | 台湾积体电路制造股份有限公司 | Ladder bump structures and methods of making same |
| US20200258855A1 (en) * | 2019-02-11 | 2020-08-13 | Infineon Technologies Ag | Semiconductor Device Having a Copper Pillar Interconnect Structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI834048B (en) * | 2021-04-29 | 2024-03-01 | 台灣積體電路製造股份有限公司 | Semiconductor structure and method of manufacturing the same |
| CN113691233A (en) * | 2021-08-27 | 2021-11-23 | 中国电子科技集团公司第二十六研究所 | High-reliability wafer-level packaged acoustic surface filter structure and preparation method thereof |
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