CN115249678A

CN115249678A - Semiconductor packaging structure and packaging method

Info

Publication number: CN115249678A
Application number: CN202210442819.8A
Authority: CN
Inventors: 许飞
Original assignee: Joulwatt Technology Co Ltd
Current assignee: Joulwatt Technology Co Ltd
Priority date: 2022-04-25
Filing date: 2022-04-25
Publication date: 2022-10-28

Abstract

The invention discloses a semiconductor packaging structure and a packaging method, wherein the packaging structure comprises: a semiconductor chip having a passivation layer at least partially covering a first surface of the semiconductor chip and exposing the pad; the insulating layer is formed on the passivation layer, and an opening is formed in the insulating layer; the metal block is positioned in the opening, and the metal block partially covers the bottom of the opening; and the bump is formed at the opening position and is electrically connected with the bonding pad through the opening and the metal block. According to the invention, the metal block is additionally arranged in the polyimide layer opening below the metal column, so that the height difference of the opening position is made up, and the performance and the service life of the device can be improved.

Description

Semiconductor packaging structure and packaging method

Technical Field

The invention relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging structure and a packaging method.

Background

With the high integration, high performance and high speed of semiconductor chips, the demand for semiconductor packaging technology is increasing, and the miniaturization and mass production is becoming the development trend of semiconductor packages. The conventional electronic packaging technology for bonding a semiconductor chip with other components by wire bonding has failed to meet the current requirements, and a flip chip bonding technology for bonding a chip with other components by using bumps has been developed.

However, as shown in fig. 1, in order to reduce the package stress of the current flip-chip product (such as the semiconductor package 1), a Polyimide (PI) layer 14 is added under the bump 16 (including the copper pillar 161 and the tin cap 162 located above the copper pillar 161), after the bump process, due to the height difference of the opening position of the PI layer 14, the Cu and Sn interface at the top of the bump 16 has a recess, and when the thermal process is performed after the flip-chip process in the later packaging process, void (such as air bubbles) is generated at the Cu and Sn interface and accumulated at the recess position and cannot overflow, thereby affecting the electrical conductivity and reliability of the product.

Therefore, there is a need to provide an improved technical solution to overcome the above technical problems in the prior art.

Disclosure of Invention

In order to solve the above technical problems, the present invention provides a semiconductor package structure and a semiconductor package method, wherein a metal block is additionally disposed in an opening of a polyimide layer, so as to compensate for a height difference of the opening, improve performance of a device, and prolong a service life of the device.

According to a first aspect of the present disclosure, there is provided a semiconductor package structure comprising: the semiconductor chip is provided with a passivation layer, and the passivation layer covers the first surface of the semiconductor chip and exposes the bonding pad;

the insulating layer is formed on the passivation layer and provided with an opening;

the metal block is positioned in the opening, and the metal block partially covers the bottom of the opening;

and the bump is formed at the opening position and is electrically connected with the bonding pad through the opening and the metal block.

Optionally, the bottom of the bump covers the bottom of the opening, the top of the metal block in the opening, and a portion of the insulating layer.

Optionally, the metal block is located in a central region of the bottom of the opening.

Optionally, the bump includes a first metal pillar and a metal cap on top of the first metal pillar.

Optionally, a difference between the thickness of the metal block and the thickness of the insulating layer is smaller than a preset value.

Optionally, the opening is located above the pad location.

Optionally, the method further comprises:

and the redistribution layer is positioned between the bonding pad and the insulating layer, the opening is positioned above the redistribution layer, and the bump is electrically connected with the bonding pad through the opening, the metal block and the redistribution layer.

Optionally, the insulating layer comprises a polyimide layer or a polybenzoxazole layer.

According to a second aspect of the present disclosure, there is provided a semiconductor packaging method including:

providing a semiconductor chip, wherein the semiconductor chip is provided with a passivation layer, and the passivation layer covers the first surface of the semiconductor chip and exposes the bonding pad;

forming an insulating layer with an opening and a metal block which is positioned in the opening and electrically connected with the bonding pad above the passivation layer;

and forming a bump covering the bottom of the opening, the top of the metal block and part of the insulating layer at the opening position, so that the bump is electrically connected with the bonding pad through the opening and the metal block.

Optionally, the method of forming the insulating layer having the opening and the metal block includes:

forming a metal block electrically connected with the bonding pad;

forming an insulating layer covering the passivation layer and the metal block;

and removing the insulating layer part above the metal block and in a certain peripheral area to form the opening so as to expose the metal block.

forming the insulating layer with an opening over the passivation layer;

and forming the metal block in the opening.

Optionally, the metal block is formed in a central region of the bottom of the opening.

Optionally, before forming the insulating layer and the metal block, the method further includes:

and forming a redistribution layer on the passivation layer, wherein the opening is positioned above the redistribution layer, and the bump is electrically connected with the pad through the opening, the metal block and the redistribution layer.

The beneficial effects of the invention at least comprise:

in the embodiment of the invention, before the bump is formed, the metal block with the preset height is formed below the bump to be formed in advance, so that the opening height difference caused in the subsequent process of forming the opening on the insulating layer can be compensated, the sinking degree of the bump at the interface of the metal column and the metal cap can be reduced, or the sinking of the bump at the interface of the metal column and the metal cap can be avoided, the performance of the bump is improved, and the performance and the service life of a device can be improved finally.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

Drawings

FIG. 1 illustrates a cross-sectional view of a semiconductor package in accordance with an aspect of the present invention;

fig. 2 (a) to 2 (g) are cross-sectional views corresponding to respective processing steps for forming a bump on a pad of a semiconductor chip provided according to a first embodiment of the present invention;

fig. 3 (a) to 3 (g) are cross-sectional views corresponding to respective processing steps for forming a bump on a pad of a semiconductor chip according to a second embodiment of the present invention;

fig. 4 is a cross-sectional view of a semiconductor package structure according to a third embodiment of the present invention.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully hereinafter with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "below 8230; below," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element (or elements) or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Semiconductor structures (which may also be referred to as semiconductor devices or semiconductor devices) are typically fabricated using two complex fabrication processes: front end manufacturing and back end manufacturing. Front end fabrication involves the formation of multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional electrical circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of current. Passive electrical components such as capacitors, inductors and resistors create the relationship between voltage and current necessary to perform the electrical circuit function.

Active and passive components are formed over the surface of a semiconductor wafer by a series of process steps including doping, deposition, photolithography, etching, and planarization. Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process modifies the conductivity of the semiconductor material in the active device by dynamically changing the conductivity of the semiconductor material in response to an electric field or base current. Transistors contain regions of different doping types and doping levels arranged as necessary to enable the transistor to promote or restrict the flow of current when an electric field or base current is applied.

The active and passive components are formed by layers of materials having different electrical properties. The layers may be formed by various deposition techniques determined in part by the type of material being deposited. For example, thin film deposition may include Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), electrolytic plating, and electroless plating processes. Each layer is typically patterned to form portions of active components, passive components, or electrical connections between components.

Back-end fabrication refers to the dicing or singulation of the finished wafer into individual semiconductor dies and the packaging of the semiconductor dies for structural support, electrical interconnection, and environmental isolation. The completed package is then inserted into an electrical system and the functionality of the semiconductor device is made available to other system components.

Herein, the organic insulating layer serves as a barrier layer of the bump to protect the semiconductor chip during the bump flip chip bonding process. Specifically, the organic insulating layer refers to a thin film organic insulating material applied to or coating the semiconductor chip to protect the semiconductor chip during back-end processing to form the bump. The organic insulating layer is also referred to as a post-wafer handle dielectric layer. Back-end processing of semiconductor chips involves forming bumps on exposed pads of the semiconductor chip to enable an integrated circuit die formed on the semiconductor chip to be subsequently packaged, for example in a flip-chip semiconductor package. An organic insulating layer is formed on the finished semiconductor chip prior to bump formation and is used to provide a mechanical stress buffer between the semiconductor chip and the bumps formed thereon. The organic insulating layer is typically a thin film polymer material such as Polyimide (PI) or Polybenzoxazole (PBO).

Example one

Fig. 2 (a) to 2 (g) are cross-sectional views showing respective processing steps for forming a bump on a pad of a semiconductor chip provided according to a first embodiment of the present invention. As shown in fig. 2 (a) to 2 (g), the semiconductor package 2 of the present embodiment includes: semiconductor chip 21, insulating layer 25, metal block 24, and bump 28. Wherein the semiconductor chip 21 has a passivation layer 23, and the passivation layer 23 at least partially covers the first surface of the semiconductor chip 21 and exposes at least a portion of the bonding pad 22. The insulating layer 25 is formed on the passivation layer 23, and an opening 251 is formed in the insulating layer 25. The metal block 24 is located in the opening 251, and the metal block 24 partially covers the bottom of the opening 251. The bump 28 is formed at a position corresponding to the opening 251, and the bump 28 extends to the bottom of the opening 251 and the top of the metal block 24 in the opening, and the bump 28 is electrically connected to the pad 22 through the opening 251 and the metal block 24, and is electrically connected to the semiconductor chip 21 through the pad 22. Specifically, the bump 28 includes a first metal pillar 281 and a metal cap 282 on top of the first metal pillar 281.

In this embodiment, the semiconductor chip 21 may include a semiconductor substrate, active devices, and interconnect structures (not separately shown). For example, the substrate may comprise doped or undoped bulk silicon, or an active layer comprising a semiconductor-on-insulator substrate. Typically, the substrate comprises a layer of semiconductor material (such as silicon) formed on an insulating layer. Alternatively, the substrate may include: another elemental semiconductor such as germanium; a compound conductor comprising silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP, and/or GaInAsP; or a combination thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

Active or passive devices such as one or more transistors, capacitors, resistors, inductors, diodes, photodiodes, fuses, and the like may be formed at the top surface of the substrate. In some embodiments, the semiconductor chip 21 includes a single active device, such as a diode or a power MOSFET.

An interconnect structure may be formed over the active or passive devices and the substrate. The interconnect structure may include an inter-layer dielectric (ILD) layer and/or an inter-metal dielectric (IMD) layer that include conductive features (e.g., conductive lines and vias including aluminum, copper, tin, nickel, gold, silver, tungsten, combinations thereof, and the like) formed using any suitable method. In some embodiments, for example, the ILD and IMD may be formed from phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), siOxCy, spin-on glass, spin-on polymers, silicon carbide materials, compounds thereof, composites thereof, combinations thereof, and the like, formed by any suitable method, such as PVD, electrolytic plating, electroless plating process, spin-on, chemical Vapor Deposition (CVD), or Plasma Enhanced (PECVD). The interconnect structure electrically connects the various active or passive devices to form functional circuitry within the semiconductor die 21. The functions provided by such circuits may include memory structures, processing structures, inductors, amplifiers, power distribution, input/output circuitry, and so forth. Those of ordinary skill in the art will appreciate that the above examples are provided for illustrative purposes only to further explain the application of the various embodiments and are not meant to limit the embodiments in any way. Other circuits may be used as appropriate for a given application.

Referring to fig. 2 (a), the semiconductor chip 21 further includes a passivation layer 23 and a pad 22, wherein the passivation layer 23 and the pad 22 may be formed over the first surface of the semiconductor chip 21 and the interconnect structure. For example, the pads 22 may be formed over an interconnect structure and may be electrically connected to active devices through various conductive features in the interconnect structure. The pads 22 may comprise a conductive material such as aluminum, copper, or the like. The passivation layer 23 at least partially covers the first surface of the semiconductor chip 21 and exposes at least a portion of the pad 22. In some embodiments, a portion of the passivation layer 23 may cover an edge portion of the pad 22, and the first surface of the semiconductor chip 21 is completely covered by the passivation layer 23 except for the exposed portion of the pad 22. Alternatively, the passivation layer 23 may be formed of a non-organic material such as silicon oxide, undoped silicate glass, silicon oxynitride, or the like, and other suitable passivation materials may be used.

The metal block 24 is formed on the upper surface of the portion of the pad 22 not covered with the passivation layer 23, and is electrically connected to the pad 22. In some embodiments, the metal block 24 has a predetermined height. In this manner, a predetermined height difference can be formed on the upper surface of the portion of the pad 22 not covered by the passivation layer 23. Alternatively, metal block 24 comprises a conductive material such as aluminum, copper, or the like, and is formed using any suitable process such as electroplating (e.g., applying photoresist-photolithography-electroplating-removing photoresist).

Referring to fig. 2 (b), an insulating layer 25 may be formed over the passivation layer 23 using an insulating material. The semiconductor package 2 introduces a significant amount of stress to the integrated circuit die when performing the bump-flip-chip bonding process. To improve reliability, an insulating layer 25 is applied onto the passivation layer 23 to cover the passivation layer 23 and the pad portions (including covering the metal blocks 24 located on the pad portions) not covered by the passivation layer 23 before the bumps 28 are formed. In some embodiments, the insulating layer 25 may be an organic insulating layer formed using an organic insulating material. The organic insulating layer covers the upper surface of the passivation layer 23 and exposes only the pad 22. The organic insulating material is typically polyimide or polybenzoxazole, and the insulating layer 25 is also referred to herein as a polyimide layer or a polybenzoxazole layer.

Referring to fig. 2 (b), the insulating layer 25 is patterned, for example, by photolithography using a reticle to the insulating layer 25, and portions of the insulating layer 25 in certain areas above and around the metal blocks 24 are removed by development to form openings 251 in the corresponding pads 22 to expose the metal blocks 24. At this time, the opening 251 is located above the position of the pad 22, the metal block 24 is located in the opening 251, and the metal block 24 partially covers the bottom of the opening 251, that is, the opening 251 formed on the insulating layer 25 exposes a part of the surface of the pad 22 in addition to the metal block 24. Thus, when the bump 28 is formed in the opening 251, the bottom surface area of the bump 28 can be increased, which is favorable for enhancing the bonding force and the conductive capability between the bump 28 and the pad 22 and the metal block 24. In some preferred embodiments, the metal block 24 is located in the central region of the bottom of the opening 251 so as to further enhance the bonding force between the bump 28 and the pad 22 and the metal block 24.

In the embodiment of the present invention, since the metal block 24 with a predetermined height is formed on the pad 22 in advance before the insulating layer 25 is formed, based on the predetermined height difference formed by the metal block 24 on the pad 22, the opening height difference caused in the subsequent process of forming the opening 251 on the insulating layer 25 can be compensated, so as to reduce the degree of dishing occurring at the interface between the first metal pillar 281 and the metal cap 282 during bump formation, or avoid the dishing occurring at the interface between the first metal pillar 281 and the metal cap 282 during bump formation 28, improve the performance of the bump, and finally improve the performance and the service life of the device.

Alternatively, after this patterning process, the insulating layer 25 may cover the entire first surface of the semiconductor chip 21 except for the openings 251 on the pads 22. The insulating layer 25 may also be patterned only to the areas around and adjacent to the bumps 28, removing the insulating layer from all remaining areas of the semiconductor chip 21 to significantly reduce or eliminate the stress introduced on the semiconductor chip 21 by the organic insulating layer.

As shown in fig. 2 (c), a seed metal layer 26 may also be formed on the insulating layer 25, the opening 251, and the metal block 24, the seed metal layer 26 containing Al, cu, sn, ni, au, ag, or other suitable conductive material. In one embodiment, the seed metal layer 26 may be formed by sputtering a titanium-copper (Ti-Cu) layer, or a titanium-nickel-copper (TiNi-Cu) layer, or a titanium/tungsten-copper (TiW-Cu) layer, or an aluminum-nickel-copper (Al-Ni-Cu) layer, or a chromium-chromium/copper-copper (Cr-CrCuCu) layer. Alternatively, electroless copper plating may be performed on the insulating layer 25, the opening 251, and the metal block 24 to deposit the seed metal layer 26. Seed metal layer 26 may serve as a plating seed layer to facilitate subsequent electroplating formation of bumps 28, while also ensuring a good electrical connection between bumps 28 and pads 22.

In some embodiments, a photolithographic mask is used to form bumps 28. A photoresist layer 27 may be applied to the upper surface of the insulating layer 25, the photoresist layer 27 being patterned to expose the area above the pad 22 (including exposing the bottom of the opening 251, the top of the metal block 24 within the opening 251, and a portion of the insulating layer 25), as shown in fig. 2 (d). And sequentially forming a first metal pillar 281 and a metal cap 282 in the window of the photoresist layer 27 by metal plating, thereby forming a bump 28, as shown in fig. 2 (e). Bumps 28 may be used to electrically connect semiconductor package structure device 2 to other package components such as another device die, interposer, package substrate, printed circuit board, motherboard, and the like. Although a photolithographic mask is used in this example to form the first metal pillars 281. In other embodiments, however, electrolytic plating, electroless plating, or other suitable deposition processes may be used to form the first metal studs 281 from Al, cu, sn, ni, au, ag, titanium (Ti), tungsten (W), other suitable conductive materials, or alloys thereof. And a metal cap 282 formed by plating or otherwise depositing Ni, au, sn, ag, or a combination thereof over the first metal pillar 281. In some embodiments, the metal cap 282 comprises a lead-free solder.

Further, in some other examples, forming a nickel adhesion layer between the first metal pillar 281 and the metal cap 282 is also included.

After the metal plating process, the photoresist layer 27 is removed as shown in fig. 2 (f). Thereafter, the seed metal layer 26 is etched to remove all of the exposed seed metal layer 26, leaving only the portion of the seed metal layer 26 under the bump 28, as shown in fig. 2 (g). The semiconductor chip is then subjected to a reflow soldering process to complete the formation of bumps 28. More specifically, the reflow process rounds the metal caps 282 to form rounded solder caps for the bumps 28, as shown in fig. 2 (g).

The cross-sectional dimensions of the bumps 28 formed in the embodiment of the present invention are all larger than the cross-sectional dimensions of the openings 251 on the insulating layer 25, so that the bottoms of the bumps 28 cover the bottoms of the openings 251, the tops of the metal blocks 24, and a part of the insulating layer 25, so that a large amount of stress introduced by the semiconductor package structure 2 during the flip-chip bonding process of the bumps can be partially borne by the insulating layer 25, thereby improving reliability.

The difference between the thickness of the metal block 24 and the thickness of the insulating layer 25 is smaller than a predetermined value. And it is preferable that the thickness of the metal block 24 is the same as that of the insulating layer 25, or the thickness of the metal block 24 is slightly greater than that of the insulating layer 25. As shown in fig. 2 (e) to fig. 2 (g), in the bump 28 formed according to the embodiment of the present invention, the top surface of the first metal pillar 281 is a plane parallel to the first surface of the semiconductor chip 21, or is a curved surface with a central region higher than a predetermined height of an edge region, so that void generated by co-metallization at an interface of the first metal pillar 281 and the metal cap 282 can overflow in time when a thermal process is performed after flip-chip mounting in a later-stage packaging process, and a recess as shown in fig. 1 does not occur, thereby improving the performance of the bump, the performance of the semiconductor device, and the service life of the semiconductor device.

Example two

The semiconductor package structure disclosed in this embodiment is shown in fig. 3 (a) to 3 (g).

The structure and the forming method of the semiconductor package 3 disclosed in this embodiment are substantially the same as those of the semiconductor package 2 shown in the first embodiment, and the same parts can be referred to each other, so that the details are not repeated.

The difference lies in that: the semiconductor package 3 shown in the present embodiment is formed in a different order from that in the first embodiment when the insulating layer 25 and the metal block 24 are formed. Referring to fig. 3 (a), the insulating layer 25 is formed on the passivation layer 23 in the present embodiment.

After that, referring to fig. 3 (a) and 3 (b), an opening 251 is formed on the insulating layer 25. And forming a seed metal layer 26 on the insulating layer 25 and the opening 251.

Then, referring to fig. 3 (c), a metal block 24 located within the opening 251 is formed on the seed metal layer 26.

Then, referring to fig. 3 (d) to 3 (g), the process described with reference to fig. 2 forms bumps 28 in the upper region of the pads 22.

The functions and the formation processes of the various layer structures in the semiconductor package structure 3 of this embodiment can be understood by referring to the corresponding descriptions in the first embodiment, which are not described herein again.

It can be understood that, based on the process sequence of the semiconductor package structure 3 disclosed in this embodiment, the seed metal layer 26 in the formed semiconductor package structure 3 has a gentle surface structure in the opening 251, so that the structural stability of the formed seed metal layer 26 and the reliability of the surface bonding with the metal block 24 are enhanced, which is beneficial to improving the stability of the formed bump 28.

EXAMPLE III

The semiconductor package structure disclosed in this embodiment is shown in fig. 4.

The structure and the forming method of the semiconductor package structure 4 disclosed in this embodiment are substantially the same as those of the semiconductor package structure 2 shown in the first embodiment or the semiconductor package structure 3 shown in the second embodiment, and the same parts can be referred to each other, so that the details are not repeated.

The difference is that: the semiconductor package 4 shown in the present embodiment further includes: a redistribution layer (RDL) 29 located between the pad 22 and the insulating layer 25. This redistribution layer 29 is electrically connected to the pad 22 and the bump 28, respectively, in other words, at this time, the bump 28 is electrically connected to the pad 22 through the insulating layer opening, the metal block 24, and the redistribution layer 29.

In this embodiment, the bump 28 remote from the pad 22 may be formed using a rewiring process. The redistribution layer 29 is a layer of metal, such as copper, and is formed on the integrated circuit die to act as a route (runner) or trace to redirect the pad 22 to the bump location of a new bump. In this manner, the bump locations may be rearranged on the integrated circuit die, and the locations of the bumps 28 are not limited by the layout of the pads 22 on the integrated circuit die.

Referring to fig. 2 (a) to 2 (g) previously described, unlike the first embodiment, the present embodiment further includes depositing a redistribution layer 29 on the passivation layer 23 and in the exposed pad 22 region before forming the metal block 24. The rewiring layer 29 is typically formed by electroplating copper.

Then, metal block 24 having a predetermined height may be formed at a position where bump 28 is to be formed on the upper surface of redistribution layer 29 by the process described with reference to fig. 2. And an insulating layer 25 and bumps 28 may be formed on the redistribution layer 29 and the metal blocks 24 in sequence by the process described with reference to fig. 2. At this time, the insulating layer 25, the insulating layer opening, the metal block 24, and the bump 28 are all located above the redistribution layer 29.

In this embodiment, the redistribution layer 29 and the pad 22 are electrically connected by at least one second metal stud 291, and the redistribution layer 29 and the bump 28 are electrically connected by the first metal stud 281 and the metal block 24. In some examples, the at least one second metal stud 291 may be fabricated with the redistribution layer 29.

It is understood that the bumps 28 in the semiconductor package 4 formed in the present embodiment have the same structure as the bumps 28 in the first embodiment, and can achieve the same functions and advantages.

It should be noted that, in other embodiments of the present invention, two or more pads 22, insulating layer openings, and bumps 28 may also be formed on the first surface of the semiconductor chip 21 according to the schemes described in the foregoing embodiments, and the metal blocks 24 are formed in the insulating layer openings under at least one of the two or more bumps 28, so that various semiconductor package structures and corresponding packaging methods extended therefrom are also within the protection scope of the present invention.

Further, the present invention also discloses an electronic device having a plurality of semiconductor packages mounted on a surface of a PCB together with at least one of the semiconductor package structure 2, the semiconductor package structure 3, and the semiconductor package structure 4 shown in the foregoing embodiments. The electronic device may have one type of semiconductor package or a plurality of types of semiconductor packages depending on the application.

It is understood that the electronic device may be a stand-alone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, the electronic device may be a subcomponent of a larger system. For example, it may be part of a tablet computer, cellular telephone, digital camera, communication system, or other electronic device. The electronic device may also be a graphics card, a network interface card, or other signal processing card that may be integrated into a computer. In some examples, a semiconductor package in the electronic device may include a microprocessor, memory, ASIC, logic circuit, analog circuit, RF circuit, discrete device, or other semiconductor die or electrical component.

Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.

Claims

1. A semiconductor package structure, comprising:

the semiconductor chip is provided with a passivation layer, and the passivation layer covers the first surface of the semiconductor chip and exposes the bonding pad;

the insulating layer is formed on the passivation layer and is provided with an opening;

2. The semiconductor package structure of claim 1, wherein the bottom of the bump covers the bottom of the opening, the top of the metal block within the opening, and a portion of the insulating layer.

3. The semiconductor package structure of claim 1, wherein the metal block is located in a central region of the bottom of the opening.

4. The semiconductor package structure of claim 1, wherein the bump comprises a first metal pillar and a metal cap on top of the first metal pillar.

5. The semiconductor package structure of claim 1, wherein a difference between a thickness of the metal block and a thickness of the insulating layer is less than a predetermined value.

6. The semiconductor package structure of claim 1, wherein the opening is located over the pad location.

7. The semiconductor package structure of claim 1, further comprising:

8. The semiconductor package structure of claim 1, wherein the insulating layer comprises a polyimide layer or a polybenzoxazole layer.

9. A semiconductor packaging method, comprising:

10. The semiconductor packaging method of claim 9, wherein the method of forming the metal block and the insulating layer having the opening comprises:

forming a metal block electrically connected with the bonding pad;

forming an insulating layer covering the passivation layer and the metal block;

11. The semiconductor packaging method according to claim 9, wherein the method of forming the insulating layer having the opening and the metal block comprises:

forming the insulating layer with an opening over the passivation layer;

and forming the metal block in the opening.

12. The semiconductor packaging method according to any one of claims 9 to 11, wherein the metal block is formed in a central region of the bottom of the opening.

13. The semiconductor packaging method of any of claims 9-11, wherein, prior to forming the insulating layer and the metal block, further comprising:

and forming a rewiring layer positioned on the passivation layer, wherein the opening is positioned above the rewiring layer, and the bump is electrically connected with the bonding pad through the opening, the metal block and the rewiring layer.