CN111739806A - Indium ball array manufacturing method of focal plane detector with small center distance - Google Patents

Indium ball array manufacturing method of focal plane detector with small center distance Download PDF

Info

Publication number
CN111739806A
CN111739806A CN202010623570.1A CN202010623570A CN111739806A CN 111739806 A CN111739806 A CN 111739806A CN 202010623570 A CN202010623570 A CN 202010623570A CN 111739806 A CN111739806 A CN 111739806A
Authority
CN
China
Prior art keywords
indium
photoresist
hole pattern
metal
focal plane
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010623570.1A
Other languages
Chinese (zh)
Inventor
马英杰
朱宪亮
邵秀梅
李雪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Institute of Technical Physics of CAS
Original Assignee
Shanghai Institute of Technical Physics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Institute of Technical Physics of CAS filed Critical Shanghai Institute of Technical Physics of CAS
Priority to CN202010623570.1A priority Critical patent/CN111739806A/en
Publication of CN111739806A publication Critical patent/CN111739806A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Ceramic Engineering (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

The invention discloses a method for manufacturing an indium ball array of a focal plane detector with small center distance, which comprises the following steps: 1) coating photoresist on the chip, and generating an electrode hole pattern on the photoresist; 2) sequentially steaming three layers of metal of chromium plating, nickel and gold; 3) removing the photoresist to produce a metal electrode; 4) depositing a medium film layer; 5) coating photoresist and generating a contact hole pattern on the photoresist; 6) etching to remove the medium film in the hole and removing the photoresist; 7) coating photoresist and generating an indium hole pattern on the photoresist; 8) evaporating indium metal; 9) removing the photoresist to generate an indium column array; 10) and carrying out thermal reflux treatment to generate an indium ball array. The method has the advantages of overcoming the problem of poor shape consistency of indium columns after balling in the traditional gold priming layer process, manufacturing the indium ball array with high uniformity and high saturation and larger duty ratio, and improving the connectivity of the inverse welding interconnection of the focal plane and the reading circuit.

Description

Indium ball array manufacturing method of focal plane detector with small center distance
Technical Field
The invention belongs to the technical field of manufacturing of semiconductor photoelectric detection chips, and particularly relates to a method for manufacturing an indium ball array of a focal plane detector with a small center distance.
Background
The semiconductor focal plane detector is mainly applied to detection applications such as imaging and spectrum. According to different detection wavelength ranges, the infrared detector can be divided into ultraviolet, visible, short-wave infrared, medium-wave infrared, long-wave infrared and very-long-wave infrared devices. The main focal plane devices with different wave bands are GaN/AlGaN (ultraviolet), Si (visible), InGaAs (short wave infrared), InAs/GaSb (medium wave infrared) and HgCdTe (medium wave wavelength very long wave infrared). Because the existing CMOS integrated circuit process is mainly manufactured based on a Si process, the focal plane detectors of the rest wave bands except for the visible light focal plane detector are mixed and integrated with a Si reading circuit through an indium stud flip chip bonding interconnection technology to form an integrated detector module of a photosensitive chip and a reading circuit. And preparing corresponding metal indium columnar electrodes on each pixel structure, aligning and extruding pixels of the reading circuit and pixels of the photosensitive chip one by one, so that reliable electrical connection is formed between the pixels of the reading circuit and the pixels of the photosensitive chip through van der Waals force of indium columns and indium columns or a hot melting welding mode of the indium columns and the indium columns/the metal electrodes, and focal plane hybrid integration is realized. Therefore, the size, shape and consistency of the indium columns directly determine the connectivity of the interconnection between the readout circuit chip and the photosensitive chip.
In the middle of the foreign 90 s, mega-pixel HgCdTe infrared focal plane detector with the pixel scale of 1024 x 1024 and the center distance of 30 microns has been developed. At present, focal plane detection is moving towards larger pixel scale, smaller center-to-center distances. Focal plane pixel center-to-center distances have evolved from the early 100 microns to 5 microns. The pixel size has also evolved from 320 x 256, an early monolithic, to 4096 x 4096, now. The increased pixel size, increased individual chip size, and continued reduction in center-to-center spacing create significant challenges for indium stud flip-chip connectivity. By utilizing the surface tension characteristic of indium and through thermal reflow treatment, indium balls are formed, the consistency of the indium column array can be improved to a certain extent, and the communication rate is improved. Limited by the reduction in center-to-center spacing, the size of the indium balls is correspondingly reduced. Therefore, more rigorous requirements are put forward on the shape, consistency, height, plumpness and the like of the indium balls. Although the problem of reduced connectivity caused by reduced center distance and reduced indium column size can be compensated to a certain extent by preparing indium balls on both sides of the read-out circuit and the photosensitive chip, the size, shape and consistency of the indium balls are still fundamental limits for realizing 100% connectivity.
The traditional indium column manufacturing process is to use a gold electrode with a thin layer as a bottom layer on a metal electrode of chromium, platinum, nickel and the like, and then manufacture an indium column (CN201410624296.4) through a photoetching metal evaporation process. By utilizing the infiltration characteristic between the gold priming layer and the indium in the high-temperature backflow balling process, the shape transformation from the indium columns to the indium balls at fixed positions is realized, and the consistency is improved. However, under a small center distance, because the sizes of the electrode and the indium column are synchronously reduced, and photoetching registration deviation is more easily generated, the problems of local curling, indium flow retardation and the like caused by the inconsistency of the metal and the semiconductor or the metal and the dielectric film material in the indium column hot reflux balling process exist, so that the indium ball array with high fullness and high uniformity is difficult to prepare under the small center distance. Although some improved technical solutions, including a double-layer photoresist stripping manufacturing process (CN201510945699.3), a mechanical planarization uniformity improving process (CN201410259001.8), etc., still have the problems of local curling, indium flow retardation, etc. during the thermal reflow process of the indium column, and it is difficult to achieve high-uniformity indium ball manufacturing with a small center distance. Therefore, technical innovation is needed to solve the problem of non-uniformity in the indium column reflow balling process and realize the manufacture of the indium ball array with high density and high uniformity under small center distance.
Disclosure of Invention
The invention provides a method for manufacturing an indium ball array of a focal plane detector with small center distance, which solves the problem of non-uniformity in the process of indium column backflow balling and realizes the manufacture of the indium ball array with small size and high uniformity under the condition of small center distance.
In order to solve the problems, the invention discloses a method for manufacturing an indium ball array of a focal plane detector with small center distance, which sequentially comprises the following steps: 1) coating photoresist on the chip, and generating an electrode hole pattern on the photoresist; 2) sequentially steaming three layers of metal of chromium plating, nickel and gold; 3) removing the photoresist to produce a metal electrode; 4) depositing a medium film layer; 5) coating photoresist and generating a contact hole pattern on the photoresist; 6) etching to remove the medium film in the hole and removing the photoresist; 7) coating photoresist and generating an indium hole pattern on the photoresist; 8) evaporating indium metal; 9) removing the photoresist to generate an indium column array; 10) and carrying out thermal reflux treatment to generate an indium ball array.
Further, in the step 1), an ultraviolet lithography process is adopted, the photoresist can be a positive or negative photoresist, the electrode holes can be in a circular, square, polygonal shape and the like, the maximum width of the electrode holes is not more than 75% of the center distance, and the minimum width of the electrode holes is not less than 30% of the center distance.
Further, in the step 2), the order of the metal deposition is chromium, nickel and gold from bottom to top. Wherein the lower chromium layer is a contact layer with the thickness of 20-100 nm; the upper layer of gold is a wetting layer, the thickness of the upper layer of gold is 50-100nm, and the upper layer of gold is used for being co-melted and wetted with indium in the heating reflux process and positioning the balling position of the indium balls; the middle nickel is an electrode thickening layer and a blocking layer, the thickness of the middle nickel is 200-600nm, the middle nickel is used for thickening the contact electrode, and simultaneously the indium is blocked from reacting with the lower electrode in the thermal reflux process. The evaporation method adopts process equipment such as thermal evaporation coating, electron beam evaporation coating, magnetron sputtering coating, ion beam sputtering coating and the like.
Further, in the step 3), according to the type of the photoresist used in the step 1), a corresponding photoresist removing reagent is adopted to dissolve and remove the photoresist, and the metal electrode structure evaporated in the previous step is stripped.
Further, in the step 4), the deposited dielectric film is silicon nitride or silicon oxide, and the film thickness is
100-1000 nm. The method is used for generating the coating of uniform materials on the surface of the chip.
Further, in the step 5), the photoresist can adopt a positive or negative photoresist, and an ultraviolet lithography process is adopted, and the contact hole pattern is generated through mask exposure and development. The center of the contact hole is aligned with the center of the metal electrode in the previous step. The size of the contact hole is smaller than that of the metal electrode, and the shape of the contact hole is square, circular or polygonal.
Further, in the step 6), etching the dielectric film by using SF-based etching4And the dry plasma etching process with Ar etchant includes RF ion beam etching, reactive ion etching, inductively coupled plasma etching, etc. Or a wet etching process based on hydrofluoric acid solution is adopted, and the wet etching process comprises hydrofluoric acid-ammonium fluoride buffer solution, hydrofluoric acid-water diluent and the like. And removing the dielectric film layer in the pattern hole of the contact electrode hole in the previous step by etching. Contact vias for interconnecting the metal layers and the indium stud layers are created.
And (5) according to the type of the photoresist used in the step 5), adopting a corresponding photoresist removing reagent to dissolve and remove the photoresist, and cleaning to generate a contact electrode hole structure.
Further, in the step 7), the photoresist may adopt a positive or negative photoresist, and an ultraviolet lithography process is adopted, and the indium hole pattern is generated through mask exposure and development. The center of the indium hole is aligned with the center of the contact electrode hole generated in the previous step. The size of the indium hole pattern is larger than that of the metal electrode and smaller than the focal plane center distance. The shape is square, round or polygonal.
Further, in the step 8), the evaporation thickness of the indium metal is smaller than that of the photoresist coated in the step 7). The evaporation method can adopt process equipment such as thermal evaporation coating, electron beam evaporation coating, magnetron sputtering coating, ion beam sputtering coating and the like.
Further, in the step 9), according to the type of the photoresist used in the step 7), a corresponding photoresist removing reagent is adopted to dissolve and remove the photoresist, and the indium metal columnar electrode structure deposited in the previous step is stripped. An array of indium columns is produced.
Further, in the step 10), the chip containing the indium column array generated in the above step is placed in a reflow furnace, the heating temperature is 200 ℃ and 250 ℃, and formic acid vapor is introduced. The heating action is to melt the indium columns and naturally reflux under the action of surface tension to form a spherical structure. The formic acid steam acts on the indium oxide on the surface in the process, so that the oxide layer is removed and the indium ball resistance is reduced.
And after the above process steps are completed, obtaining the indium ball array with consistent size and high uniformity. The requirement of high reverse welding connectivity of the high-density pixel focal plane chip with the center distance of less than or equal to 15 micrometers is met.
Advantageous effects
(1) The invention adopts the dielectric film to coat, combines the chromium-nickel-gold specific multilayer metal electrode structure, fundamentally avoids the interface problem of materials, and effectively solves the problem of poor balling consistency of indium columns prepared by the traditional priming layer process. The problems of local curling, indium flow retardation and the like caused by the inconsistency of materials of metal and semiconductor or metal and dielectric film in the process of forming the indium column by thermal reflow are effectively solved, the consistency of the appearance and the size of the indium ball array is obviously improved, and the connectivity of the focal plane inverse welding interconnection is improved.
(2) The method is particularly suitable for manufacturing the indium ball array with high uniformity of the focal plane with small center distance, and the tolerance capability, the repeatability and the reliability of the process are improved. Because the influence of photoetching registration deviation of patterns such as metal electrodes, indium columns and the like is more prominent under the condition of small center distance, adverse influence is more easily generated on the reflux consistency in the indium column balling process. The invention leads the interface problem of metal-semiconductor-metal material to be no longer existed by introducing the dielectric film coating, and even if a certain photoetching alignment deviation exists, the consistency of the indium column backflow balling process is not influenced. The reliability of indium column preparation of the focal plane with the center distance of 15 microns or below is effectively improved. The manufacture of the indium ball array with high density and high uniformity is realized.
(3) The method for manufacturing the indium ball array of the focal plane detector with the small center distance is completely compatible with the conventional universal semiconductor processes such as ultraviolet lithography, metal coating, dielectric film deposition, etching and the like, and has the advantages of high process feasibility and high equipment compatibility. Meanwhile, the manufacturing method of the invention can also be suitable for manufacturing the focal plane high-uniformity indium ball array with the center distance of more than 15 microns, and the consistency of the indium ball appearance is improved. And the communication rate of the interconnection of the focal plane photosensitive chip and the reading circuit is improved. Can be widely applied to the manufacture of indium columns of focal plane photosensitive chips with different wave bands and different center distances, such as InGaAs, HgCdTe, InAs/GaSb superlattice, GaAs/AlGaAs quantum wells and the like.
Drawings
Fig. 1 is a schematic process flow diagram of an indium column manufacturing method of a focal plane detector with a small center distance according to the present invention.
Fig. 2 is a topography of an indium ball electron microscope with a center distance of 15 microns and high uniformity obtained in example 1 of the invention.
Fig. 3 is a topography of an indium ball electron microscope with a center distance of 10 microns and high uniformity obtained in example 2 of the present invention.
Detailed Description
The invention will be further illustrated with reference to the following specific examples. It should be understood that this example is only for illustrating the present invention and is not intended to limit the scope of the present invention. It should be understood that various changes and modifications can be made by those skilled in the art after reading the teachings herein, and such equivalents also fall within the scope of the invention as defined by the appended claims.
Example 1
The purpose of the embodiment is to manufacture a high-uniformity indium ball array meeting the requirement of inverse welding with a reading circuit by adopting the manufacturing method of the high-uniformity indium ball array aiming at an InAs/GaSb secondary superlattice medium wave infrared focal plane photosensitive chip with the center distance of 15 microns, and to verify the feasibility of the invention.
Based on the InAs/GaSb second-class superlattice focal plane photosensitive chip after the p-contact electrode is prepared, the preparation method comprises the following steps:
(1) and adopting AZ4330 positive photoresist to generate a square contact electrode hole pattern in the center of the pixel through ultraviolet exposure and development. The pore side is 7 microns.
(2) And (3) evaporating three layers of metal of chromium plating, nickel plating and gold plating in sequence by adopting ion beam sputtering coating equipment, wherein the thicknesses of the three layers of metal are respectively 100nm, 600nm and 100 nm.
(3) And soaking in acetone to dissolve and remove the photoresist and strip the evaporated metal electrode structure.
(4) Deposition of SiN using inductively coupled chemical vapor deposition apparatusxThin film, thickness 1000 nm.
(5) And adopting AZ1500 positive photoresist, and generating a square contact hole pattern in the center of the pixel through ultraviolet exposure and development. The pore side is 6 microns. The center of the contact hole is aligned with the center of the metal electrode in the previous step.
(6) Using reactive ion etching equipment, using SF4And (5) taking gas as an etchant to etch and remove the SiNx film layer in the contact hole pattern hole in the previous step. And soaking with acetone, dissolving and removing the photoresist, and cleaning to obtain the SiNx contact hole structure.
(7) And an AZ4620 positive photoresist is adopted, and a circular indium hole pattern is generated through ultraviolet exposure and development, wherein the hole diameter is 7 microns, and the photoresist thickness is 7 microns. The center of the indium hole is aligned with the center of the contact electrode hole generated in the previous step.
(8) And evaporating an indium metal layer by adopting thermal evaporation equipment, wherein the thickness of the indium metal layer is 6.5 microns.
(9) And soaking by using acetone, dissolving and removing the photoresist, cleaning, and stripping to generate an indium column electrode structure to generate an indium column array.
(10) Adopting a heat flow furnace device, introducing formic acid steam, keeping the highest heat treatment temperature of 200 ℃ for 5 minutes, and keeping the highest temperature for 1 hour.
After the above steps are completed, the focal plane photosensitive chip is taken out from the reflow furnace, and a high-uniformity indium ball array with a center distance of 15 microns is obtained, wherein the appearance is shown in fig. 2. The indium balls have high shape consistency, large duty ratio, full shape, 7.5 micrometers of average diameter and high positioning precision, and meet the requirement of high connectivity rate reverse welding interconnected with a 15-micrometer center distance reading circuit.
Example 2
The purpose of this embodiment is to manufacture a high-uniformity indium ball array meeting the requirement of flip chip bonding with a readout circuit by using the manufacturing method of the high-uniformity indium ball array for an InGaAs/InAsP/InP short-wave infrared focal plane photosensitive chip with a center distance of 12.5 microns, and to verify the feasibility of the invention.
Based on the nGaAs/InAsP/InP focal plane photosensitive chip after the p contact electrode is prepared, the manufacturing method comprises the following steps:
(1) and adopting AZ4330 positive photoresist to generate a square contact electrode hole pattern in the center of the pixel through ultraviolet exposure and development. The pore side is 6 microns.
(2) And (3) evaporating three layers of metal, namely chromium plating, nickel plating and gold plating in sequence by adopting ion beam sputtering coating equipment, wherein the thicknesses of the three layers of metal are respectively 50nm, 400 nm and 70 nm.
(3) And soaking in acetone to dissolve and remove the photoresist and strip the evaporated metal electrode structure.
(4) Deposition of SiN using inductively coupled chemical vapor deposition apparatusxFilm thickness 500 nm.
(5) And adopting AZ1500 positive photoresist, and generating a square contact hole pattern in the center of the pixel through ultraviolet exposure and development. The pore side is 5 microns. The center of the contact hole is aligned with the center of the metal electrode in the previous step.
(6) Using reactive ion etching equipment, using SF4Gas is used as an etchant to etch and remove SiN in the contact hole pattern holesxAnd (5) film layer. Soaking in acetone, dissolving and removing photoresist, cleaning to obtain SiNxAnd (5) a contact hole structure.
(7) And an AZ4620 positive photoresist is adopted, and a circular indium hole pattern is generated through ultraviolet exposure and development, wherein the hole diameter is 6 microns, and the photoresist thickness is 7 microns. The center of the indium hole is aligned with the center of the contact electrode hole generated in the previous step.
(8) And evaporating an indium metal layer with the thickness of 5.5 microns by adopting thermal evaporation equipment.
(9) And soaking by using acetone, dissolving and removing the photoresist, cleaning, and stripping to generate an indium column electrode structure to generate an indium column array.
(10) Adopting a heat flow furnace device, introducing formic acid steam, keeping the highest heat treatment temperature at 220 ℃ for 5 minutes, and keeping the highest temperature for 1 hour.
And after the above process steps are completed, taking out the focal plane photosensitive chip from the reflow furnace to obtain the high-uniformity indium ball array with the center distance of 12.5 microns. The indium balls have high shape consistency, large duty ratio, full shape, 6-micron average diameter and high positioning precision, and meet the requirement of high connectivity rate reverse welding interconnected with a 12.5-micron center distance reading circuit.
Example 3
The purpose of this embodiment is to manufacture a high-uniformity indium ball array meeting the requirement of flip chip bonding with a readout circuit by using the manufacturing method of the high-uniformity indium ball array for an InGaAs/InP short-wave infrared focal plane photosensitive chip with a center distance of 10 microns, and to verify the feasibility of the invention.
Based on the InGaAs/InP focal plane photosensitive chip with the prepared p-contact electrode, the manufacturing method comprises the following steps:
(1) and adopting AZ4330 positive photoresist to generate a square contact electrode hole pattern in the center of the pixel through ultraviolet exposure and development. The pore side is 5.5 microns.
(2) And (3) evaporating three layers of metal of chromium plating, nickel plating and gold plating in sequence by adopting ion beam sputtering coating equipment, wherein the thicknesses of the three layers of metal are respectively 20 nm, 200 nm and 50 nm.
(3) And soaking in acetone to dissolve and remove the photoresist and strip the evaporated metal electrode structure.
(4) Deposition of SiN using inductively coupled chemical vapor deposition apparatusxFilm thickness 100 nm.
(5) And adopting AZ1500 positive photoresist, and generating a square contact hole pattern in the center of the pixel through ultraviolet exposure and development. The pore side length was 4.5 microns. The center of the contact hole is aligned with the center of the metal electrode in the previous step.
(6) Using reactive ion etching equipment, using SF4Gas is used as an etchant to etch and remove SiN in the contact hole pattern holesxAnd (5) film layer. Soaking in acetone, dissolving and removing photoresist, cleaning to obtain SiNxAnd (5) a contact hole structure.
(7) And an AZ4620 positive photoresist is adopted, and a circular indium hole pattern is generated through ultraviolet exposure and development, wherein the hole diameter is 5.5 microns, and the photoresist thickness is 6 microns. The center of the indium hole is aligned with the center of the contact electrode hole generated in the previous step.
(8) And evaporating an indium metal layer by adopting thermal evaporation equipment, wherein the thickness of the indium metal layer is 5.0 microns.
(9) And soaking by using acetone, dissolving and removing the photoresist, cleaning, and stripping to generate an indium column electrode structure to generate an indium column array.
(10) Adopting a heat flow furnace device, introducing formic acid steam, keeping the highest heat treatment temperature of 250 ℃ for 5 minutes, and keeping the highest temperature for 1 hour.
After the above steps are completed, the focal plane photosensitive chip is taken out from the reflow furnace, and a high-uniformity indium ball array with a center distance of 10 microns is obtained, wherein the appearance is shown in fig. 3. The indium balls have high shape consistency, large duty ratio, full shape, 5.5 microns of average diameter and high positioning precision, and meet the requirement of high connectivity rate reverse welding interconnected with a 10-micron center distance reading circuit.

Claims (1)

1. A method for manufacturing an indium ball array of a focal plane detector with small center distance is characterized by comprising the following steps:
1) coating photoresist on the chip, and generating an electrode hole pattern on the photoresist;
2) sequentially steaming three layers of metal of chromium plating, nickel and gold; the thickness of the chromium layer is 20-100nm, the thickness of the nickel layer is 200-600nm, and the thickness of the gold layer is 50-100 nm;
3) removing the photoresist to produce a metal electrode;
4) depositing a dielectric film layer, wherein the dielectric film layer is silicon nitride or silicon oxide, and the film thickness is 100-1000 nm;
5) coating photoresist and generating a contact hole pattern on the photoresist; the contact hole pattern is aligned with the metal electrode, the size of the contact hole is smaller than that of the metal electrode, and the contact hole pattern is square, circular or polygonal;
6) etching to remove the medium film in the hole and removing the photoresist; the dielectric film etching adopts plasma dry etching or hydrofluoric acid solution wet etching;
7) coating photoresist and generating an indium hole pattern on the photoresist; the indium hole pattern is aligned with the contact electrode hole, and the size of the indium hole pattern is larger than that of the metal electrode and smaller than the focal plane center distance. The shape is square, round or polygonal;
8) evaporating indium metal; the thickness of the indium metal vapor plating is less than that of the photoresist coated in the step 7);
9) removing the photoresist to generate an indium column array;
10) and carrying out thermal reflux treatment to generate an indium ball array, wherein the indium column thermal reflux process atmosphere is formic acid, and the process temperature is 200-250 ℃.
CN202010623570.1A 2020-07-01 2020-07-01 Indium ball array manufacturing method of focal plane detector with small center distance Pending CN111739806A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010623570.1A CN111739806A (en) 2020-07-01 2020-07-01 Indium ball array manufacturing method of focal plane detector with small center distance

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010623570.1A CN111739806A (en) 2020-07-01 2020-07-01 Indium ball array manufacturing method of focal plane detector with small center distance

Publications (1)

Publication Number Publication Date
CN111739806A true CN111739806A (en) 2020-10-02

Family

ID=72652344

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010623570.1A Pending CN111739806A (en) 2020-07-01 2020-07-01 Indium ball array manufacturing method of focal plane detector with small center distance

Country Status (1)

Country Link
CN (1) CN111739806A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113314556A (en) * 2021-05-28 2021-08-27 北京智创芯源科技有限公司 Focal plane detector and indium ball array preparation method thereof
CN113314555A (en) * 2021-04-12 2021-08-27 北京智创芯源科技有限公司 Preparation method of detector interconnection structure and detector
CN114512554A (en) * 2022-02-14 2022-05-17 浙江拓感科技有限公司 Preparation method of table-board type infrared detector indium dot matrix, infrared detector, focal plane array chip and reading circuit chip
CN115036390A (en) * 2022-04-24 2022-09-09 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） Method for preparing height-width ratio increased type welding point column, electronic device and infrared detector

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113314555A (en) * 2021-04-12 2021-08-27 北京智创芯源科技有限公司 Preparation method of detector interconnection structure and detector
CN113314556A (en) * 2021-05-28 2021-08-27 北京智创芯源科技有限公司 Focal plane detector and indium ball array preparation method thereof
CN113314556B (en) * 2021-05-28 2022-02-15 北京智创芯源科技有限公司 Focal plane detector and indium ball array preparation method thereof
CN114512554A (en) * 2022-02-14 2022-05-17 浙江拓感科技有限公司 Preparation method of table-board type infrared detector indium dot matrix, infrared detector, focal plane array chip and reading circuit chip
CN115036390A (en) * 2022-04-24 2022-09-09 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） Method for preparing height-width ratio increased type welding point column, electronic device and infrared detector
CN115036390B (en) * 2022-04-24 2024-03-26 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） Preparation method of high-width-ratio increased welding spot column, electronic device and infrared detector

Similar Documents

Publication Publication Date Title
CN111739806A (en) Indium ball array manufacturing method of focal plane detector with small center distance
US8456004B2 (en) Template wafer and process for small pitch flip-chip interconnect hybridization
CN106057834B (en) Color filter array deeply buried by stacked grid structure
CN108878296B (en) Preparation method of three-dimensional micro-convex point
US20100248399A1 (en) Method for manufacturing hybrid image sensors
US10658267B2 (en) Metal cored solder decal structure and process
US10983278B2 (en) Adhesion promoter apparatus and method
CN111755572B (en) Method for preparing indium salient point of infrared detector reading circuit and prepared reading circuit
CN110444607B (en) Large-scale indium gallium arsenic focal plane detector with stress balance layer and preparation method
CN111584368B (en) Method for forming concave points at top end of high-density micro indium column array for infrared focal plane device
Merken et al. Technology for very dense hybrid detector arrays using electroplated indium solderbumps
US8617997B2 (en) Selective wet etching of gold-tin based solder
US20040195516A1 (en) Indium features on multi-contact chips
CN110970314A (en) Micro-welding point interconnection method for graphical nanoparticles in chip packaging and product
WO2019160517A2 (en) A method for improving the flip-chip bonding process
CN110911394A (en) Packaging structure of terahertz focal plane detector and manufacturing method thereof
EP4207996A1 (en) Method of forming bumpless superconductor device
CN113502521B (en) Readout circuit module preparation method, seed layer removal method and bump preparation method
CN116936591A (en) III-V compound semiconductor 3D stack type image sensor bonding pad opening method
US20230317753A1 (en) Methods Of Forming Optical Modules
CN118073374A (en) Method for forming absorption enhancement structure of image sensor
CN115394738A (en) Method for manufacturing bonding welding spot
KR101542161B1 (en) The solder bump structure and method of fabricating the same
CN116092958A (en) Reflow balling process method for indium bumps
CN117832327A (en) Preparation method of high-thin indium bump, indium bump array and infrared detector

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination