CN113502521B - Readout circuit module preparation method, seed layer removal method and bump preparation method - Google Patents
Readout circuit module preparation method, seed layer removal method and bump preparation method Download PDFInfo
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- CN113502521B CN113502521B CN202110571739.8A CN202110571739A CN113502521B CN 113502521 B CN113502521 B CN 113502521B CN 202110571739 A CN202110571739 A CN 202110571739A CN 113502521 B CN113502521 B CN 113502521B
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- 239000004642 Polyimide Substances 0.000 claims abstract description 44
- 229920001721 polyimide Polymers 0.000 claims abstract description 44
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 23
- 238000000227 grinding Methods 0.000 claims abstract description 19
- 238000009713 electroplating Methods 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- 238000001259 photo etching Methods 0.000 claims abstract description 6
- 239000011248 coating agent Substances 0.000 claims abstract description 5
- 238000000576 coating method Methods 0.000 claims abstract description 5
- 239000010931 gold Substances 0.000 claims description 14
- 229910052738 indium Inorganic materials 0.000 claims description 11
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 10
- 229910052737 gold Inorganic materials 0.000 claims description 10
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 9
- 239000002131 composite material Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 4
- 238000002791 soaking Methods 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 3
- 150000002739 metals Chemical class 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 23
- 230000008569 process Effects 0.000 abstract description 15
- 235000012431 wafers Nutrition 0.000 description 16
- 238000010586 diagram Methods 0.000 description 6
- 238000005457 optimization Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000005498 polishing Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000010790 dilution Methods 0.000 description 2
- 239000012895 dilution Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004132 cross linking Methods 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
- C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/14—Metallic material, boron or silicon
- C23C14/16—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
- C23C14/165—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon by cathodic sputtering
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
- C23C14/35—Sputtering by application of a magnetic field, e.g. magnetron sputtering
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/58—After-treatment
- C23C14/5873—Removal of material
- C23C14/588—Removal of material by mechanical treatment
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/48—Electroplating: Baths therefor from solutions of gold
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/54—Electroplating: Baths therefor from solutions of metals not provided for in groups C25D3/04 - C25D3/50
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/02—Electroplating of selected surface areas
- C25D5/022—Electroplating of selected surface areas using masking means
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- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Electrochemistry (AREA)
- Mechanical Engineering (AREA)
- Electroplating Methods And Accessories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention provides a method for removing a seed layer of a read-out circuit module, which comprises the following steps: coating polyimide on the surface of a readout circuit wafer, and photoetching the polyimide to form a plurality of sequentially-spaced pits; growing a seed layer on the surfaces of the polyimide and the pit; covering photoresist on the seed layer on the upper surface of polyimide; electroplating convex points on the seed layer in the deep pits to fill the deep pits with the convex points; and removing the photoresist, and grinding to remove the seed layer on the upper surface of the polyimide. The invention also provides a preparation method of the readout circuit module bump, which comprises the method for removing the seed layer of the readout circuit module. The preparation method of the read-out circuit module comprises the step of obtaining the read-out circuit module salient points by the preparation method of the read-out circuit module salient points. The invention can avoid the problems of the speed difference of the traditional etching process and the damage of a read-out circuit, and can ensure the complete removal of the seed layer metal by controlling the grinding thickness.
Description
Technical Field
The invention relates to the technical field of infrared detectors, in particular to a read-out circuit module preparation method, a seed layer removal method and a bump preparation method.
Background
Miniaturization of pixel size is one of the important development directions of infrared detectors. The small-size pixel can obviously improve the imaging resolution without increasing the area array scale, thereby improving the performance of an infrared system. One of the significant difficulties in reducing the pixel size at the process end is that the difficulty in preparing the interconnection bumps between the sensitive chip end and the readout circuit end is increased, and the electrical interconnection failure rate of the sensitive chip end and the readout circuit end is improved.
To realize interconnection between a sensitive chip and a readout circuit, the shape, size and uniformity of the salient points are required to meet certain requirements, when the pixel size of the chip is reduced, the traditional salient point preparation mode, such as indium column reflow balling after vapor deposition, can lead to abnormal indium balls with substandard indium column heights after reflow due to poor uniformity of the size of the salient points obtained by vapor deposition, so that interconnection failure is caused.
In addition, for small-size electroplating patterns, the bottom of the electroplating patterns is easy to fall off due to transverse under-etching while the seed layer is etched due to the inherent isotropy characteristic of the traditional wet etching, and the traditional dry etching process avoids the condition of transverse under-etching, but for workpieces with electric functions, such as infrared detector readout circuit wafers, the etching rate difference exists between patterns with different line widths under the same etching condition, and the etching rate is reduced along with the reduction of line widths. Therefore, to ensure complete etching of the seed layer, over etching of the entire pattern is required. At this time, the large pattern area is very easy to cause the function damage of the device due to the overlarge etching depth. In addition, the photoresist is easy to generate crosslinking deformation due to high-energy plasma bombardment in the etching process, the photoresist removing difficulty after etching is high, and the photoresist residue phenomenon is easy to occur, so that the subsequent process is influenced.
Disclosure of Invention
The invention aims to provide a read-out circuit module preparation method, a seed layer removal method and a bump preparation method, which at least can solve part of defects in the prior art.
In order to achieve the above object, the embodiment of the present invention provides the following technical solutions: a method for removing seed layer of read-out circuit module includes the following steps:
coating polyimide on the surface of a readout circuit wafer, and photoetching the polyimide to form a plurality of sequentially-spaced pits;
growing a seed layer on the surfaces of the polyimide and the pit;
covering photoresist on the seed layer on the upper surface of the polyimide;
electroplating convex points on the seed layer in the deep pits to enable the convex points to fill the deep pits;
and removing the photoresist, and grinding to remove the seed layer on the upper surface of the polyimide.
Further, the pit depth is 8+ -0.2 μm and the pit aspect ratio is 2:1.
Further, the pit pitch is the same as the pit depth.
Further, the seed layer is titanium/gold composite metal, and the bump is gold/indium composite metal.
Further, the gold to indium thickness ratio is 3:5.
And further, growing a seed layer on the surfaces of the polyimide and the pit by using a magnetron sputtering mode, wherein the thickness of the grown seed layer is 200-400 nm.
Further, the seed layer on the upper surface of the polyimide is removed by grinding, and the heights of the polyimide and the protruding points are controlled to be not less than 7.5 mu m.
Further, after forming a plurality of the pits, baking cures the polyimide.
The embodiment of the invention provides another technical scheme that: the method for preparing the convex points of the readout circuit module comprises the step of removing the seed layer of the readout circuit module, and the step of removing the polyimide after the seed layer on the upper surface of the polyimide is polished.
The embodiment of the invention provides another technical scheme that: a method of manufacturing a readout circuit module, comprising the steps of: after the readout circuit module salient points are obtained through the readout circuit module salient point preparation method, the readout circuit module which can be interconnected with the sensitive chip is obtained through soaking, cutting and cleaning by dilute hydrochloric acid.
Compared with the prior art, the invention has the beneficial effects that:
1. the seed layer is thoroughly removed. The seed layer is removed by adopting a mechanical grinding mode aiming at the structure obtained by the bump electroplating technology, so that the problems of speed difference of the traditional etching process and damage of a read-out circuit are avoided, and meanwhile, the metal of the seed layer is completely removed by controlling the grinding thickness.
2. The indium column electroplating technology can well solve the problem of poor uniformity of evaporation bumps, bumps obtained by electroplating are full and uniform, flip-chip interconnection difficulty is remarkably reduced, and accordingly interconnection success rate is improved.
3. The uniformity of the electroplated patterns is high. The mechanical polishing planarizes the plane of the bump top, and the technique can achieve 100% uniformity of the electroplated pattern.
Drawings
Fig. 1 is a schematic diagram of step S1 of a readout circuit module seed layer removal method according to an embodiment of the present invention;
fig. 2 is a schematic diagram of step S2 of a readout circuit module seed layer removal method according to an embodiment of the present invention;
fig. 3 is a schematic diagram of step S3 of a readout circuit module seed layer removal method according to an embodiment of the present invention;
fig. 4 is a schematic diagram of step S4 of a readout circuit module seed layer removal method according to an embodiment of the present invention;
fig. 5 is a schematic diagram of step S5 of a readout circuit module seed layer removal method according to an embodiment of the present invention;
fig. 6 is a schematic diagram of step S6 of a readout circuit module seed layer removal method according to an embodiment of the present invention;
in the reference numerals: 1-reading out a circuit wafer; 2-polyimide; 3-pit; 4-seed layer; 5-photoresist; and 6-protruding points.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1 to 6, an embodiment of the invention provides a method for removing a seed layer of a readout circuit module, which includes the following steps: s1, coating polyimide 2 on the surface of a readout circuit wafer 1, and photoetching the polyimide 2 to form a plurality of sequentially-spaced deep pits 3; s2, growing a seed layer 4 on the surfaces of the polyimide 2 and the pit 3; s3, covering the seed layer 4 on the upper surface of the polyimide 2 with photoresist 5; s4, electroplating a bump 6 on the seed layer 4 in the pit 3, so that the pit 3 is filled with the bump 6; and S5, removing the photoresist 5, and grinding to remove the seed layer 4 on the upper surface of the polyimide 2. In the prior art, the bump 6 prepared by electroplating has different flatness on the upper surface of the bump 6, and the conventional etching process is difficult to achieve high flatness, because the etching rate is slow along with the line width reduction under the same etching condition, so that the whole pattern needs to be over-etched in order to ensure the complete etching of the seed layer, and the large pattern area is extremely easy to cause the functional damage of the device due to the overlarge etching depth. In this embodiment, for the structure obtained by the bump electroplating technology, the seed layer is removed by adopting a mechanical polishing mode, so that the problems of speed difference of the traditional etching process and damage of a readout circuit are avoided, meanwhile, the metal of the seed layer can be completely removed by controlling the polishing thickness, the plane of the top of the bump 6 can be flattened by mechanical polishing, and the uniformity of the electroplating pattern can reach 100%.
As an optimization scheme of the embodiment of the invention, the depth of the pit is 8+/-0.2 mu m, and the depth-to-width ratio of the pit is 2:1. In this embodiment, the depth of the defined pit is 8±0.2 μm, the distance between the adjacent "pits" is 8 μm, and then the size of the bump formed by electroplating matching with the pit will be in micron order, in the process of preparing the bump with such small size, the process requirement is very high, for the processing modes with different flatness on the bump with small size, the conventional etching technology cannot meet the etching requirement, and damage is often brought, but the defect can be solved by adopting the grinding mode. Preferably, the pit pitch is the same as the pit depth, and the resulting bumps are symmetrical.
As an optimization scheme of the embodiment of the present invention, referring to fig. 1 to 6, in step S1, after the pit 3 is obtained, the polyimide 2 is cured by baking at a high temperature, so as to facilitate subsequent growth and grinding. In this example, the baking conditions were 300 ℃/30min.
As an optimization scheme of the embodiment of the present invention, referring to fig. 1 to 6, in step S2, the seed layer 4 is specifically a titanium/gold composite metal prepared by magnetron sputtering. In this embodiment, the seed layer 4 is a titanium/gold composite metal, and the thickness of the grown seed layer is 200-400 nm. Wherein, ti=30 nm and Au=300 nm, and the resistance value of the two ends of the diameter of the wafer is not more than 0.5 omega.
As an optimization scheme of the embodiment of the present invention, referring to fig. 1 to 6, in the step S3, the covering photoresist 5 includes a photoresist coating, baking, exposing, and developing process.
As an optimization scheme of the embodiment of the present invention, referring to fig. 1 to 6, in step S4, electroplating operation is performed by using electroplating equipment, the obtained bump 6 is gold/indium composite metal, and then the photoresist in step S3 is removed through a cleaning chamber of the equipment. Preferably, the gold to indium thickness ratio is 3:5. The bump height is 3 μm for Au layer and 5 μm for In layer.
As an optimization scheme of the embodiment of the present invention, referring to fig. 1 to 6, in the step S5, the seed layer on the upper surface of the polyimide is polished and removed, and the heights of the polyimide and the bump are controlled to be not less than 7.5 μm. In this embodiment, the readout circuitry wafer is then cleaned to remove the stickers, and finally the readout circuitry wafer is subjected to polyimide 2 removal on a photoresist stripper.
The embodiment of the invention provides a method for preparing a bump of a readout circuit module, which comprises the method for removing a seed layer of the readout circuit module, and further comprises the step S6 of removing polyimide after grinding the seed layer on the upper surface of polyimide, and then processing an oxide layer on a wafer to obtain the bump 6. In the step S6, the polyimide 2 is removed by oxygen plasma in a photoresist stripper, and the wafer is treated with dilute hydrochloric acid for oxide layer. In this embodiment, the key step in bump array fabrication is insulation lithography between pixels, and mechanical polishing removes the seed layer. Because the bump size is smaller, the 'pit' pattern generally has a larger depth-to-width ratio, photoresist at the pit bottom needs to be thoroughly developed during insulating lithography, and in addition, for small-size pixels, the bump is extremely easy to damage by a wet seed layer removing method, and the function of a read-out circuit is easy to be abnormal by a dry method, so that a seed layer removing method which is small in damage and easy to control is provided by a mechanical grinding process, and the bump higher than the 'pit' surface can be trimmed during the grinding process, and the height uniformity of the bump is improved. Preferably, the hydrochloric acid dilution ratio (volume ratio) is hydrochloric acid: deionized water=1:9, treatment time was 20s.
The specific implementation mode is as follows: designing a photomask, performing polyimide photoetching on the surface of a wafer to obtain an array of 'pit' patterns, and baking the wafer at high temperature to solidify the patterns; plating a seed layer on the surface of the wafer, wherein Ti/Au=30/300 (nm); photoetching the surface of the wafer by adopting a photomask in the first step, wherein the photoresist layer has the function of enabling the adjacent 'deep pits' to be in an insulating state, removing a bottom film after finishing, and removing residues of the photoresist at the bottoms of the 'deep pits'; electroplating the indium column, wherein the plating structure is Au/In=3/5 (mu m), and then removing the photoresist; grinding the electroplated wafer after photoresist removal on a grinder, removing the seed layer between the convex points to expose polyimide, wherein the residual thickness of the polyimide is not less than 7.5 mu m; and (3) putting the wafer into a photoresist remover, removing polyimide by using O2 plasma, and then soaking the wafer for 20s by using diluted hydrochloric acid with the dilution of 10 times to remove an oxide layer on the surface of the salient point.
The embodiment of the invention provides a preparation method of a read-out circuit module, which comprises the following steps: after the circuit module salient points 6 are obtained through the method for preparing the read-out circuit module salient points, the read-out circuit module which can be interconnected with the sensitive chip is obtained through soaking, cutting and cleaning by dilute hydrochloric acid. In this embodiment, the method for manufacturing the bump of the readout circuit module uses a mechanical grinding method to remove the seed layer, so that the problems of speed difference of the traditional etching process and damage of the readout circuit are avoided, meanwhile, the metal of the seed layer can be completely removed by controlling the grinding thickness, the plane of the top of the bump 6 can be flattened by mechanical grinding, and the uniformity of the electroplating pattern can reach 100%. In the small-size bump preparation process, the process requirement is very high, for the processing modes with different flatness on the small-size bumps, the conventional etching technology cannot meet the etching requirement, damage is often brought, and the defect can be overcome by adopting a grinding mode.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (10)
1. A method for removing a seed layer of a readout circuit module, comprising the steps of:
coating polyimide on the surface of a readout circuit wafer, and photoetching the polyimide to form a plurality of sequentially-spaced pits;
growing a seed layer on the surfaces of the polyimide and the pit;
covering photoresist on the seed layer on the upper surface of the polyimide;
electroplating convex points on the seed layer in the deep pits to enable the convex points to fill the deep pits;
and removing the photoresist, and grinding to remove the seed layer on the upper surface of the polyimide.
2. The readout circuitry module seed layer removal method of claim 1, wherein the pit depth is 8±0.2 μm and the pit aspect ratio is 2:1.
3. The readout circuitry module seed layer removal method of claim 2, wherein the pit pitch is the same as the pit depth.
4. A method of removing a seed layer from a readout circuit module according to any one of claims 1 to 3, wherein the seed layer is a titanium/gold composite metal and the bumps are gold/indium composite metals.
5. The method of claim 4, wherein the gold to indium thickness ratio is 3:5.
6. The method of removing seed layer of readout circuit module according to claim 1, wherein seed layer is grown on the polyimide and the pit surface by magnetron sputtering, and the thickness of the grown seed layer is 200 to 400nm.
7. The method of removing seed layer of readout circuit module according to claim 1, wherein the seed layer on the upper surface of the polyimide is polished off, and the polyimide and the bump height are controlled to be not less than 7.5 μm.
8. The readout circuitry module seed layer removal method of claim 1, wherein after forming a plurality of the pits, baking cures the polyimide.
9. A method for producing a bump of a readout circuit module, comprising the method for removing a seed layer of a readout circuit module according to any one of claims 1 to 8, and removing the polyimide after grinding the seed layer on the upper surface of the polyimide.
10. A method of manufacturing a readout circuit module, comprising the steps of: after the readout circuit module bump is obtained by the readout circuit module bump preparation method according to claim 9, the readout circuit module which can be interconnected with the sensitive chip is obtained by soaking, dicing and cleaning with dilute hydrochloric acid.
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| KR20050036464A (en) * | 2003-10-16 | 2005-04-20 | 삼성테크윈 주식회사 | Method for forming bump on wafer and semiconductor package with bump formed thereby |
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| CN102856213A (en) * | 2012-08-24 | 2013-01-02 | 中国兵器工业集团第二一四研究所苏州研发中心 | Thin film multilayer wiring manufacturing method based on LTCC (Low Temperature Co-Fired Ceramic) base plate |
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