CN113502521A - Method for removing electroplating seed layer of read circuit module and method for preparing salient point - Google Patents
Method for removing electroplating seed layer of read circuit module and method for preparing salient point Download PDFInfo
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- CN113502521A CN113502521A CN202110571739.8A CN202110571739A CN113502521A CN 113502521 A CN113502521 A CN 113502521A CN 202110571739 A CN202110571739 A CN 202110571739A CN 113502521 A CN113502521 A CN 113502521A
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- 238000000034 method Methods 0.000 title claims abstract description 56
- 238000009713 electroplating Methods 0.000 title claims abstract description 32
- 239000004642 Polyimide Substances 0.000 claims abstract description 44
- 229920001721 polyimide Polymers 0.000 claims abstract description 44
- 238000000227 grinding Methods 0.000 claims abstract description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- 238000001259 photo etching Methods 0.000 claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- 239000011248 coating agent Substances 0.000 claims abstract description 5
- 238000000576 coating method Methods 0.000 claims abstract description 5
- 239000010931 gold Substances 0.000 claims description 14
- 238000007747 plating Methods 0.000 claims description 13
- 229910052738 indium Inorganic materials 0.000 claims description 11
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 10
- 229910052737 gold Inorganic materials 0.000 claims description 10
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 9
- 239000002131 composite material Substances 0.000 claims description 7
- 239000010936 titanium Substances 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 3
- 238000002791 soaking Methods 0.000 claims description 3
- 238000005406 washing Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 19
- 230000008569 process Effects 0.000 abstract description 14
- 235000012431 wafers Nutrition 0.000 description 15
- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 238000002360 preparation method Methods 0.000 description 6
- 239000000243 solution Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 238000010790 dilution Methods 0.000 description 2
- 239000012895 dilution Substances 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004132 cross linking Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 229910052760 oxygen Inorganic materials 0.000 description 1
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- 238000006467 substitution reaction Methods 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
- C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/14—Metallic material, boron or silicon
- C23C14/16—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
- C23C14/165—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon by cathodic sputtering
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
- C23C14/35—Sputtering by application of a magnetic field, e.g. magnetron sputtering
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/58—After-treatment
- C23C14/5873—Removal of material
- C23C14/588—Removal of material by mechanical treatment
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/48—Electroplating: Baths therefor from solutions of gold
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/54—Electroplating: Baths therefor from solutions of metals not provided for in groups C25D3/04 - C25D3/50
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/02—Electroplating of selected surface areas
- C25D5/022—Electroplating of selected surface areas using masking means
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- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Electrochemistry (AREA)
- Mechanical Engineering (AREA)
- Electroplating Methods And Accessories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The invention provides a method for removing an electroplating seed layer of a read circuit module, which comprises the following steps: coating polyimide on the surface of a read circuit wafer, and photoetching the polyimide to form a plurality of sequentially spaced deep pits; growing a seed layer on the surfaces of the polyimide and the deep pit; covering photoresist on the seed layer on the upper surface of the polyimide; electroplating a convex point on the seed layer in the deep pit to fill the deep pit with the convex point; and removing the photoresist, and grinding to remove the seed layer on the upper surface of the polyimide. The method for preparing the salient point of the reading circuit module comprises the method for removing the electroplating seed layer of the reading circuit module. A manufacturing method of a reading circuit module comprises the step of obtaining a reading circuit bump by the reading circuit bump manufacturing method. The method avoids the problems of rate difference and circuit damage of the traditional etching process, and can ensure that the seed layer metal is completely removed by controlling the grinding thickness.
Description
Technical Field
The invention relates to the technical field of infrared detectors, in particular to a method for removing an electroplating seed layer of a reading circuit module and a method for preparing a salient point.
Background
The miniaturization of the pixel size is one of the important development directions of the infrared detector. The small-size pixel can obviously improve the imaging resolution ratio under the condition of not increasing the area array scale, thereby improving the performance of an infrared system. One of the major problems brought by the reduction of the pixel size at the process end is that the difficulty in preparing the interconnection bumps at the sensitive chip end and the read-out circuit end is increased, and further the electrical interconnection failure rate of the sensitive chip end and the read-out circuit end is also improved.
When the size of a chip pixel is reduced, the traditional bump preparation method, such as indium column backflow balling after evaporation, can cause abnormal indium balls with unqualified heights after indium column backflow due to poor size uniformity of the bump obtained by evaporation, thereby causing interconnection failure.
In addition, for small-size electroplating patterns, due to the inherent isotropic characteristic of the traditional wet etching, the bottom of the electroplating pattern is easy to drop due to transverse underetching while the seed layer is etched, and although the traditional dry etching process avoids the condition of transverse underetching, for workpieces with electrical functions, such as infrared detector read circuit wafers, different line width patterns have etching rate differences, and the etching rate is reduced along with the reduction of line width under the same etching condition. Therefore, to ensure that the seed layer is completely etched, the entire pattern needs to be over-etched. At this time, the large pattern area is easy to damage the function of the device due to the overlarge etching depth. In addition, the photoresist is easy to generate cross-linking deformation due to bombardment of high-energy plasma in the etching process, the photoresist removing difficulty after the etching is finished is high, and the photoresist residue phenomenon is easy to occur, so that the subsequent process is influenced.
Disclosure of Invention
The invention aims to provide a method for removing an electroplating seed layer of a reading circuit module and a method for preparing a salient point, which can at least solve part of defects in the prior art.
In order to achieve the above purpose, the embodiments of the present invention provide the following technical solutions: a method for preparing a salient point of a reading circuit comprises the following steps:
a method for preparing a salient point of a reading circuit comprises the following steps:
coating polyimide on the surface of a read circuit wafer, and photoetching the polyimide to form a plurality of sequentially spaced deep pits;
growing a seed layer on the polyimide and the deep pit surface;
covering photoresist on the seed layer on the upper surface of the polyimide;
electroplating a convex point on the seed layer in the deep pit to fill the deep pit with the convex point;
and removing the photoresist, and grinding to remove the seed layer on the upper surface of the polyimide.
Further, the depth of the deep pit is 8 +/-0.2 mu m, and the depth-to-depth ratio of the deep pit is 2: 1.
Further, the pit pitch is the same as the pit depth.
Further, the seed layer is made of titanium/gold composite metal, and the salient points are made of gold/indium composite metal.
Further, the ratio of the thickness of the gold to the thickness of the indium is 3: 5.
Further, a seed layer is grown on the surfaces of the polyimide and the deep pit in a magnetron sputtering mode, and the thickness of the grown seed layer is 200-400 nm.
Further, grinding to remove the seed layer on the upper surface of the polyimide, and controlling the height of the polyimide and the salient point to be not less than 7.5 μm.
Further, after forming a plurality of the pits, baking is performed to cure the polyimide.
The embodiment of the invention provides another technical scheme: a method for preparing a salient point of a reading circuit module is characterized by comprising the method for removing the electroplating seed layer of the reading circuit module, wherein the polyimide is removed after the seed layer on the upper surface of the polyimide is ground.
The embodiment of the invention provides another technical scheme: a method of making a readout circuit, comprising the steps of: after the read circuit bump is obtained by the read circuit bump preparation method, the read circuit bump is soaked, cut and cleaned by dilute hydrochloric acid to obtain the read circuit module which can be interconnected with the sensitive chip.
Compared with the prior art, the invention has the beneficial effects that:
1. the seed layer was removed completely. Aiming at the structure obtained by the electroplating salient point technology, the seed layer is removed by adopting a mechanical grinding mode, so that the problem of the rate difference of the traditional etching process and the problem of the damage of a reading circuit are avoided, and meanwhile, the complete removal of the metal of the seed layer can be ensured by controlling the grinding thickness.
2. The indium column electroplating technology can well solve the problem of poor uniformity of evaporated bumps, the bumps obtained by electroplating are full and uniform, the flip interconnection difficulty is obviously reduced, and the interconnection success rate is improved.
3. The uniformity of the electroplating pattern is high. The mechanical grinding can flatten the plane of the top of the salient point, and the uniformity of the electroplating pattern can reach 100 percent.
Drawings
Fig. 1 is a schematic diagram of a step S1 of a method for removing a plating seed layer of a readout circuit module according to an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating a step S2 of a method for removing a plating seed layer of a readout circuit module according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating a step S3 of a method for removing a plating seed layer of a readout circuit module according to an embodiment of the present invention;
fig. 4 is a schematic diagram illustrating a step S4 of a method for removing a plating seed layer of a readout circuit module according to an embodiment of the present invention;
fig. 5 is a schematic diagram illustrating a step S5 of a method for removing a plating seed layer of a readout circuit module according to an embodiment of the present invention;
fig. 6 is a schematic diagram illustrating a step S6 of a method for removing a plating seed layer of a readout circuit module according to an embodiment of the present invention;
in the reference symbols: 1-a read-out circuit die; 2-polyimide; 3-pit deepening; 4-seed layer; 5-photoresist; 6-salient points.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1 to 6, an embodiment of the invention provides a method for removing a plating seed layer of a readout circuit, including the following steps: s1, coating polyimide 2 on the surface of the readout circuit wafer 1, and photoetching the polyimide 2 to form a plurality of sequentially spaced deep pits 3; s2, growing a seed layer 4 on the surfaces of the polyimide 2 and the deep pits 3; s3, covering a photoresist 5 on the seed layer 4 on the upper surface of the polyimide 2; s4, electroplating a bump 6 on the seed layer 4 in the pit 3, so that the pit 3 is filled with the bump 6; and S5, removing the photoresist 5, and grinding to remove the seed layer 4 on the upper surface of the polyimide 2. In the prior art, the bumps 6 prepared by electroplating have different surface flatness on the bumps 6, and a conventional etching process is difficult to achieve high flatness, because the etching rate is slowed down along with the reduction of the line width under the same etching condition, the whole pattern needs to be over-etched to ensure the complete etching of the seed layer, and at the moment, the function of a device is easily damaged in a large pattern area due to the overlarge etching depth. In the embodiment, the seed layer is removed by adopting a mechanical grinding mode aiming at the structure obtained by the electroplating bump technology, so that the problems of speed difference of the traditional etching process and circuit damage are solved, meanwhile, the metal of the seed layer can be completely removed by controlling the grinding thickness, the plane where the top of the bump 6 is located can be flattened by mechanical grinding, and the uniformity of an electroplating pattern can reach 100 percent by adopting the technology.
As an optimization scheme of the embodiment of the invention, the depth of the deep pit is 8 +/-0.2 mu m, and the depth-to-width ratio of the deep pit is 2: 1. In this embodiment, the depth of the limited pit is 8 ± 0.2 μm, and the distance between adjacent "pits" is 8 μm, so the size of the bump made by electroplating matched with the limited pit will also be in micron order, and in the bump preparation process with such small size, the process requirement is very high, and for the processing modes with different flatness on the small-size bump, the conventional etching technology cannot meet the etching requirement, which often causes damage, and the defect can be solved by adopting a grinding mode. Preferably, the pitch of the pits is the same as the depth of the pits, and the obtained bumps are uniform.
As an optimization scheme of the embodiment of the present invention, referring to fig. 1 to 6, in the step S1, after the deep pits 3 are obtained, the polyimide 2 is cured by high temperature baking, so as to facilitate subsequent growth and grinding. In this example, the baking conditions were 300 ℃/30 min.
Referring to fig. 1 to 6 as an optimized scheme of the embodiment of the present invention, in the step S2, the seed layer 4 is specifically a titanium/gold composite metal prepared by a magnetron sputtering method. In the embodiment, the seed layer 4 is a titanium/gold composite metal, and the thickness of the grown seed layer is 200-400 nm. Wherein, Ti is 30nm, Au is 300nm, and the resistance value at two ends of the diameter of the wafer is not more than 0.5 omega.
Referring to fig. 1 to 6 as an optimized solution of the embodiment of the present invention, in the step S3, the covering photoresist 5 includes processes of coating, baking, exposing, and developing.
Referring to fig. 1 to 6 as an optimized solution of the embodiment of the present invention, in the step S4, an electroplating device is used to perform an electroplating operation to obtain a gold/indium composite metal bump 6, and then the photoresist in S3 is removed through a cleaning chamber of the device. Preferably, the ratio of gold to indium thickness is 3: 5. The height of the bump was 3 μm for the Au layer and 5 μm for the In layer.
As an optimized solution of the embodiment of the present invention, referring to fig. 1 to 6, in the step S5, the seed layer on the upper surface of the polyimide is removed by grinding, and the heights of the polyimide and the bump are controlled to be not less than 7.5 μm. In this embodiment, the readout circuit wafer is cleaned to remove the adhesive, and finally the readout circuit wafer is removed by the polyimide 2 on the degumming machine.
The embodiment of the invention provides a method for preparing a salient point of a read-out circuit module, which comprises the method for removing the electroplating seed layer of the read-out circuit module and the step S6, wherein the step S comprises the steps of removing the polyimide after the seed layer on the upper surface of the polyimide is ground, and then processing the oxide layer on a wafer to obtain the salient point 6. In the S6 step, the polyimide 2 is removed by oxygen plasma in a resist remover, and the wafer is treated with dilute hydrochloric acid for an oxide layer. In this embodiment, the key step of the bump array preparation is the insulation lithography between pixels, and the mechanical grinding is performed to remove the seed layer. Because the size of the salient point is smaller, the figure of the 'deep pit' generally has larger depth-to-width ratio, the photoresist at the bottom of the pit needs to be ensured to be developed thoroughly during insulation photoetching, in addition, for the small-size pixel, the mode of removing the seed layer by a wet method is easy to cause the damage of the salient point, and the self function of a reading circuit is easy to cause abnormity by a dry method, so the grinding process based on a mechanical mode provides the method for removing the seed layer with small damage and easy control, and the grinding process can also achieve the effect of trimming the salient point higher than the surface of the 'deep pit', thereby improving the height uniformity of the salient point. Preferably, the dilution ratio (volume ratio) of the hydrochloric acid is hydrochloric acid: deionized water at 1:9 for 20 s.
The specific implementation mode is as follows: designing a photomask, carrying out polyimide photoetching on the surface of the wafer to obtain an array of 'deep pit' patterns, and baking the wafer at high temperature to solidify the patterns; plating a seed layer on the surface of the wafer, wherein Ti/Au is 30/300 (nm); photoetching the surface of the wafer by adopting the photomask in the first step, wherein the photoresist layer has the function of enabling adjacent 'deep pits' to be in an insulating state, removing the bottom film after the photoetching is finished, and removing the residues of the photoresist at the bottoms of the 'deep pits'; indium column electroplating, wherein the plating structure is Au/In-3/5 (mum), and then removing the photoresist; grinding the electroplated and photoresist-removed wafer on a grinding machine, removing the seed layer between the salient points to expose polyimide, wherein the residual thickness of the polyimide is not less than 7.5 mu m; and putting the wafer into a degumming machine, removing polyimide by using O2 plasma, and then soaking the wafer for 20s by using diluted hydrochloric acid with 10 times of dilution to remove an oxide layer on the surface of the salient point.
The embodiment of the invention provides a preparation method of a reading circuit module, which comprises the following steps: after the circuit bump 6 is obtained by the above method for preparing the read circuit module bump, the read circuit module which can be interconnected with the sensitive chip is obtained by soaking, cutting and cleaning with dilute hydrochloric acid. In this embodiment, by using the above method for manufacturing a salient point of a readout circuit module, the seed layer is removed by mechanical grinding, so that the problems of rate difference of the conventional etching process and damage of the readout circuit are avoided, and meanwhile, the metal of the seed layer can be completely removed by controlling the grinding thickness, the plane where the top of the salient point 6 is located can be flattened by mechanical grinding, and the uniformity of the electroplating pattern can reach 100%. In the preparation process of the small-sized salient points, the process requirement is very high, and for processing modes with different flatness on the small-sized salient points, the conventional etching technology cannot meet the etching requirement and often causes damage, and the defect can be solved by adopting a grinding mode.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (10)
1. A method for removing an electroplating seed layer of a read circuit module is characterized by comprising the following steps:
coating polyimide on the surface of a read circuit wafer, and photoetching the polyimide to form a plurality of sequentially spaced deep pits;
growing a seed layer on the polyimide and the deep pit surface;
covering photoresist on the seed layer on the upper surface of the polyimide;
electroplating a convex point on the seed layer in the deep pit to fill the deep pit with the convex point;
and removing the photoresist, and grinding to remove the seed layer on the upper surface of the polyimide.
2. The method for removing the electroplating seed layer of the readout circuit module as claimed in claim 1, wherein the depth of the deep pit is 8 ± 0.2 μm, and the aspect ratio of the deep pit is 2: 1.
3. The method of removing a plating seed layer of a readout circuitry module of claim 2, wherein the pitch of the pits is the same as the depth of the pits.
4. The method for removing the electroplating seed layer of the readout circuit module as claimed in any one of claims 1 to 3, wherein the seed layer is made of titanium/gold composite metal, and the bump is made of gold/indium composite metal.
5. The method for removing the electroplating seed layer of the readout circuit module as claimed in claim 4, wherein the ratio of the thickness of gold to the thickness of indium is 3: 5.
6. The method for removing the electroplating seed layer of the readout circuit module as claimed in claim 1, wherein a seed layer is grown on the polyimide and the surface of the deep pit by magnetron sputtering, and the thickness of the grown seed layer is 200-400 nm.
7. The method for removing a plating seed layer of a readout circuit module as claimed in claim 1, wherein the seed layer on the upper surface of the polyimide is removed by grinding, and the height of the polyimide and the bump is controlled to be not less than 7.5 μm.
8. The method for removing a plating seed layer of a readout circuit module according to claim 1, wherein after the plurality of pits are formed, the polyimide is cured by baking.
9. A method for manufacturing a bump of a readout circuit module, comprising the method for removing a plating seed layer of a readout circuit module according to any one of claims 1 to 8, wherein the polyimide is removed after the seed layer on the upper surface of the polyimide is ground.
10. A method for manufacturing a readout circuit module is characterized by comprising the following steps: the method of manufacturing a readout circuit bump according to claim 9, soaking in dilute hydrochloric acid, dicing, and washing to obtain a readout circuit module capable of being interconnected with a sensitive chip.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050036464A (en) * | 2003-10-16 | 2005-04-20 | 삼성테크윈 주식회사 | Method for forming bump on wafer and semiconductor package with bump formed thereby |
| JP2008251750A (en) * | 2007-03-29 | 2008-10-16 | Yamaha Corp | Forming method of bump for electric connection |
| CN101847592A (en) * | 2010-04-09 | 2010-09-29 | 中国科学院上海微系统与信息技术研究所 | Indium welded ball array preparing method based on electroplating technology |
| CN102856213A (en) * | 2012-08-24 | 2013-01-02 | 中国兵器工业集团第二一四研究所苏州研发中心 | Thin film multilayer wiring manufacturing method based on LTCC (Low Temperature Co-Fired Ceramic) base plate |
| CN110660690A (en) * | 2019-09-29 | 2020-01-07 | 中国电子科技集团公司第十一研究所 | Method for preparing indium salient point of infrared detector reading circuit |
| CN111312656A (en) * | 2020-03-03 | 2020-06-19 | 西安微电子技术研究所 | Pretreatment method before chemical mechanical polishing of TSV blind hole electrocoppering hard warping wafer |
| CN111755572A (en) * | 2020-06-24 | 2020-10-09 | 中国电子科技集团公司第十一研究所 | Method for preparing indium salient points of infrared detector reading circuit and prepared reading circuit |
-
2021
- 2021-05-25 CN CN202110571739.8A patent/CN113502521B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050036464A (en) * | 2003-10-16 | 2005-04-20 | 삼성테크윈 주식회사 | Method for forming bump on wafer and semiconductor package with bump formed thereby |
| JP2008251750A (en) * | 2007-03-29 | 2008-10-16 | Yamaha Corp | Forming method of bump for electric connection |
| CN101847592A (en) * | 2010-04-09 | 2010-09-29 | 中国科学院上海微系统与信息技术研究所 | Indium welded ball array preparing method based on electroplating technology |
| CN102856213A (en) * | 2012-08-24 | 2013-01-02 | 中国兵器工业集团第二一四研究所苏州研发中心 | Thin film multilayer wiring manufacturing method based on LTCC (Low Temperature Co-Fired Ceramic) base plate |
| CN110660690A (en) * | 2019-09-29 | 2020-01-07 | 中国电子科技集团公司第十一研究所 | Method for preparing indium salient point of infrared detector reading circuit |
| CN111312656A (en) * | 2020-03-03 | 2020-06-19 | 西安微电子技术研究所 | Pretreatment method before chemical mechanical polishing of TSV blind hole electrocoppering hard warping wafer |
| CN111755572A (en) * | 2020-06-24 | 2020-10-09 | 中国电子科技集团公司第十一研究所 | Method for preparing indium salient points of infrared detector reading circuit and prepared reading circuit |
Non-Patent Citations (1)
| Title |
|---|
| 李高明 等: "阵列式日盲紫外成像CMOS读出集成电路及凸点连接的制作", 红外, vol. 30, no. 3, pages 7 - 17 * |
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